BIDES: A BIST design expert system

BIDES is an expert system for incorporating BIST into a hardware design that is described in VHDL. Based on the BILBO technique, the BIDES system allocates pseudorandom pattern generators and signature analysis registers to each combinational logic module in a design in such a way that given constraints on testing time and hardware overhead are satisfied. This assignment is performed using the iterative process of regeneration and evaluation of various BIST implementations. In order to effectively perform regeneration, an abstraction hierarchy for a BIST design is introduced and a hierarchical planning technique is employed using this structure. This formulation also leads to an easily modifiable system. Prolog is used for implementing the system.Now with Samsung Electronics, Chase Plaza Bldg. SF, 34–35 Jeong-Dong, Choong-Ku, Seoul, Korea.     

24位BOOTH乘法器核的一种有效BIST方法

针对24位BOOTH乘法器核的可测性问题，提出了一种有效的BIST(built-in self-test)设计方案。这种方案只需要对乘法器进行少量的改动，缺陷测试覆盖率可以达到95％左右。该方案还可以应用到其他嵌入式核的可测性设计中。     

Optimizing error masking in BIST by output data modification

The error masking in conventional built-in self-test schemes is known to be around 2^–m when the output data is compacted in an m-bit multi-input linear feedback shift register. In the recent years, several schemes have been proposed which claim to reduce the error masking in a significant way while maintaining the need for a small overhead. In this paper, a completely new scheme for reducing error masking is proposed. Unlike the previous schemes in the literature, the new scheme is circuit-dependent and uses the concept of output data modification. This concept suggests modifying the original test output sequence before compaction, in order to obtain a new sequence with a reduced error masking probability. It is shown that the output data modification scheme provides a simple trade-off between the desired error masking which could run into (2^1thousands) and the area overhead needed (which would usually be equal to a 16 or 32 bit multi-input linear feedback shift register) for this masking. Finally, a formal proof is presented which establishes that despite circuit-dependency, the proposed scheme will on the average always lead to the desired error masking.     

一种改进的嵌入式SRAM内建自测试设计

对单端口SRAM常用的13N测试算法进行修改和扩展,提出了一种适用于双端口SRAM的测试算法。该测试算法的复杂度为O(n),具有很好的实用性。作为一个实际应用,通过将该算法和13N测试算法实现于测试算法控制单元,完成了对片内多块单端口SRAM和双端口SRAM的自测试设计。     

Multiple-output parity bit signature for exhaustive testing

In this article we propose a multiple-output parity bit signature generation method for exhaustive testing of VLSI circuits. Given a multiple-output combinational circuit, a parity bit signature is generated by first EXORing all the outputs to produce a new output function and then feeding this resulting function to a single-output parity bit signature generator. The method preserves all the desirable properties of the conventional single-output circuits response analyzers and can be readily implemented using the current VLSI technology.     

SOC设计方法学和可测试性设计研究进展

随着微电子工艺技术和设计方法的发展，系统级芯片(SOC)设计成为解决日益增长的设计复杂度的主要方法。文章概述了SOC设计方法学和SOC可测试性设计的发展现状，阐述了目前SOC测试存在的和需要解决的问题，描述了目前开发的各种SOC测试结构和测试策略。最后，提出了今后进一步研究的方向。     

A Novel BIST Approach for Testing Input/Output Buffers in SoCs

A novel built-in self-test （BIST） approach to test the configurable input/output buffers in Xilinx Virtex series SoCs （system on a chip） using hard macro has been proposed in this paper. The proposed approach can completely detect single and multiple stuck-at gate-level faults as well as associated routing resources in I/O buffers. The proposed BIST architecture has been implemented and verified on Xilinx Virtex series FPGAs （field programmable gate configurations are required array）. Only total of 10 to completely test the I/O buffers of Virtex devices.     

一种实现数模混合电路中ADC测试的BIST结构

针对模／数转换器(ADC)数模混合电路的测试问题，提出了一种内建自测试(BIST)的测试结构，分析并给出了如何利用该结构计算ADC的静态参数和信噪比参数。利用该方法，既可以利用柱状图快速测试ADC的静态参数，又可利用FFT技术实现对ADC频域参数的分析，使得测试电路简单、紧凑和有效。     

Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores

This paper introduces a new concept of testability called consecutive testability and proposes a design-for-testability method for making a given SoC consecutively testable based on integer linear programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from test pattern sources (implemented either off-chip or on-chip) consecutively at the speed of system clock. Similarly the test responses are propagated to test response sinks (implemented either off-chip or on-chip) from the core outputs consecutively at the speed of system clock. The propagation of test patterns and responses is achieved by using interconnects and consecutive transparency properties of surrounding cores. All interconnects can be tested in a similar fashion. Therefore, it is possible to test not only logic faults but also timing faults that require consecutive application of test patterns at the speed of system clock since the consecutively testable SoC can achieve consecutive application of any test sequence at the speed of system clock.     

Design for Testability Techniques at the Behavioral and Register-Transfer Levels

Improving testability during the early stages of the design flow can have several benefits, including significantly improved fault coverage, reduced test hardware overheads, and reduced design iteration times. This paper presents an overview of high-level design methodologies that consider testability during the early (behavior and architecture) stages of the design flow, and their testability benefits. The topics reviewed include behavioral and RTL test synthesis approaches that generate easily testable implementations targeting ATPG (full and partial scan) and BIST methodologies, and techniques to use high-level information for ATPG.     

Parity bit calculation and test signal compaction for BIST applications

Parity bit checking and pseudo-exhaustive testing are two design techniques which have been widely discussed in the BIST literature but have seldom been employed in practice because of the exponential nature of the processes involved. In this paper we describe several procedures designed to avoid these exponential explosions. Specifically we show how the parity of a large combinational function can (often) be quickly calculated. This is accomplished by an examination of the circuit realization itself particularly with regard to the connectivity between the various inputs and outputs. We then show how this same approach can be used to partition circuits so that they can be tested efficiently with a relatively small number of test patterns. Using these methods we were able to calculate the parity bits for more than 80% of ISCAS benchmark circuits' outputs. Interestingly enough, only 15% of these outputs were found to be parity-odd, but for these cases high fault coverage was invariably found to result. Several examples are included.This work was partially supported by the National Science Foundation under grant MIP-8902014.     

SOC芯片的可测试性设计与功耗优化

介绍了数字集成电路可测试性设计与测试覆盖率的概念,针对一款电力网通信芯片完成了可测试性设计,从测试的覆盖率、功耗等方面提出了优化改进方案,切实提高了芯片的测试覆盖率,缩减了测试时间和成本,降低了测试功耗,同时保证了芯片测试的可靠性,最终使芯片顺利通过量产测试。     

数字集成电路故障测试策略和技术的研究进展

IC制造工艺的发展，持续增加着VLSI电路的集成密度，亦日益加大了电路故障测试的复杂性和困难度。作者在承担相应研究课题的基础上，综述了常规通用测试方法和技术，并分析了其局限性。详细叙述了边界扫描测试(BST)标准、可测性设计(DFT)思想和内建自测试(BIST)策略。针对片上系统(SoC)和深亚微米(VDSM)技术给故障测试带来的新挑战，本文进行了初步的论述和探讨。     

一款百万门缀SOC芯片的可测性设到

本文介绍了一款基于65nm工艺的数字处理芯片的可测性设计,采用了边界扫描测试,存储器内建自测试和内部扫描测试技术。这些测试技术的使用为该芯片提供了方便可靠的测试方案,实验结果表明该设计的测试覆盖率符合工程应用要求。     

面向低功耗BIST 的VLSI 可测性设计技术

随着手持设备的兴起和芯片对晶片测试越来越高的要求，内建自测试的功耗问题引起了越来越多人的关注，本文对目前内建自测试的可测性设计技术进行了分析并对低功耗的VLSI可测性设计技术的可行性和不足分别进行了探讨。在文章的最后简单介绍了笔者最近提出的一种低功耗的BIST结构。     

LSC87中嵌入式ROM内建自测试实现

LSC87芯片是与Intel8086配套使用的数值协处理器，体系结构复杂，有较大容量的嵌入式ROM存储器，考虑到与Intel8087的兼容性和管脚的限制，必须选择合适的可测性设计来提高芯片的可测性。文章研究了LSC87芯片中嵌入式ROM存储器电路的设计实现，然后提出了芯片中嵌入式ROM电路的内建自测试，着重介绍了内建自测试的设计与实现，并分析了采用内建自测试的误判概率，研究结果表明，文章进行的嵌入式ROM内建自测试仅仅增加了很少的芯片面积开销，获得了满意的故障覆盖率，大大提高了整个芯片的可测性。     

Cost/Quality Trade-off in Synthesis for BIST

This paper details our allocation for Built-in Self Test (BIST) technique used by the core part of our Testability Allocation and Control System (TACOS) called IDAT. IDAT tool objective is to fulfill the designer requirements regarding selected design and testability attributes of a circuit data-path to be synthesized. A related tool is used to synthesize a test controller for the final testable circuit. The allocation process of BIST resources in the data-path is driven by two trade-off techniques performed in order to: (1) at the local level, select the optimal set of Functional Units (FUs) to be BISTed, using a new testability analysis method and (2) at the global level, for each selected FU of this set, choose either to allocate its BIST version (when available in a library) or to connect it to an internal Test Pattern Generator (TPG) and Test Results Checker (TRC). When necessary, a last step of the process is the allocation of scan chains used to test the remaining untested interconnections. Experiments show the results of our allocation for BIST technique on three benchmarks.     

An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths

In this paper an effective Built-In Self-Test (BIST) scheme for the shifter-accumulator pair (accumulation performed either by an adder or an ALU) which appears very often in embedded processor, microprocessor or DSP datapaths is introduced. The BIST scheme provides very high fault coverage (>99%) with respect to the stuck-at fault model for any datapath width with a regular, very small and counter-generated deterministic test set, as it is verified by a comprehensive set of experiments.     

A quasi-optimal scheduling of intermediate signatures for multiple signature analysis compaction testing schemes

In this article, a strategy based on the use of intermediate signatures is proposed that enables the exact fault coverage of compact testing schemes to be determined in a feasible computation time. Two models to predict fault simulation time, a fault simulator dependent and independent model, are developed and used by a dynamic programming based algorithm to find the optimal scheduling of the signatures with respect to the total simulation time. Simulation results for both models are then presented demonstrating the feasibility of the proposed strategy.This work was supported in part by grants from the Natural Sciences and Engineering Research Council (NSERC) of Canada, the Canadian Microelectronics Corporation (CMC) and the British Columbia Advanced Systems Institute (B.C. A.S.I.).