当前直接覆铜技术的研究进展

叙述了近期国内外关于直接覆铜(DBC)技术的发展动态,指出DBC技术在电力电子模块、LED器件以及半导体制冷等领域的广泛应用,特别是AlN基片的DBC工艺研究应该引起有关科技人员的关注。     

ULSI制备中多层布线导体铜的抛光液与抛光技术的研究

提出了在碱性浆料中ULSI多层布线导体铜化学机械抛光的模型,对铜CMP所需达到的平面化、选择性、抛光速率控制、浆料的稳定及洁净度、抛光液成分的优化选择进行了实验研究。     

ULSI制备中多层布线导体铜的抛光液与抛光技术的研究

提出了在碱性浆料中 UL SI多层布线导体铜化学机械抛光的模型 ,对铜 CMP所需达到的平面化、选择性、抛光速率控制、浆料的稳定及洁净度、抛光液成分的优化选择进行了实验研究。     

Advantages and new development of direct bonded copper substrates

Direct bonded copper (DBC) substrates have become the most important electronic circuit boards for multichip power semiconductor modules. They are replacing complicated assemblies based on leadframes and refractory metallized substrates due to ease of assembly and the low temperature coefficient of expansion of DBC which matches silicon in spite of thick copper metallization. The DBC technology allows bonding of copper to alumina and aluminum nitride, fusing of copper to copper has been developed to establish efficient water cooling devices with sophisticated internal micro channel structures for cooling power laser diodes and other high power density electronics. Low weight, hermetically sealed DBC packages are replacing more and more heavy weight metal can packages. Increasing requirements for temperature cycling reliability and mechanical stability in automotive, avionics and space applications is the driving force for the development of a new type of DBC material with a 60% increase in flexural strength and more than 100% increase of temperature cycles: This new type of DBC allows 35% thicker copper layers on 20% thinner ceramic, for example 0.4 mm copper on 0.32 mm ceramic. By this the thermal resistance of multichip power modules can be reduced substantially without decreasing reliability. In many applications this will be an economic solution where the price of AlN and Si₃N₄ substrates would be too high.     

The effect of forming gas anneal on the oxygen content in bonded copper layer

Using a combination of copper (Cu) thermocompression bonding and silicon wafer thinning, a face-to-face silicon bi-layer layer stack is fabricated. The oxygen content in the bonded Cu layer is analyzed using secondary ion mass spectrometry (SIMS). Copper-covered wafers that are exposed to the air for 12 h and 12 days prior to bonding exhibit 0.08 at.% and 2.96 at.% of oxygen, respectively. However, prebonding forming gas anneal at 150°C for 15 min on 12-day-old Cu wafers successfully reduces the oxygen content in the bonded Cu layer to 0.52 at.%.     

Effects of barrier layer and processing conditions on thin film Cu microstructure

The crystallographic texture and grain size of sputtered Cu films were characterized as a function of deposition temperature, barrier layer material, and vacuum conditions. For Cu deposited in a HV chamber, (111) Cu texture was found to weaken with increasing deposition temperatures on W, amorphous C and Ta barrier layers, each deposited at 30°C. Conversely, under identical Cu deposition conditions, texture was found to strengthen with increasing deposition temperature on Ta deposited at 100°C. Median Cu grain size varied parabolically with deposition temperature on all barrier layers and was slightly higher on the 100°C Ta at a given Cu deposition temperature, relative to the other underlayers. For depositions in an UHV chamber, Cu texture was found to strengthen with increasing Cu deposition temperature, independent of Ta deposition temperature. Median Cu grain size, however, was still higher on 100°C Ta than on 30°C Ta. The observed differences between the two different chambers suggest that the trend of weak texture at elevated deposition temperatures may be related to contamination. Characterization of the Ta underlayers revealed that the strengthened texture of Cu films deposited on 100°C Ta is likely related to textural inheritance.     

Characterization of materials and their interfaces in a direct bonded copper substrate for power electronics applications

Direct bonded copper (DBC) are produced by high temperature ( >1000 ° C) bonding between copper and a ceramic (usually alumina). They are commonly used in power electronics. However, their reliability when exposed to thermal cycling is still an issue, that could be addressed by advanced numerical simulations. This paper describes the identification of the parameters for a numerical model that uses finite elements with cohesive zones. This identification is based on careful mechanical characterization of all components of the DBC (ceramic, copper and interface) using an innovative approach based on image correlation.     

A low-cost copper oxide thin film memristive device based on successive ionic layer adsorption and reaction method

Metal-insulator-metal based memristive structure is a promising configuration for next generation information storage, reconfigurable circuits and neuromorphic application. In view of this, we experimentally demonstrated the simple and cost effective approach to fabricate CuO memristive device using successive ionic layer adsorption and reaction method. The developed two terminal Al/CuO/SS thin film memristive device successfully mimic the biological synapse-like properties such as analog memory, synaptic weights and bidirectional information flow. Furthermore, the bipolar resistive switching with different magnitudes of V_SET and V_RESET were observed due to stochastic nature of formation and breaking of the conductive filament. The slopes of current-voltage characteristics suggested that the Ohmic and space charge limited conduction mechanisms were dominant in developed devices. The analysis of electrical characterization suggested that the memcapacitive and meminductive properties coexisted with memristive behavior in the developed devices. The results reported herein are useful for the development of low-cost electronic synapse and nano-scaled self-resonating, reconfigurable and adaptive circuits.     

基于聚合物绝缘栅的低电压有机薄膜晶体管

利用甲基丙烯酸甲酯-甲基丙烯酸环氧丙脂为栅绝缘层制备了酞箐铜有机薄膜晶体管,在电压为10V时器件具有较好的性能,栅绝缘层的漏电流密度低至2×10-8A/cm2 。测量其电容特性,该绝缘薄膜的介电常数介于3.9-5.0 。通过对绝缘层的减薄,阈值电压由 -3.5V 升至-2.0V,该酞箐铜有机薄膜晶体管可以在低电压下工作,其场效应迁移率为1.2×10-3 cm2/Vs 。     

Influence of channel layer and passivation layer on the stability of amorphous InGaZnO thin film transistors

The electrical stability of amorphous InGaZnO (a-IGZO) TFTs with three different channel layers was investigated. Compared with the single channel layer, the a-IGZO TFT with double stacked channel layer showed the lowest threshold voltage shift with slightly change in field effect mobility and sub-threshold swing under positive and negative gate bias stress tests. Moreover, sputtered SiN_x thin film was served as passivation layer where the V_th shift in bias stress effect evidently became less. It was found that the passivated a-IGZO TFT with double stacked channel layer still exhibited the best stability. The results prove that the stability of a-IGZO TFTs can be effectively improved by using double stacked channel layer and passivation layer.     

Isolation of silicon film grown on porous silicon layer

We have investigated a new technology for dielectric isolation of a Si film grown epitaxially on a porous silicon layer. After oxidation of the porous silicon layer, a Si on Ohcidized Porous Silicon(SOPS) structure can be obtained. It is proposed that micropores pinch off quickly in the interfacial region between the porous silicon layer and the epitaxial film. A minimum yield calculated from Rutherford backscattering spectra of the epitaxial silicon film is 5.3%, and an electron Hall mobility of 600cm²/V.s is obtained in the film with a carrier concentration of 1 x 10¹⁷ /cm³. MOSFETs were fabricated on the SOPS structure.     

Effects of the ZnO buffer layer and Al proportion on AZO film properties

To evaluate the influence of the ZnO buffer layer and Al proportion on the properties of ZnO: Al (AZO)/ZnO bi-layer films, a series of AZO/ZnO films are deposited on the quartz substrates by electron beam evaporation. The X-ray diffraction measurement shows that the crystal quality of the films is improved with the increase of the film thickness. The electrical properties of the films are investigated. The carrier concentration and Hall mobility both increase with the increase of buffer layer thickness. However, the resistivity reaches the lowest at about 50 nm-thick buffer layer. The lowest resistivity and the maximum Hall mobility are both obtained at 1 wt% Al concentration. But the optical transmittance of all the films is greater than 80% regardless of the buffer layer thickness with Al concentration lower than 5 wt% in the visible region.     

Improved estimation of the resistivity of pure copper and electrical determination of thin copper film dimensions

Improved values for the resistivity, ρ, of pure, bulk copper from 50 to 1200 K, and their confidence intervals, are developed by extending the analysis of Matula. A recommended value for dρ/dT and its confidence interval in the temperature range of 290–425 K is developed for use with Matthiessen's rule to calculate the electrical thickness of thin copper films and the cross-sectional area of copper lines from resistance measurements at two temperatures. Error analyses are used to estimate the uncertainty with which the electrical thickness and cross-sectional area can be determined. Values for the temperature coefficient of resistance of pure, bulk copper are also provided.