集成CMOS四象限模拟乘法器

给出了一种CMOS型四象限模拟乘法器,该乘法器采用有源衰减器结合吉尔伯特单元结构.利用基于CSMC的0.6μm n阱2p2m工艺SPICE BSIM3V3 MOS模型(level=49)进行仿真,采用单电源5V电压供电.利用HSPICE仿真并给出了仿真的结果及版图实现.     

集成CMOS四象限模拟乘法器

给出了一种CMOS型四象限模拟乘法器,该乘法器采用有源衰减器结合吉尔伯特单元结构.利用基于CSMC的0.6μm n阱2p2m工艺SPICE BSIM3V3 MOS模型(level=49)进行仿真,采用单电源5V电压供电.利用HSPICE仿真并给出了仿真的结果及版图实现.     

集成CMOS四象限模拟乘法器

给出了一种CMOS型四象限模拟乘法器，该乘法器采用有源衰减器结合吉尔伯特单元结构.利用基于CSMC的0.6μm n阱2p2m工艺SPICE BSIM3V3 MOS模型(level=49)进行仿真，采用单电源5V电压供电.利用HSPICE仿真并给出了仿真的结果及版图实现.     

20×18位符号定点乘法器的FPGA实现

在数字信号处理中经常需要进行乘法运算,乘法器的设计对整个器件的性能有很大的影响,在此介绍20×18比特定点阵列乘法器的设计.采用基4-Booth算法和4-2压缩的方案,并采用先进的集成电路工艺,使用SMIC 0.18μm标准单元库,提高了乘法器的速度,节省了器件.利用Xilinx FPGA(xc2vp70-6ff1517)对乘法器进行了综合仿真,完成一次乘法运算的时间为15.922 ns,在减少乘法器器件的同时,提高了乘法器的速度,降低了器件的功耗.     

基于Booth算法的32位流水线型乘法器设计

为了减少乘法指令在保留站中的等待时间,设计了一款32位流水线型乘法器,该乘法器将应用于作者设计的一款超标量处理器中.该乘法器应用了改进型的booth编码算法,对部分积生成电路进行了优化,并采用了4-2压缩器与3-2压缩器相结合的Wallace树型结构对部分积进行压缩,最后再根据各级的延迟,在电路中插入了流水线寄存器,使其运算速度得到了提高.该乘法器使用GSMC 0.18μm工艺进行综合.经过仿真验证,该乘法器大大减少了在保留站中等待执行的乘法指令的完成时间,使每个时钟周期都有一条新的乘法指令被发送至乘法器进行运算.     

一种高压缩Wallace树的快速乘法器设计

介绍了一种32位有符号/无符号乘法器.该乘法器采用改进的Booth编码减少了部分积个数,并通过符号扩展的优化,减少中间资源消耗,对部分积进行统一的符号操作,简化了程序设计的复杂性.采用了7:2压缩结构的Wallace树及64位Brent Kung树结构超前进位加法器,有效地提高了乘法器计算速度.整个设计采用Verilog语言编写,通过Modelsim仿真验证设计功能的正确性.采用Synopsys的Design Compiler进行基于SMIC的0.18微米标准库的综合并得到性能参数.     

54位高速冗余二进制乘法器的设计

冗余二进制(RB)数是一种有符号数的表示方法,利用冗余二进制算法的进位无关特性和规整的结构,可以设计高速RB并行乘法器.系统地研究了RB乘法器的算法和结构,给出了基于修正Booth算法,RB部分积压缩树和RB-NB转换器的54b乘法器的设计过程,并利用并行前缀/进位选择混合加法器对RB-NB转换器进行优化设计.采用Verilog HDL对乘法器进行描述,并在ModelSim平台上进行仿真验证,在SMIC 0.18mm标准工艺库下,通过Synopsys公司综合工具Design Compiler进行综合,得到54bRB乘法器的延时可达到3.97ns,面积是409 293mm2.     

一种宽输入范围CMOS模拟乘法器的优化设计

设计了一种基于CMOS工艺设计的宽输入范围的Gilbert单元乘法器.通过在乘法器的输入端加入有源衰减器和电位平移电路,增大了乘法器的输入范围(±4 V).该乘法器采用TSMC 0.35 μm的CMOS工艺进行设计,并用HSpice仿真器对电路进行了仿真,得到了电源电压为±4 V,以及线性电压输入范围为±4 V时,非线性误差小于1.0%,乘法运算误差小于0.3%,x输入端的-3 dB带宽为470 MHz,y输入端的-3 dB带宽为4.20 GHz的良好结果,整个乘法器电路的功耗为2.82 mW.     

面向多媒体信息处理的可重构BOOTH乘法器设计

设计了一种新型可重构BOOTH乘法器.该乘法器在BOOTH编码、部分积生成、部分积压缩和最终加法器的设计中都充分考虑了可重构的需要,能方便快速地实现8位乘法器和16位乘法器之间的切换,便于在同一电路上实现基于字节和字的多媒体信息处理.该乘法器通过VHDL语言编程实现,采用XST综合,并通过Modelsim在XC2V4000上完成布局布线后仿真.试验结果表明:与基于乘法分配律的可重构乘法器相比,该方法具有占用资源少和速度快的优点.     

并行行旁路乘法器的设计与实现

为了进一步降低乘法器运算过程中的延迟,减少功耗,在行旁路乘法器的基础上进一步优化,提出一种并行行旁路(PRB)乘法器,并用有限状态机进行了实现.在行旁路的基础上,通过对乘数进行重新编码并行输出部分积,使乘法运算中产生的部分积数量减少,提高运算速度;利用有限状态机实现PRB乘法器,有效减少了电路中逻辑元件的数量,降低了功耗.在Quartus平台上进行的仿真表明PRB乘法器在整体性能上有较大的改善.     

微波PIN二极管倍频器研究

用理想的开关模型对反向并联PIN二极管对的输出频谱和倍频损耗进行分析,与混频二极管倍频器和变容二极管倍频器进行了比较,分析了PIN二极管的倍频机理。对微波PIN二极管倍频器进行了实验研究,得出了有益的结论。研制的S波段和C波段五倍频器倍频损耗分别达到15.4 dB和10.6 dB,而S波段的倍频源相位噪声达到—136 dBc/Hz@10 kHz,具有低噪声性能。     

一种低压高频CMOS电流乘法器的设计

提出了一种新颖的高频四象限电流乘法器电路，该乘法器使用了工作在三极管区的互补MOS器件，并且采用了饱和区MOS管的平方律特性。该电路采用0．35pmCMOS工艺，使用HSpice软件仿真。仿真结果显示，该乘法器电路在±1.18V的电源电压下工作时，静态功耗为1．18mW，-3dB带宽可达到1．741GHz。与先前的电流乘法器电路相比，工作电压降低了，带宽提高了。     

Two's complement computation sharing multiplier and its applications to high performance DFE

We present a novel computation sharing multiplier architecture for two's complement numbers that leads to high performance digital signal processing systems with low power consumption. The computation sharing multiplier targets the reduction of power consumption by removing redundant computations within system by computation reuse. Use of computation sharing multiplier leads to high-performance finite impulse response (FIR) filtering operation by reusing optimal precomputations. The proposed computation sharing multiplier can be applicable to adaptive and nonadaptive FIR filter implementation. A decision feedback equalizer (DFE) was implemented based on the computation sharing multiplier in a 0.25-/spl mu/ technology as an example of an adaptive filter. The performance and power consumption of the DFE using a computation sharing multiplier is compared with that of DFEs using a Wallace-tree and a Booth-encoded multiplier. The DFE implemented with the computation sharing multiplier shows improvement in performance over the DFE using a Wallace-tree multiplier, reducing the power consumption significantly.     

A one volt four-quadrant analog current mode multiplier cell

This paper describes a four-quadrant analog multiplier cell that can operate below one volt dc bias. This new multiplier cell is specially designed for low voltage portable communication equipment. The multiplier cell consists of two translinear loops. We have operated this new multiplier cell at as low as 0.8 V. With the exception of the low voltage operation, the output current of the multiplier cell is a true product of the input currents, and there is no limitation on the input dynamic range as with the conventional Gilbert cell     

A data-path multiplier with automatic insertion of pipeline stages

The architecture of an easy-to-use, highly configurable, compiled pipelined multiplier is described. The multiplier is designed for use in high-performance pipelined data paths such as those found in digital signal processing applications. The multiplier compiler allows the data-path designer to control the bit width of the multiplier as well as the clock-cycle time, setup time, and output-delay time. Given these parameters, the multiplier compiler uses a simple timing model to decide where pipeline stages should be inserted into the multiplier and generates a pipelined multiplier that meets the designer's system requirements     

一种规整高效的缩1码模2^n＋1乘法器的VLSI设计

针对目前缩1码模2n＋1乘法器的优缺点,设计出一个有效的缩1码模2n＋1乘法器。该模乘法器是由改进的基-4 Booth编码模块、规整的缩1码进位保留加法器树以及缩1码模加法器构成,部分积的个数减少到n/2＋2个,具有统一的编码电路,简单的校正项生成电路,较快的计算速度,尤其是能够处理操作数和结果为0的情况,实现了操作数的全输入。比较结果表明,该模乘法器在同类型模乘法器中以最少的面积获得了更快的速度。     

Asynchronous cross-pipelined multiplier

In this paper, a design of a 16-bit asynchronous multiplier is presented. The multiplier core consists of small basic blocks. Each block includes handshake and computation logic and communicates with four neighbor cells in asynchronous handshake fashion using four-phase protocol. The computation logic is implemented in dual-rail coded domino logic. The input and output signals of the multiplier are single-rail coded. The single-rail coding allows communication with other single-rail coded asynchronous blocks using four-phase signaling. The design speed is self-adjusting to the technology parameters and supply voltage variations. The multiplier has low latency and achieves a throughput rate of 250 MHz. The multiplier was fabricated in a 0.6-μm CMOS process and has a core size of 4.3×2.1 mm     

环绕立体声处理ASlC中并行乘法器的设计与实现

介绍了环绕立体声处理ASIC设计中的基于多路选择器结构的并行乘法器设计原理及实现方法,这种并行乘法器适合四级指令流水线结构的处理器对声音信号的实时处理。其结构规则,有利于VLSI设计实现并且提高了设计效率。使用VHDL语言描述并进行综合和仿真。结果表明,其占用硬件资源较省,工作频率可达47.2MHz,满足声音信号实时处理要求。     

High-performance FIR filter design based on sharing multiplication

Finite impulse response (FIR) filtering can be expressed as multiplications of vectors by scalars. We present high-speed designs for FIR filters based on a computation sharing multiplier which specifically targets computation re-use in vector-scalar products. The performance of the proposed implementation is compared with implementations based on carry-save and Wallace tree multipliers in 0.35-/spl mu/m technology. We show that sharing multiplier scheme improves speed by approximately 52 and 33% with respect to the FIR filter implementations based on the carry-save multiplier and Wallace tree multiplier, respectively. In addition, sharing multiplier scheme has a relatively small power delay product than other multiplier schemes. Using voltage scaling, power consumption of the FIR filter based on computation sharing multiplier can be reduced to 41% of the FIR filter based on the Wallace tree multiplier for the same frequency of operation.     

FPGA中专用可重构乘法器的设计

提出了一种新的嵌入在FPGA中可重构的流水线乘法器设计.该设计采用了改进的波茨编码算法,可以实现18×18有符号乘法或17×17无符号乘法.还提出了一种新的电路优化方法来减少部分积的数目,并且提出了一种新的乘法器版图布局,以便适应tilebased FPGA芯片设计所加的约束.该乘法器可以配置成同步或异步模式,也町以配置成带流水线的模式以满足高频操作.该设计很容易扩展成不同的输入和输出位宽.同时提出了一种新的超前进位加法器电路来产生最后的结果.采用了传输门逻辑来实现整个乘法器.乘法器采用了中芯国际0.13μm CMOS工艺来实现,完成18×18的乘法操作需要4.1ns.全部使用2级的流水线时,时钟周期可以达到2.5ns.这比商用乘法器快29.1%,比其他乘法器快17.5%.与传统的基于查找表的乘法器相比,该乘法器的面积为传统乘法器面积的1/32.