Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors

Adaptive supply voltage as well as adaptive body bias may be used to control the frequency and leakage distribution of fabricated microprocessor dies. Test chip measurements show that adaptive V/sub CC/ is effective in reducing the impact of parameter variations on frequency, active power, and leakage power of microprocessors when 20 mV V/sub CC/ resolution is used. Using adaptive V/sub CC/ together with adaptive V/sub BS/ or within-die body bias is much more effective than using any of them individually.     

Threshold-voltage balance for minimum supply operation [LV CMOS chips]

The difference between the threshold voltages V/sub t/ of pMOS and nMOS transistors is a critical issue in the low-voltage operation of CMOS circuits. The pMOS/nMOS V/sub t/ balancing profit is analyzed in terms of subthreshold leakage current and the performance of CMOS LSIs and the minimum supply voltage of logic circuits. Matching the pMOS/nMOS V/sub t/ improves LSI performance and reduces the lowest supply voltage by 0.15 V. We propose a new concept of body bias management that uses forward biasing, fluctuation compensating, and V/sub t/ matching technologies to resolve the issue.     

High-responsivity high-gain In/sub 0.53/Ga/sub 0.47/As-InP quantum-well infrared photodetectors grown using metal-organic vapor phase epitaxy

We report the growth and fabrication of bound-to-bound In/sub 0.53/Ga/sub 0.47/As-InP quantum-well infrared photodetectors using metal-organic vapor phase epitaxy. These detectors have a peak detection wavelength of 8.5 /spl mu/m. The peak responsivities are extremely large with R/sub pk/=6.9 A/W at bias voltage V/sub b/=3.4 V and temperature T=10 K. These large responsivities arise from large detector gain that was found to be g/sub n/=82 at V/sub b/=3.8 V from dark current noise measurements at T=77 K and g/sub p/=18.4 at V/sub b/=3.4 V from photoresponse data at T=10 K. The background-limited temperature with F/1.2 optics is T/sub BLIP/=65 K for 0相似文献   

MOS Compatibility of High-Conductivity TaSi/sub 2//n+ Poly-Si Gates

The MOS-VLSI parameters and process compatibility of a high-conductivity refractory silicide gate with a sheet resistance of -2 Omega//spl square/ have been evaluated. The gate metallization typically consisted of 2.5 k/spl Aring/ TaSi/sub 2//2.5 k/spl Aring/ poly-Si, which was sintered prior to patterning with a CF/sub 4//O/sub 2/ plasma etch. Measurements were made to determine the metal work function, oxide freed charge, surface-states density, dielectric strength, oxide defect density, lifetime, current leakage, and the flat-band voltage stability with respect to mobile charge contamination, slow trapping, and hot-electron trapping. On IGFET's (500-/spl Aring/ SiO/sub 2/, As-implanted source/drain), V/sub T/ and Beta measurements were made as a function of the back-gate bias and the channel length as small as 2 µm. The MOS and IGFET parameters are nearly ideal and correspond to those expected of n+ poly-Si gates. Static and dynamic bias-temperature aging stability of the V/sub FB/ is excellent. These characteristics are preserved through subsequent standard VLSI process steps. However, certain process and structure limitations do exist and these have been defined.     

Reverse-body bias and supply collapse for low effective standby power

Integrated circuits fabricated on a low-leakage process typically display lower performance due to the high threshold voltage (V/sub t/) transistors. Higher performance microprocessors sacrifice power efficiency by decreasing V/sub t/. We show that a processor built on a low V/sub t/ process can achieve the power-per-computation characteristics of one built using a high V/sub t/ process, by using a "drowsy" mode combining reverse body bias (RBB) and voltage collapse when idle. This approach also allows for higher peak performance, if needed. A simple power model is shown to accurately match the measured data; high-operational frequency is demonstrated when in active operation. The circuit techniques used to provide the RBB mode of operation are described and compared with other techniques such as multi-threshold CMOS. While both techniques can be effective for logic, the design effort for RBB is shown to be smaller, while reducing embedded static random access memory standby power without added size.     

Drain-bias dependence of threshold voltage stability of amorphous silicon TFTs

Amorphous silicon (a-Si:H) thin-film transistors (TFTs) used in emerging, nonswitch applications such as analog amplifiers or active loads, often have a bias at the drain terminal in addition to the gate that can alter their threshold voltage (V/sub T/) stability performance. At small gate stress voltages (0/spl les/V/sub ST//spl les/15 V) where the defect state creation instability mechanism is dominant, the presence of a bias at the TFT drain decreases the overall shift in V/sub T/(/spl Delta/V/sub T/) compared to the /spl Delta/V/sub T/ in the absence of a drain bias. The measured shift in V/sub T/ appears to agree with the defect pool model that the /spl Delta/V/sub T/ is proportional to the number of induced carriers in the a-Si:H channel.     

Analyses and design of bias circuits tolerating output voltages above BV/sub CEO/

Due to the inevitable tradeoff between speed and breakdown voltage, the spectacular speed improvement of modern SiGe processes in recent history has partially been achieved at the cost of a reduction in breakdown voltages. Because supply voltages have hardly been reduced however, circuits operating at a supply voltage above the collector-emitter breakdown voltage (BV/sub CEO/) are common practice today and collector-base avalanche currents are therefore of major concern. Transistors that need to handle a collector-emitter voltage above (BV/sub CEO/) are typically found as output transistors in output driver stages and in bias current circuits. Such circuits can be designed to tolerate collector-emitter voltages above (BV/sub CEO/) by driving the base terminal with a relatively low impedance. This paper analyzes various conventional as well as two new bias current circuits supporting operation at collector voltages above (BV/sub CEO/). In the new circuits, feedforward and feedback avalanche current compensation techniques are introduced that obtain a substantial increase in output breakdown voltage of the bias circuits and improve the accuracy of the current mirror at output voltages above (BV/sub CEO/). With the feedback technique, a measured increase in output breakdown voltage by more than 2 V is demonstrated while the accuracy of the current mirror ratio at output voltages of 2 to 3 times (BV/sub CEO/) is improved by an order of magnitude.     

DC and RF characteristics of E-mode Ga/sub 0.51/In/sub 0.49/P-In/sub 0.15/Ga/sub 0.85/As pseudomorphic HEMTs

The DC and RF characteristics of Ga/sub 0.49/In/sub 0.51/P-In/sub 0.15/Ga/sub 0.85/As enhancement- mode pseudomorphic HEMTs (pHEMTs) are reported for the first time. The transistor has a gate length of 0.8 /spl mu/m and a gate width of 200 /spl mu/m. It is found that the device can be operated with gate voltage up to 1.6 V, which corresponds to a high drain-source current (I/sub DS/) of 340 mA/mm when the drain-source voltage (V/sub DS/) is 4.0 V. The measured maximum transconductance, current gain cut-off frequency, and maximum oscillation frequency are 255.2 mS/mm, 20.6 GHz, and 40 GHz, respectively. When this device is operated at 1.9 GHz under class-AB bias condition, a 14.7-dBm (148.6 mW/mm) saturated power with a power-added efficiency of 50% is achieved when the drain voltage is 3.5 V. The measured F/sub min/ is 0.74 dB under I/sub DS/=15 mA and V/sub DS/=2 V.     

Mixed body bias techniques with fixed V/sub t/ and I/sub ds/ generation circuits

There remains a need to improve sub-1-V CMOS VLSIs with respect to variation in transistor behavior. In this paper, to minimize variation in delay and the noise margin of the circuits in processors, we propose several mixed body bias techniques using body bias generation circuits. In these circuits, either the saturation region of the current between source and drain (I/sub ds/) or the threshold voltage (V/sub t/) of PMOS/NMOS is permanently fixed, regardless of temperature range or variation in process. A test chip that featured these body bias generation circuits was fabricated using a 130-nm CMOS process with a triple-well structure. The mixed body bias techniques which keep the I/sub ds/ of the MOS in the decoder and I/O circuits of a register file fixed and maintain the V/sub t/ of the MOS in both the memory cell and domino circuits of the register file fixed resulted in positive temperature dependence of delay from -40 /spl deg/C to 125 /spl deg/C, 85% reduction of the delay variation compared with normal body bias (NBB) at V/sub DD/ = 0.8 V. In addition, the results using these techniques show a 100-mV improvement in lower operating voltage compared with NBB at -40 /spl deg/C on a 4-kb SRAM.     

Wide-wavelength-band (30 nm) 10-Gb/s operation of InP-based Mach-Zehnder modulator with constant driving voltage of 2 V/sub pp/

Wide-wavelength-band operation of InP-based Mach-Zehnder modulators is investigated. From the measured dependences of the half-wavelength voltage on operating wavelength and applied-bias voltage, it is shown that wide-wavelength operation with a constant driving voltage can be realized by adjusting the bias voltage for each operating wavelength. Ten-gigabits/second clear eye openings are demonstrated over a 30-nm wavelength range with a constant driving voltage of 2 V/sub pp/.     

High-energy tail electrons as the mechanism for the worst-case hot-carrier stress degradation of the deep submicrometer N-MOSFET

Experimental evidence, based on sensitively modulating the concentration of the high-energy tail of the electron energy distribution, reveals an important trend in the mid-to-high gate stress voltage (V/sub g/) regime, where device degradation is seen to continuously increase with the applied V/sub g/, for a given drain stress voltage V/sub d/. The shift in the worst-case degradation point from V/sub g//spl ap/V/sub d//2 to V/sub g/=V/sub d/, depicting an uncorrelated behavior with the substrate current, is caused by the injection of the high-energy tail electrons into the gate oxide, when the oxide field near the drain region becomes increasingly favorable as V/sub g/ approaches V/sub d/. This letter offers an improved framework for understanding the worst-case hot-carrier stress degradation of deep submicrometer N-MOSFETs under low bias condition.     

Metal-semiconductor-metal (MSM) photodetectors fabricated on MOCVD grown Hg/sub 1-x/Cd/sub x/Te

The fabrication of the first metal-semiconductor-metal photodetectors on Hg/sub 1-x/Cd/sub x/Te is reported using MOCVD grown layers on GaAs substrates. An epitaxial CdTe overlayer has been incorporated in the device structure for the enhancement of Schottky barrier characteristics. The interdigitated devices (2.3 mu m electrode width, 3.3 mu m spacing) exhibited a breakdown voltage of -60 V and responsivities of more than 1.0 A/W at a wavelength of 1.3 mu m and bias voltage of 40 V. Over the range of bias voltage examined, the dark leakage current of the detectors was dependent on the choice of contact metal, with minimum values of 10 nA at <1 V for Pt/CdTd/Hg/sub 1-x/Cd/sub x/Te.<>     

A highly threshold Voltage-controllable 4T FinFET with an 8.5-nm-thick Si-fin channel

Highly threshold voltage (V/sub th/)-controllable four-terminal (4T) FinFETs with an aggressively thinned Si-fin thickness down to 8.5-nm have successfully been fabricated by using an orientation-dependent wet-etching technique, and the V/sub th/ controllability by gate biasing has systematically been confirmed. The V/sub th/ shift rate (/spl gamma/=-/spl delta/V/sub th///spl delta/V/sub g2/) dramatically increases with reducing Si-fin thickness (T/sub Si/), and the extremely high /spl gamma/=0.79 V/V is obtained at the static control gate bias mode for the 8.5-nm-thick Si-fin channel device with the 1.7-nm-thick gate oxide. By the synchronized control gate driving mode, /spl gamma/=0.46 V/V and almost ideal S-slope are achieved for the same device. These experimental results indicate that the optimum V/sub th/ tuning for the high performance and low-power consumption very large-scale integrations can be realized by a small gate bias voltage in the ultrathin Si-fin channel device and the orientation-dependent wet etching is the promising fabrication technique for the 4T FinFETs.     

Markov model for threshold-voltage shift in amorphous silicon TFTs for variable gate bias

Amorphous silicon (a-Si:H) thin-film transistors (TFTs) are widely used in active matrix displays and sensors, in which their operation is typically analog in nature. However, the TFT experiences a V/sub T/ shift with time under gate bias, and the need for a model of the V/sub T/ shift with variable gate bias is imperative for robust circuit design. A model for the V/sub T/ shift under constant and variable gate bias has been presented and agrees with measurement results. The developed model can be easily represented by circuit elements and incorporated into a circuit simulator. As a proof of concept, we use the model to predict the transients of a weighted voltage subtractor circuit.     

Stress-related hydrogen degradation of 0.1-/spl mu/m InP HEMTs and GaAs PHEMTs

Hydrogen degradation of III-V field-effect transistors (FETs) is a serious reliability concern. Previous work has shown that threshold-voltage shifts induced by H/sub 2/ exposure in 1-/spl mu/m-channel InP high-electron mobility transitors (HEMTs) can be attributed to compressive stress in the gate due to the formation of TiH/sub x/ in Ti/Pt/Au gates. The compressive stress affects the device characteristics through the piezoelectric effect. This paper examined the H/sub 2/ sensitivity of 0.1-/spl mu/m strained-channel InP HEMTs and GaAs pseudomorphic HEMTs. After exposure to H/sub 2/, the threshold voltage V/sub T/ of both types of devices shifted positive. This positive shift in V/sub T/ is predicted by a model for hydrogen-induced piezoelectric effect. In situ V/sub T/ measurements reveal distinct time dependences of the V/sub T/ shifts, which are also consistent with stress-related phenomena.     

Temperature‐Adaptive Back‐Bias Voltage Generator for an RCAT Pseudo SRAM

In order to guarantee the proper operation of a recessed channel array transistor (RCAT) pseudo SRAM, the back‐bias voltage must be changed in response to changes in temperature. Due to cell drivability and leakage current, the obtainable back‐bias range also changes with temperature. This paper presents a pseudo SRAM for mobile applications with an adaptive back‐bias voltage generator with a negative temperature dependency (NTD) using an NTD VBB detector. The proposed scheme is implemented using the Samsung 100 nm RCAT pseudo SRAM process technology. Experimental results show that the proposed VBB generator has a negative temperature dependency of ?0.85 mV/°C, and its static current consumption is found to be only 0.83 µA@2.0 V.     

Enhanced negative substrate bias degradation in nMOSFETs with ultrathin plasma nitrided oxide

The degradation induced by substrate hot electron (SHE) injection in 0.13-/spl mu/m nMOSFETs with ultrathin (/spl sim/2.0 nm) plasma nitrided gate dielectric was studied. Compared to the conventional thermal oxide, the ultrathin nitrided gate dielectric is found to be more vulnerable to SHE stress, resulting in enhanced threshold voltage (V/sub t/) shift and transconductance (G/sub m/) reduction. The severity of the enhanced degradation increases with increasing nitrogen content in gate dielectric with prolonged nitridation time. While the SHE-induced degradation is found to be strongly related to the injected electron energy for both conventional oxide , and plasma-nitrided oxide, dramatic degradation in threshold voltage shift for nitrided oxide is found to occur at a lower substrate bias magnitude (/spl sim/-1 V), compared to thermal oxide (/spl sim/-1.5 V). This enhanced degradation by negative substrate bias in nMOSFETs with plasma-nitrided gate dielectric is attributed to a higher concentration of paramagnetic electron trap precursors introduced during plasma nitridation.     

Dependence of self-heating effects on operation conditions and device structures for polycrystalline silicon TFTs

Self-heating, a degradation mechanism of n-channel poly-Si thin-film transistors (TFTs) due to bias stress, has been investigated. The aim of this work is to study this effect in depth to be able to propose a device structure designed to reduce it. The variation of the threshold voltage (V/sub t/) shift with the stress-pulsewidth is related to the temperature rise due to the self-heating effect that depends on the stress-pulsewidth. Electron trapping in the oxide caused by the bias stress is considered to be enhanced by the TFT temperature rise owing to the self-heating. We show that copper-film-based TFTs, which have a substrate made of an extremely thin glass layer and a copper film exhibit much reduced self-heating and thus a decrease of V/sub t/ shift caused by the bias stress. These observations are interpreted using numerical simulations to estimate the temperature rise in the poly-Si channel region due to Joule heating.     

Determination of tunnel mass and physical thickness of gate oxide including poly-Si/SiO/sub 2/ and Si/SiO/sub 2/ interfacial transition Layers

By including poly-Si/SiO/sub 2/ and Si/SiO/sub 2/ interfacial transition (IFT) layers, an excellent agreement in terms of both C-V and J-V characteristics is obtained between the experiment and theory for both polarities of gate voltage (V/sub G/) for the first time. The highly precise physical models for gate depletion and gate accumulation bring an oxide thickness extracted from the C-V fitting in a negative V/sub G/ close to that extracted in a positive V/sub G/. It is shown that the physical oxide thickness should be regarded as a distance between the middle points inside the IFT layers in both sides of the gate oxide. In addition, it is found that the tunnel mass is independent of the gate-oxide thickness from 14 to 28 /spl Aring/. It is also shown that the oxide-thickness dependence of the tunnel mass , is ascribable to the C-V-J-V fitting only in the case of a negative polarity of V/sub G/ while neglecting the poly-Si/SiO/sub 2/ IFT layer.     

高可靠性Cu BCE a-IGZO TFTs的制作

背沟道刻蚀型（BCE）非晶氧化铟镓锌薄膜晶体管（a-IGZO TFT）具有工艺简单、寄生电容小以及开口率高等优点,但BCE IGZO器件背沟道易受酸液和等离子体损伤,进而引起TFT均匀性和稳定性等方面问题,随着GOA技术的导入,对TFT器件电学性能的均匀性和稳定性提升的要求也日益迫切,因此开发高信赖性BCE IGZO TFT是技术和市场的迫切要求。本文主要分析了基于IGZO的背沟道刻蚀型薄膜晶体管电学性质,通过优化钝化层材料,色阻材料以及GOA TFT结构等削弱因背沟道水汽吸附引起的器件劣化,偏压温度应力测试结果显示优化后的TFT展现了良好的稳定性——在80℃,栅极30 V负向偏压条件下,2 000 s的ΔV_th小于1 V。最终,利用优化的IGZO TFT制作了215.9 mm（85 in）8K4K 120 Hz液晶显示器。