新一代RISC微处理器的技术特征与趋向

从流水线技术，指令调度技术，Ｃａｃｈｅ设计技术及多媒体支持等方面详细讨论新一代ＲＩＳＣ微处理器的技术特征，并简要论述ＲＩＳＣ微处理器的发展趋向。     

一种 新的Cache优化方法—部分Cache局部性方法

Ｃａｃｈｅ的性能优化在高性能计算中起着非常重要的作用。传统的Ｃａｃｈｅ优化方法存在着一些缺陷。本文分析ＲＩＳＣ处理器的特点的基础 上，提出了“部分ｃａｃｈｅ方法。实践表明，该方法有很好的优化效果，且易实于实现。     

一种基于二叉树的Cache一致性目录方法

本文提出了一种高度并发的Ｃａｃｈｅ一致性方法，着重描述了它的并发性，并且通过和ＩＥＥＥＳＣＩ协议的性能比较，表明这种Ｃａｃｈｅ一致性方法具有较好的伸缩能力，适于Ｓ２ＭＰ结构。     

PCI协议对Cache的支持

论述了Ｃａｃｈｅ在高性能计算机系统中的作用和访问Ｃａｃｈｅ的过程，以及Ｃａｃｈｅ数据一致性问题和解决的方法，介绍和分析了ＰＣＩ协议对Ｃａｃｈｅ的支持。     

Pentium的Cache组织结构及其在多机系统中的一致性机制

本文对Ｐｅｎｔｉｕｍ的片内Ｃａｃｈｅ工作机理进行分析和研究，由此得到与Ｃａｃｈｅ系统设计有关的Ｐｅｎｔｉｕｍ芯片的引脚信号，通过分析这些引脚信号的作用为设计Ｃａｃｈｅ系统提供了参考和依据     

分布式计算环境下的并行体绘制算法

分布式计算环境中基于消息传递机制的分布式共享缓冲区中，Ｃａｃｈｅ效率是算法性能的“瓶颈”。本文在分布式共享缓冲区上实现了一个并行体绘制算法。在数据空间，八叉树快速分类改善了Ｃａｃｈｅ的空间相关性；在图象空间。Ｈｉｂｅｒｔ象素遍历方式改善了Ｃａｃｈｅ的时间相关性，在曙光１０００和ＳＧＩ工作站网络上的实验结果都表明，算法的网络数据传送量大大减少，Ｃａｃｈｅ效率明显提高，绘制时间大大缩短。     

简单访问模式下假共享Cache行抖动的消除

在采用ｌｏｃａｌ ｃａｃｈｅ，ｗｒｉｔｅ－ｉｎｖａｌ：ｄａｔｅ ｃａｃｈｅ一致性协议的多级存储并行处理系统中，一个经常出现的现象就是真假共享所引起的Ｃａｃｈｅ行抖动，由于这种数据在不同处理机的Ｃａｃｈｅ间来回移动的现象严重地影响了并行机性能的发挥，它已受到计算机界广泛的关注，如何使这一问题得到简单而有效的解决已成为多级存储并行处理系统研究的一个关键，为了消除真共享引起的抖动现象，我们已经提出了一套     

Cache一致性协议的研究与评价

Ｃａｃｈｅ一致性是紧耦合多处理机系统设计中的一项重要课题．为提高访存效率，每台处理机通常带有高速缓冲存储器Ｃａｃｈｅ。这便产生了Ｃａｃｈｅ一致性问题，要求共享数据在各Ｃａｃｈｅ间以及Ｃａｃｈｅ与主存间保持一致。为此出现了多种Ｃａｃｈｅ一致性协议。本文分析了几种类型的一致性协议，并对其进行了软件模拟和性能评价．     

廉价冗余磁盘阵列（RAID）Cache浅析

廉介冗余磁盘陈列技术已掀起研究开发热潮，磁盘Ｃａｃｈｅ技术的研究早在七十年代就已广泛展开，但是关于磁盘阵列Ｃａｃｈｅ技术的专门性研究文献在国内外并不多见。本文论述了磁盘阵列中引入高速缓存Ｃａｃｈｅ的必要性，综述了磁盘阵列Ｃａｃｈｅ技术的国内外技术动态，提出了磁盘阵列Ｃａｃｈｅ研究中的几个关键问题，并阐述了作者的观点。     

VHDL语言及其应用

介绍目前数字电子系统硬件设计的一种标准输入输出工具ＶＨＤＬ语言，并结合小巨型机上Ｄｃａｃｈｅ的设计，用ＶＨＤＬ语言实现ＭＳＣ－Ｄｃａｃｈｅ的控制。     

高性能RISC微处理器硬件仿真器设计

在微处理器设计中，为了系统级软硬件协同仿真，在后端设计前必须采用硬件仿真器对设计进行系统验证．为此，采用FPGA设计32位RISC流水线结构微处理器的硬件仿真器．此设计主要包括以下特点：采用内存管理单元(MMU)可以实现虚拟地址管理；包括片上Cache，其中包括指令Cache(I-Cache)和数据Cache(D-Cache)；采用标准SYSAD接口设计；包括片上乘除处理单元(MDU)；实现精确异常处理．设计采用XILINX公司的xc2v2000实现，其工作频率为30MHz．     

采用动态译码缓存的高速指令集模拟器

指令集模拟器是计算机体系结构研究和SoC软硬件协同设计的重要工具，模拟器的性能和灵活性是影响设计和验证效率的重要因素。解释型指令集模拟器具有很好的灵活性，在操作系统等涉及到自修改代码的模拟中具有不可替代的作用。该文给出了一个高性能解释型指令集模拟器的设计，它具有很高的模拟精度和很好的灵活性；同时指令集模拟器采用了动态译码缓存等优化技术，使其具有很高的模拟性能。以ARM7指令集模拟器为实例，所提出的优化技术同样适用于其它现心RISC体系结构。     

Performance of One''s Complement Caches

On-chip caches to reduce average memory access latency are commonplace in today's commercial microprocessors. These on-chip caches generally have low associativity and small cache sizes. Cache line conflicts are the main source of cache misses, which are critical for overall system performance. This paper introduces an innovative design for on-chip data caches of microprocessors, called one's complement cache. While binary complement numbers have been successfully used in designing arithmetic units, to the best of our knowledge, no one has ever considered using such complement numbers in cache memory designs. This paper will show that such complement numbers help greatly in reducing cache misses in a data cache, thereby improving data cache performance. By parallel computation of cache addresses and memory addresses, the new design does not increase the critical hit time of cache accesses. Cache misses caused by line interference are reduced by evenly distributing data items referenced by program loops across all sets in a cache. Even distribution of data in the cache is achieved by making the number of sets in the cache a prime or an odd number, so that the chance of related data being mapped to a same set is small. Trace-driven simulations are used to evaluate the performance of the new design. Performance results on benchmarks show that the new design improves cache performance significantly with negligible additional hardware cost.     

CMFSim:高可配可扩展的缓存微架构功能模拟器

作为提高CPU读取和存储数据的效率,弥补与主存之间存取速度差距的有效策略,CPU的缓存（Cache）充分利用其对数据使用的局部性原理,对最近或最常使用的数据进行暂存,对CPU的性能起着决定性作用.缓存的微架构正是决定缓存性能的关键性因素.然而,现代先进的CPU缓存都具备极为复杂的结构,存在多种策略、多种硬件算法和多个层级等不同维度的设计,从硬件上直接设计和论证不仅耗时而且成本很高,Cache微架构模拟器正是用软件方法对硬件微架构进行模拟和仿真.设计一款结构优良的缓存,对不同微架构进行评估,是一件具有深远意义的工作.本文从硬件结构出发,设计实现了一款多级、高可配、高可扩展的缓存微架构功能模拟器CMFSim（Cache microarchitecture functional simulator）,实现了常见的缓存策略和硬件算法,可以进行给定配置下的缓存功能的模拟,从而分析配置参数与缓存性能间的关系.     

The design of the 88000 RISC family

The design and implementation of the RISC (reduced-instruction-set computer) 88000 system in high-speed, complementary metal-oxide semiconductor (HCMOS) technology is described. The total system consists of the 88100 processor and two 88200 cache memory management units (CMMUs). The various features and components of the 88000 are discussed     

Path and cache conscious prefetching (PCCP)

Main memory cache performance continues to play an important role in determining the overall performance of object-oriented, object-relational and XML databases. An effective method of improving main memory cache performance is to prefetch or pre-load pages in advance to their usage, in anticipation of main memory cache misses. In this paper we describe a framework for creating prefetching algorithms with the novel features of path and cache consciousness. Path consciousness refers to the use of short sequences of object references at key points in the reference trace to identify paths of navigation. Cache consciousness refers to the use of historical page access knowledge to guess which pages are likely to be main memory cache resident most of the time and then assumes these pages do not exist in the context of prefetching. We have conducted a number of experiments comparing our approach against four highly competitive prefetching algorithms. The results shows our approach outperforms existing prefetching techniques in some situations while performing worse in others. We provide guidelines as to when our algorithm should be used and when others maybe more desirable.     

Improving Data Prefetching Efficacy in Multimedia Applications

The workload of multimedia applications has a strong impact on cache memory performance, since the locality of memory references embedded in multimedia programs differs from that of traditional programs. In many cases, standard cache memory organization achieves poorer performance when used for multimedia. A widely-explored approach to improve cache performance is hardware prefetching, which allows the pre-loading of data in the cache before they are referenced. However, existing hardware prefetching approaches are unable to exploit the potential improvement in performance, since they are not tailored to multimedia locality. In this paper we propose novel effective approaches to hardware prefetching to be used in image processing programs for multimedia. Experimental results are reported for a suite of multimedia image processing programs including MPEG-2 decoding and encoding, convolution, thresholding, and edge chain coding.     

32位嵌入式RISC微处理器的设计

ＮＲＳ４０００微处理器是西北工业大学航空微电子中心设计的３２位嵌入式ＲＩＳＣ微处理器,在指令系统级与Ｉｎｔｅｌ的８０９６０ＫＡ完全兼容,具有自主版权,规模约３０万等效门。在微体系结构上采用了ＲＩＳＣ核心结构,提出了一种基于核心ＲＩＳＣ微操作的设计方案,具有简单,通用,灵活的特征,而且处理器开发更细粒度的并行性提供了可能,结合多执行部件,流水执行和乱序执行等先进技术,使得ＮＲＳ４０００既实现了与８０     

An Application-Driven Study of Multicast Communication for Write Invalidation

In distributed shared-memory (DSM) multiprocessors, a write operation requires multiple messages to invalidate the nodes which share and cache the memory block to being written. The consequent write stall time impedes the performance of such systems. An effective means of achieving efficient invalidation is to employ multicast messages to reach the sharing nodes. This study evaluates two multicast-based invalidation schemes, dual-path and pruning, by performing application-driven simulation. The experimental settings used herein find that multicasts improve invalidation traffic for four of the six evaluated real applications. The remaining two applications are computationally intensive, and multicast-based invalidation is less effective. However, since multicasts encourage bursty communication, our results indicate that they help relieve network congestion during these periods. Dual-path performs slightly better than pruning, because it is less sensitive to routing delay in the routers. Our results further demonstrate that cache size is an important design parameter for multicast-based invalidation, and is highly effective for DSM multiprocessors with larger caches.