High Performance RF Passive Integration on a Si Smart Substrate for Wireless Applications

To achieve cost and size reductions, we developed a low cost manufacturing technology for RF substrates and a high performance passive process technology for RF integrated passive devices (IPDs). The fabricated substrate is a conventional 6“ Si wafer with a 25 μm thick SiO₂ surface. This substrate showed a very good insertion loss of 0.03 dB/mm at 4 GHz, including the conductive metal loss, with a 50 Ω coplanar transmission line (W=50 μm, G=20 μm). Using benzo cyclo butene (BCB) interlayers and a 10 μm Cu plating process, we made high Q rectangular and circular spiral inductors on Si that had record maximum quality factors of more than 100. The fabricated inductor library showed a maximum quality factor range of 30‐120, depending on geometrical parameters and inductance values of 0.35‐35 nH. We also fabricated small RF IPDs on a thick oxide Si substrate for use in handheld phone applications, such as antenna switch modules or front end modules, and high‐speed wireless LAN applications. The chip sizes of the wafer‐level‐packaged RF IPDs and wire‐bondable RF IPDs were 1.0‐1.5 mm² and 0.8‐1.0 mm², respectively. They showed very good insertion loss and RF performances. These substrate and passive process technologies will be widely utilized in hand‐held RF modules and systems requiring low cost solutions and strict volumetric efficiencies.     

高可靠先进微系统封装技术综述

在人工智能、航空航天、国防武器装备电子系统小型化、模块化、智能化需求驱动下,系统级封装设计及关键工艺技术取得了革命性突破。新型的系统封装方法可把不同功能器件集成在一起,并实现了相互间高速通讯功能。封装工艺与晶圆制造工艺的全面融合,使封装可靠性、封装效率得到极大的提升,封装寄生效应得到有效抑制。文章概述了微系统封装结构及类型,阐述了高可靠晶圆级芯片封装(WLP)、倒装焊封装(BGA)、系统级封装(SIP)、三维叠层封装、TSV通孔结构的实现原理、关键工艺技术及发展趋势。     

System on Wafer: A New Silicon Concept in SiP

System integration is clearly a driving force for innovation in packaging. The need for miniaturization has led to new architectures that combine disparate technologies and materials. Today several different approaches have been developed. These include technologies like system in package. In this way, a new concept for heterogeneous integration is currently being developed at CEA-LETI and is called system on wafer (SoW). This concept is based on a chip to wafer approach. Every component is achieved by using wafer-level technologies, and the final system is performed by single component mounting on a silicon substrate. The main strength of this approach is to use silicon as a substrate for components and for basic support. To perform the SoW, a generic technological toolbox is needed. This includes every standard packaging technology such as flip chip, signal rerouting, and passive component integration as well as new advanced technologies such as microelectromechanical systems packaging, advanced interconnections, energy source integration, integrated cooling, or silicon through vias. In this paper, the SoW concept will be presented and the generic toolbox for SoW achievement will be described.      

Characterization of novel varistor+inductor integrated passive devices

This letter describes the design, modeling, simulation, and fabrication of novel integrated passive devices (IPDs). These IPDs, comprising of a cofired multilayered varistor and inductor, have been developed in the ceramic coprocessing technology. The equivalent model of the new structures is presented, suitable for design and circuit simulations. The fabrication method, new design of structures and patented materials of these devices lead to improved characteristics suitable for application in high-frequency suppressors. The IPDs were tested in the frequency range of 1 MHz-3 GHz using an Agilent 4287A RF LCR meter. The measurements confirm the validity of the proposed model.     

用于MEMS器件芯片级封装的金-硅键合技术研究

MEMS器件大都含有可动的硅结构 ,在器件加工过程中 ,特别是在封装过程中极易受损 ,大大影响器件的成品率。如果能在MEMS器件可动结构完成以后 ,加上一层封盖保护 ,可以显著提高器件的成品率和可靠性。本文提出了一种用于MEMS芯片封盖保护的金 硅键合新结构 ,实验证明此方法简单实用 ,效果良好。该技术与器件制造工艺兼容 ,键合温度低 ,有足够的键合强度 ,不损坏器件结构 ,实现了MEMS器件的芯片级封装。我们已经将此技术成功地应用于射流陀螺的制造工艺中     

芯片制造的电化学处理技术

电化学处理技术的性价比优势在芯片制造上是一个范例转移。Cu芯片金属化的双大马士革处理和面阵列芯片封装互连的C4(倒装)技术使电化学技术置于最复杂的制造工艺技术之间。这些工艺技术被集成到用于芯片制造的300mm晶圆处理中。新材料和工艺的持续发展来满足微处理器件不断增加性能和小型化的趋势。电迁移问题和集成超低k电介质材料与Cu镀层的新抛光方法是芯片制造中的一个关键问题。发展一个适用成本低的无铅C4芯片封装互连是微电子工业的主要目标,微电子工业正作努力在几年里市场化无铅产品。     

Use of voltage stressing at wafer probe for reliability predictions

In two independent evaluations, good correlation has been found between I_DDQ degradation due to voltage stressing at wafer probe and the reliability of devices built from a given wafer or wafer lot. This provides a useful reliability predictor and screening tool at the wafer level. This technique also provides a useful vehicle for the manufacturing facility to better understand and modify those portions of their wafer fabrication process where reliability improvements are warranted. The usefulness of this method should be applicable to evolving integrated circuit (IC) manufacturing technologies that have reduced feature sizes and operating voltages, provided proper precautions are taken in the selection of voltage stress values     

Ultra CSPTM-a wafer level package

There has been a significant amount of work over the past five years on chip scale packaging. The majority of this work has been an extension of conventional integrated circuit (IC) packaging technology utilizing either wire bonders or tape automated bonding (TAB)-type packaging technology. Handling discrete devices during the IC packaging for these type of chip scale packages (CSPs) has resulted in a relatively high cost for these packages. This paper reports a true wafer level packaging (WLP) technology called the Ultra CSP^TM. One advantage of this WLP concept is that it uses standard IC processing technology for the majority of the package manufacturing. This makes the Ultra CSP ideal for both insertion at the end of the wafer fab as well as the facilitation of wafer level test and burn-in options. This is especially true for dynamic random access memory (DRAM) wafers. Wafer level burn-in and wafer level processing can be used for DRAM and other devices as a way to both reduce cost and improve cycle time. Thermal cycling results for Ultra CSPs with a variety of package sizes and input/output (I/O) counts are presented. These test vehicles, assembled to FR-4 boards without underfill, cover a range of footprints typical of flash memory, DRAM and other devices. The electrical and thermal performance characteristics of the Ultra CSP package technology are discussed     

Wafer-level chip scale packaging: benefits for integrated passivedevices

Chip scale packaging continues to draw attention for applications that require high performance or small form factor solutions. The term chip scale package (CSP) has become synonymous with “fine pitch BGA” as the distinction between a ball grid array (EGA) and some chip scale packages becomes nearly indistinguishable. The cost of chip scale packages also continues to draw attention as one of the barriers to wide scale industry adoption. Sometimes lost in the chip scale debate is the discussion about wafer level chip scale packages, which offer the fastest path to small form factor, high performance and cost effective solutions. In this paper, we describe an approach to wafer level chip scale packaging that is an extension of integrated passive device processing, which results in low cost     

LTCC package for high temperature applications

There is a growing demand for sensors and electronics that can work in harsh environments and at high temperature. Applications include sensors and actuators for control in petroleum and geothermal industry, process monitoring and distributed control systems in the automotive and aerospace fields. Process development and packaging materials for electronic devices are closely connected to such packaging issues. In many cases the package is as important as the device itself in meeting the applications needs.Low temperature co-fired ceramics (LTCC) and thick-film technologies have the potential to incorporate multilayer structures, enabling fabrication of specialized packaging systems. LTCC technology enables easy electrical or optical connections within and between layers in addition to enabling use of integrated passive components, heaters, sensors, converters etc.This paper presents attempts to develop a reliable packaging technology for silicon carbide (SiC) based hydrogen sensors operating at temperatures up to 300 °C. Some simulations of thermal properties were carried out and package structures were made and investigated. The package protects the sensor against mechanical damage and makes possible easy electrical connections. Moreover, the heater and temperature sensors allow for proper temperature regulation of the element. The manufacturing process, basic electrical parameters of the integrated heater as well as real temperature distribution are presented.     

Methods for passive fiber chip coupling of integrated opticaldevices

A useful technique for high precision passive coupling of single mode optical fibers to integrated optical devices is crucial for cost effective packaging especially in multiport devices like switches (N×N) and other WDM components. These devices were fabricated on two different material bases, silicon on insulator (SOI) and polymers. In both cases the waveguides are based on the oversized rib waveguide concept and utilize silicon as a substrate. Two possible fabrication processes for this passive fiber chip coupling IN or ON silicon are presented and compared. The first approach involves a technology similar to flip chip fabrication using a sub- and superstrate, that allows separate processing of v-grooves for fiber alignment and the integrated optical devices. The self aligned mounting of the chip is achieved by a v-shaped rib-groove combination created by wet chemical etching, where the rib is the exact negative of the groove so that the flip chip is put on precisely defined crystal planes rather than on sensitive edges, which would be the case when using rectangular alignment ribs. The second approach utilizes the same chip for waveguides and fiber alignment structures which makes it possible to define both in the same lithographic step and thereby eliminating any vertical displacement. Processing difficulties arise primarily from completely different processing requirements of fiber aligning v-grooves and integrated waveguides. The need to define patterns of the size of only several microns (μm) in the proximity to deep grooves makes the use of an electrophoretic photoresist necessary that is deposited via galvanic means on the extremely nonplanar surface. Both processes allow for fiber chip alignment precisions in the sub-μm range which was also experimentally verified with coupling losses as low as 0.7 dB per end-face. The fabrication processes along with experimental and theoretical results are presented     

Optics and electronics are living together

The differences between optoelectronic and electronic ICs are identified. Crystal growth and device fabrication techniques for optoelectronic ICs are discussed, focusing on their advantages and disadvantages. Two novel devices that exist only as discrete components and will perform even better when integrated with other components on a monolithic chip are highlighted. One is an integrated passive cavity laser, which overcomes one of the drawbacks of semiconductor lasers, i.e. that they emit light over a relatively wide spectral band and are thus less coherent than other lasers. The other is a surface-emitting laser which emits light normal to its top surface and can therefore be placed anywhere on the substrate     

声表面波器件晶圆键合工艺研究

声表面波器件向小型化、集成化、更高性能方向发展,需要制作复合单晶薄膜和采用晶圆级封装。该文针对关键工艺中的晶圆键合工艺开展研究,提出工艺要求,简述有关键合工艺要求和设备特点,并进行了金属键合工艺验证。实验证明,设备和工艺能满足产品封装要求。     

Isolation on Si wafers by MeV proton bombardment for RF integratedcircuits

This paper studies issues related with using high energy protons to create local semi-insulating silicon regions on IC wafers for device isolation and realization of high-Q IC inductors. Topics on two approaches, i.e., one using Al as the radiation mask and the other using proton direct-write on wafers were studied. It was shown that Al can effectively mask the proton bombardment of 15 MeV up to the fluence of 10¹⁷ cm^-2. For the unmasking direct write of the proton bombardment, isolation in the silicon wafer can be achieved without damaging active devices if the proton fluence is kept below 1×10¹⁴ cm^-2 with the substrate resistivity level chosen at 140 Ω-cm, or kept at 1×10¹⁵ cm ^-2 with the substrate resistivity level chosen at 15 Ω-cm. Under the above approaches, the 1 h-200°C thermal treatment, which is necessary for device final packaging, still gives enough high resistivity for the semi-insulating regions while recovering somewhat the active device characteristics. For the integrated passive inductor fabricated on the surface of the silicon wafer, the proton radiation improves its Q value     

WLCSP封装技术中的集成无源器件

芯片规模封装技术一直倍受高性能、小形状因素解决方案在各类应用中的关注。芯片规模封装与球栅阵列(BGA)封装之间的区别变得不可分辨,已成为“细间距BGA”的同义词。芯片规模封装成本也是业界关注的焦点之一。芯片规模晶圆级封装是提供小形状、高性能和低成本的最快途径。论述了集成无源器件加工、低成本化的晶圆级芯片规模封装技术。     

Integrated optics approach for advanced semiconductor lasers

Recent advances in the field of semiconductor integrated optics are reviewed from the point of view of monolithic integration of semiconductor lasers and other optical components and/or devices. Emphasis is placed on dynamic-single-mode (DSM) lasers, such as DFB and DBR lasers, intended for highly stable single-wavelength light sources for such monolithic integration. The realization of high-performance DSM lasers and the fabrication techniques of monolithically integrated optical devices and circuits are briefly reviewed. A variety of potential applications is discussed.     

Silicon Bench for Passive Coupling and Packaging of High-Frequency Optoelectronic Devices

Coupling and packaging have become decisive factors in the final performance and cost of high-frequency optoelectronic devices. Here, we report the design and successful fabrication of a silicon bench that integrates a V-groove and high-frequency coplanar waveguide (CPW) on the same high-resistivity silicon wafer as an effective optoelectronic packaging solution     

Statistical design of experiments and analysis on gate poly-silicon critical dimension

Gate poly-silicon critical dimension is one of the most important characteristics of up-to-date integrated circuit devices. Hence, in a semiconductor wafer fabrication process, gate poly-silicon critical dimension control is inevitable in order to achieve a competitive net-die-per-wafer yield as well as electrically acceptable device test characteristics. This paper presents a framework for statistical design of experiments and analysis on gate poly-silicon critical dimension. Three typical types of design of experiments are considered: 1) a nested design; 2) a randomized complete block design; and 3) a factorial design. With these designs, relevant linear statistical models are established. Based on the models, the analysis of variance technique and Duncan's multiple range tests are chosen as major methodologies not only to estimate related variance components but also to test uniformity on gate poly-silicon critical dimension. Statistical analyses are illustrated with experimental datasets from real pilot semiconductor wafer fabrication processes. Results show that: 1) according to the sources of variation, variance components are estimated separately, and 2) distinctive patterns of gate poly-silicon critical dimension can be detected with statistical significance. Consequently, the framework in this study can provide guidelines to practitioners on the variance components estimation as well as the uniformity test in parallel for any characteristic datasets collected from similar designs in a semiconductor wafer fabrication process.     

Analytic modeling, optimization, and realization of cooling devicesin silicon technology

A novel cooling device fully built in silicon technology is presented. The new concept developed in this work consists of micromachining the bottom side of the circuit wafer in order to embed heat sinking microchannels directly into the silicon material. These microchannels are then sealed, by a direct wafer bonding procedure, with another silicon wafer where microchannels and inlet-outlet nozzles are micromachined too. A cooling fluid (water) is then forced through the array of channel to convey heat outside the chip. Such a configuration presents advantages to provide a significant reduction of the cooler overall dimensions, to reduce the number of the involved materials and to be compatible with integrated circuit fabrication procedures, In this study analytical tools were used in order to get a global evaluation of all the thermal resistances characteristic of such devices. Using these adequate analytic models with appropriate approximations, a global optimization procedure was then applied and led to the definition of he optimum dimensions of the silicon micro heat sink. The realization procedure was then carried out in a clean room environment. First experimental characterization results obtained from the earlier prototypes demonstrated that the thermal properties of this silicon-based cooling device are satisfactory and can be reasonably compared to those of commercially available copper micro heat sinking components     

硅通孔互连技术的开发与应用

随着三维叠层封装、MEMS封装、垂直集成传感器阵列以及台面MOS功率器件倒装焊技术的开发,硅通孔互连技术正在受到越来越广泛的重视和研究。本文叙述了几种硅通孔互连的制造方法,及其应用。最后,进一步阐述了硅通孔互连中几项关键技术的研究现状以及存在的挑战。