非制冷焦平面探测器牺牲层制备工艺研究

研究了牺牲层制备的工艺过程。通过对牺牲层材料选择、牺牲层图形化及牺牲层固化等工艺技术的研究,获得了图形质量较好的牺牲层样品。建立了优化的牺牲层制备工艺制度,为探测器的后续研究奠定了基础。     

MEMS器件牺牲层腐蚀释放技术研究

以非制冷红外焦平面阵列和热剪切应力传感器为代表,分析了这两种典型的薄膜悬浮结构和带空腔结构的MEMS器件在进行二氧化硅牺牲层的腐蚀和最终结构释放过程中的各种问题。根据二氧化硅的腐蚀机理,指导了对腐蚀孔(槽)的设计,通过测量不同条件下的腐蚀速度,得出升温、超声、适时更换腐蚀液是加快腐蚀速度的方法,基于粘连现象中拉起长度的概念,提出基于硅衬底下突点制作及释放牺牲层的方法,并获得了成功释放。     

基于微机械的多孔硅牺牲层技术

多孔硅作为一种牺牲层材料 ,在表面硅微机械加工技术中有着重要的应用。文中综合讨论了三种不同的多孔硅牺牲层技术 ,并用后两种“在低掺杂衬底上的多孔硅牺牲层技术”,制作了良好的悬空微薄膜结构 ,同时对多孔硅表面的薄膜淀积 ,和制备过程中的掩膜材料等进行了分析 ,为利用多孔硅工艺制作各种 MEMS器件奠定了基础。     

一种新型微机械锚

在不增加薄膜层数的前提下设计出一种新型的薄膜微机械锚结构。新型微机械锚与传统微机械锚相比具有更大的厚度和合理的形状 ,其刚度得到很大增强。有限元的模拟表明 ,新型微机械锚不仅能向连接在其结构上的其他微结构提供更高的支撑力 ,还提供了更接近于固支的支撑边界条件     

RF MEMS工艺中牺牲层的去除方法研究

研究了MEMS开关聚酰亚胺牺牲层的去除，通过添加少许碳粉，能够减少刻蚀时间。讨论了在这种刻蚀情况下刻蚀温度和刻蚀时间之间的关系。此研究应用在表面微细加工工艺中，对MEMS加工具有重要的参考价值。该研究还可应用于RF MEMS开关、可调电容、高Q值悬臂电感、MOSFET等制造工艺中。     

Generation of Monodisperse,Shape‐Controlled Single and Hybrid Core–Shell Nanoparticles via a Simple One‐Step Process

In nano‐biotechnology, optoelectronics, and energy research areas, various fabrication methods have been developed for hybrid nanoparticles. A method is developed here for fabricating highly monodisperse three‐dimensional hybrid nanoparticles using a unique top‐down method based on secondary sputtering lithography. Nanostructures that have been formed on a PEDOT sacrificial layer are transferred from the substrate to an aqueous solution in a process that could be used to successfully disperse a variety of nanoparticle shapes and hybrid nanoparticles. By this method, a fluorescent dye could be encapsulated within the fabricated hybrid nanoparticles for use in bio‐sensing and drug‐delivery applications     

OEIC台面腐蚀工艺研究

深入研究了牺牲层腐蚀机制,摸索出完整的台面自停止工艺并实际应用于OEIC器件制作。实验中发现了侧蚀、台面变形以及表面清洁等问题。从实验现象着手分析,并由此对工艺进行了改进,采用了新的腐蚀剂和工艺步骤。改进后的工艺解决了上述问题,可以完全满足后续工艺的要求。     

微结构制备中选择性多孔硅牺牲层技术的研究

利用多孔硅形成的选择性。在指定的硅衬底区域制作多孔硅作牺牲层，提出了制作微结构，后进行阳极氧化，形成多孔硅牺牲层的工艺，由此制备出了良好的悬空结构，并对多孔硅形成的选择性、掩模材料和工艺条件进行了研究。     

微加工电化学沉积锌牺牲层工艺

在微加工中通过电化学沉积Zn制备牺牲层从而制备悬空结构。电化学沉积Zn牺牲层工艺具有易获取牺牲层,去除快速,腐蚀选择性好,耐高温等优点。在电化学沉积Zn牺牲层工艺中易遇到与基底结合力不够、使用高温工艺时易产生气泡、打磨后残留杂质、去除牺牲层时残留难去物和悬空结构释放时易黏附等问题,通过在Ti/Cu电镀种子层上预镀Ni薄层获使用Ti/Au电镀种子层、慢速升温的预真空高温烘烤、电解稀碱液法和氧化清洗、使用丙酮和F117进行应力释放等方法改进工艺后可以克服这些问题。电化学沉积Zn牺牲层工艺是较为理想的制备悬空结构的工艺。     

High-throughput fabrication of <Emphasis Type="Italic">infinitely</Emphasis> long 10 nm slit arrays for terahertz applications

In pursuit of higher field enhancement and applications in terahertz frequency regime, many techniques have been developed and reported for fabrication of high-aspect-ratio metallic nanostructures. While techniques utilizing spacer deposition has successfully overcome the size limit of conventional fabrication tools, they suffer from low throughput or vulnerability to mechanical and chemical treatment, limiting their further application to various fields. In this Letter we report a high-throughput scheme for fabricating metallic gap structures, free from all the aforementioned shortcomings. Vertically aligned gaps are first defined with photolithography and atomic layer deposition, and then made suitable for transmission measurements by etching out predefined sacrificial layers. Existence of the sacrificial layers alleviates many requirements associated with fabrication steps, thereby increasing the overall reliability of the whole process. Using this method we fabricate arrays of 10 nm wide metallic slits whose length is only limited by the substrate size, here 1 cm, and then characterize the sample with terahertz time domain spectroscopy. The sample show steady performance of up to 2500-fold field enhancement even after sonication under various solvents.     

Printing of Highly Integrated Crossbar Junctions

A new process is presented that combines nanoimprint lithography and soft lithography to assemble metal–bridge–metal crossbar junctions at ambient conditions. High density top and bottom metal electrodes with half‐pitches down to 50 nm are fabricated in a parallel process by means of ultraviolet nanoimprint lithography. The top electrodes are realized on top of a sacrificial layer and are embedded in a polymer matrix. The lifting of the top electrodes by dissolving the sacrificial layer in an aqueous solution results in printable electrode stamps. Crossbar arrays are noninvasively assembled with high yield by printing the top electrode stamps onto bare or modified bottom electrodes. A semiconducting and a quasi metal like conducting type of polymer are incorporated in the cross points to form metal‐polymer‐metal junctions. The electrical characterization of the printed junctions revealed that the functional integrity of the electrically addressed conductive polymers is conserved during the assembling process. These findings suggest that printing of electrodes represents an easy and cost effective route to highly integrated nanoscale metal‐bridge‐metal junctions if imprint lithography is used for electrode fabrication.     

MicroPen direct-write deposition of polyimide

Polyimide has been widely used as structural or sacrificial material in MEMS device fabrication. However, all the typical methods for processing polyimide are based on lithographic technique, which are time-consuming, expensive and non-flexible. In this paper, we propose a novel approach for depositing polyimide patterns by the microPen direct-write deposition technique, which is CAD direct-driven, maskless, rapid-prototyping, and diverse materials integration. Material and device for the microPen direct-write deposition of polyimide technique are presented in detail, and the influences of direct-writing parameters, such as extrusive gas–pressure, direct-writing velocity and the tip-to-substrate distance, on the profile of the deposited polyimide pattern are discussed. Using commercial gold paste (Au) as the structural layer material and polyimide as the sacrificial layer, a micro air-bridge array is successfully fabricated by the microPen direct-write deposition technique, which shows its potential applications in the area of MEMS device fabrication.     

A hybrid Nb/CMOS integration process for superconducting tunneljunction imaging arrays

A process for hybrid superconductor/CMOS integration was developed for the fabrication of extremely sensitive color-imaging arrays using superconducting tunnel junctions. A Nb-AlO_x-Nb process was used to fabricate arrays of junctions directly on top of CMOS devices. The CMOS wafers required the development of a planarization process suitable for subsequent tunnel-junction fabrication. The process involved the deposition of a sacrificial oxide layer by electron cyclotron resonance plasma-enhanced chemical vapor deposition, chemical-mechanical polishing, and a layer of spin-on glass. A process was also developed for via contacts through the oxide layer that optimized the stability of the contacts. The critical current spreads of the arrays (50 junctions) were as small (spread about 1% for 3 μm × 3 μm junctions) as on bare silicon wafers     

Excimer Laser Projection Photoablation Patterning of Metal Thin Films for Fabrication of Microelectronic Devices and Displays

A nonlithographic process is demonstrated for patterning Al, Cr, Cu, Ni, Ti, and W thin films, which are widely used in microelectronic and display fabrication. A projection photoablation process using 248-nm-deep ultraviolet radiation from a KrF excimer laser was used to pattern a polyimide film coated on a SiN layer deposited on glass. The photoablation-patterned polyimide film was used as a sacrificial layer in a lift-off patterning process for the metal films, which resulted in clean metal patterns with fine line-edge definition being fabricated after lift-off. This process provides a simpler and more economical patterning technique compared to conventional lithography methods, eliminating the developing and etching steps.     

A new simple and reliable method to form a textured Si surface forthe fabrication of a tunnel oxide film

In this work, a textured Si surface was formed with a new simple and reliable method for tunnel oxide fabrication. First, a thin poly-Si layer (12 nm thick) was deposited on Si surface and a 30-nm thick dry oxide film was then grown in O₂ ambient. This oxide film was served as a sacrificial oxide. The poly-Si film and Si substrate were both oxidized during thermal oxidization. After stripping this sacrificial oxide, a textured Si surface was obtained. Tunnel oxide grown on this textured Si surface has asymmetrical J-E characteristics, less interface states generation and better reliability (larger Q_bd ) as compared to those of normal oxide     

MEMS/Sensor工艺中无定形碳应用及干法蚀刻研究

提出一套新的无定型碳牺牲层蚀刻工艺,新工艺应用于MEMS和Sensor牺牲材料工艺中,能够很好地解决无定形碳蚀刻工艺中有机副产物问题。在无定形碳蚀刻工艺中添加低浓度的CF4蚀刻气体(1%~5%),有助于去除在蚀刻过程中侧壁形成的有机副产物。在无定形碳蚀刻工艺前添加一步光刻胶硬化步骤,和在无定形碳蚀刻工艺后添加一步有机副产物各项异性蚀刻步骤,有助于去除表面产生的有机副产物。并针对新工艺去除无定形碳蚀刻过程中形成的有机副产物反应机制进行了详尽阐述与讨论。     

High-performance poly-Si TFTs on plastic substrates using a nano-structured separation layer approach

We demonstrate a manufacturable, large-area separation approach for producing high-performance polycrystalline silicon thin-film transistors on flexible plastic substrates. The approach allows the use of high growth-temperature gate oxides and removes the need for hydrogenation. The process flow starts with the deposition of a nano-structured high surface-to-volume ratio film on a reuseable "mother" substrate. This film functions as a sacrificial release layer and is Si-based for process compatibility. After high-temperature TFT fabrication (up to 1100/spl deg/C) is carried to completion on the sacrificial film coated mother substrate, a thick plastic top layer film is applied, and the sacrificial layer is removed by chemical attack. By using this separation process, the temperature, smoothness, and mechanical limitations posed by plastic substrates are completely circumvented. Both excellent n-channel and p-channel TFTs on plastic have been produced. We report here on p-channel TFTs on separated plastic with a linear field effect (hole) mobility of 174 cm/sup 2//V/spl middot/s, on/off current ratio of >10/sup 8/ at V/sub ds/=-0.1 V, off current of <10/sup -11/ A//spl mu/m-channel-width at V/sub ds/=-0.1 V, sub-V/sub t/ swing of /spl sim/200 mV/dec, and threshold voltage of -1.1 V.     

(中国微米纳米)一种牺牲层工艺中金属电极保护方法研究

为了在牺牲层工艺中保护金属电极不被腐蚀,提出了一种利用铝层保护金属电极的方法。在试验中采用了两种铝保护层厚度300nm和1μm,在两种腐蚀液体4NH4F:1HF:2甘油和1HAC: 1NH4F中进行了试验,通过试验表明,铝金属层在两种腐蚀液体中都能够有效保护金属电极,延长牺牲层的腐蚀时间。最后,通过SOI微加速度计加工工艺进一步验证了该方法的有效性。     

多晶硅微机械开关

利用LPCVD SiO2和多晶硅作牺牲层和悬臂梁技术,解决了多晶硅应力释放问题以及微机械开关工艺与IC工艺兼容技术问题,获得了淀积弱张应力的多晶硅膜的最佳工艺条件,研制出多晶硅微机械开关.初步测试出其开关的开启电压为89V,开关速度为5μs,这为研制用于雷达和通讯的全单片集成的RF MEMS开关系统打下了基础.     

多晶硅微机械开关

利用LPCVD SiO2和多晶硅作牺牲层和悬臂梁技术,解决了多晶硅应力释放问题以及微机械开关工艺与IC工艺兼容技术问题,获得了淀积弱张应力的多晶硅膜的最佳工艺条件,研制出多晶硅微机械开关.初步测试出其开关的开启电压为89V,开关速度为5μs,这为研制用于雷达和通讯的全单片集成的RF MEMS开关系统打下了基础.