Associative processors and memories: a survey

The functional structure of a classical content-addressable memory (CAM) and its realization at the transistor level are described. Some unorthodox CAM approaches are briefly examined. Associative processor systems are discussed, and application-specific CAM architectures to support artificial intelligence features are surveyed. Limitations of associative processing and ways to circumvent them are addressed. The use of parallel cellular logic is considered     

The AM3 associative processor

As an associative 32-bit processor based on a modified Harvard architecture, the Associative Microprogrammable Multipurpose Monoprocessor (AM³) uses a standard address-bus system to handle von Neumann data and instructions. A separate addressless associative bus system links it to associative memory components. Its microprogrammability enables the AM³ to adapt to a variety of associative memory circuits. After discussing the AM³ architecture and programming environment, we present two application paradigms     

ACE: An Associative Calculus Data Structure

The associative calculus is a methodology for problem solving using a natural-language interface. Associative calculus environment (ACE) is a language designed to eliminate ambiguities and misunderstandings that can occur when using English. ACE uses tables and charts as the basic data structure and is based on associative computing which uses content-addressable memory and responders. Parallelism is inherent in the ACE data structure and the expression syntax used for processing the referenced data. Thus, the programmer need not explicitly think about parallel constructs.     

Flag-oriented parallel associative architectures and applications

Flag transformation, a new design concept for parallel associative memory and processor architectures, maps word-oriented data into flag-oriented data. A flag vector represents each word in a set. The flag position corresponds to the value of the transformed word, and all flags in a vector are processed simultaneously to obtain parallel operations. The results of complex search operations performed by modular, cascadable hardware components are also represented by flags and retransformed into word-oriented data. This transformation method allows parallel processing of associative or content-addressable data in uniprocessor architectures, expedites IC design rule checks, and accelerates complex memory tests. It can also be used to develop associative processor architectures and to emulate very fast, modular, cascadable artificial neural networks     

基于一种新型联想记忆神经网络的传感器故障诊断

联想记忆网络是一种反馈型神经网络。由于反馈型网络会收敛于某个稳定状态，因此，可用于联想记忆。神经网络具有高度的并行处理能力和极强的非线性映射能力，可以实现故障与征兆之间复杂的非线性映射关系，因此在机械故障诊断领域中显示了很大的应用潜力。本文以模拟人脑由部分记忆而联想整体的特点为基础，通过引入联想记忆衰减因子，改进神经网络结构和学习算法．应用于系统的故障诊断。     

语音词汇网单词联想记忆

语音联想记忆是一种高效的记忆方法。为了给学习者提供语音联想的素材,引导学习者进行语音联想,熟悉读音规则,加深对单词拼写和发音的记忆,帮助学习者建立字母组合与相关发音间的双向认知,提出一种基于语音的词汇网。语音词汇网是基于常见字母组合和单词读音之间的差异构建的,因此其中既包含了语音近似度信息,也包含了一定的单词结构信息。利用该网络,学习系统不但可以实现语音联想功能,还能提供语音方面的相关统计信息。语音词汇网的引入能进一步完善单词学习系统的联想记忆功能。     

A general-purpose CMOS associative processor IC and system

An associative processor architecture that integrates the functionality of content-addressable memory (CAM), functional memory (FM), and associative parallel processors (APPs) in a single-chip architecture is described. The hardware design, environment and applications of the Coherent Processor, a microchannel memory device designed by combining 16 such chips, are discussed. It is shown that the processor's writable control store permits quick execution of application-specific microcoded operations     

Cellular matrix model for parallel combinatorial optimization algorithms in Euclidean plane

We propose a parallel computation model, called cellular matrix model (CMM), to address large-size Euclidean graph matching problems in the plane. The parallel computation takes place by partitioning the plane into a regular grid of cells, each cell being affected to a single processor. Each processor operates on local data, starting from its cell location and extending its search to the neighborhood cells in a spiral search way. In order to deal with large-size problems, memory size and processor number are fixed as O(N), where N is the problem size. Then one key point is that closest point searching in the plane is performed in O(1) expected time for uniform or bounded distribution, for each processor independently. We define a generic loop that models the parallel projection between graphs and their matching, as executed by the many cells at a given level of computation granularity. To illustrate its efficacy and versatility, we apply the CMM, on GPU platforms, to two problems in image processing: superpixel segmentation and stereo matching energy minimization. Firstly, we propose an extended version of the well-known SLIC superpixel segmentation algorithm, which we call SPASM algorithm, by using a parallel 2D self-organizing map instead of k-means algorithm. Secondly, we investigate the idea of distributed variable neighborhood search, and propose a parallel search heuristic, called distributed local search (DLS), for global energy minimization of stereo matching problem. We evaluate the approach with regards to the state-of-the-art graph cut and belief propagation algorithms. For each problem, we argue that the parallel GPU implementation provides new competitive quality/time trade-offs, with substantial acceleration factors as the problem size increases.     

Image understanding architecture: exploiting potential parallelismin machine vision

A hardware architecture that addresses at least part of the potential parallelism in each of the three levels of vision abstraction, low (sensory), intermediate (symbolic), and high (knowledge-based), is described. The machine, called the image understanding architecture (IUA), consists of three different, tightly coupled parallel processors; the content addressable array parallel processor (CAAPP) at the low level, the intermediate communication associative processor (ICAP) at the intermediate level, and the symbolic processing array (SPA) at the high level. The CAAPP and ICAP levels are controlled by an array control unit (ACU) that takes its directions from the SPA level. The SPA is a multiple-instruction multiple-data (MIMD) parallel processor, while the intermediate and low levels operat in multiple modes. The CAAPP operates in single-instruction multiple-data (SIMD) associative or multiassociative mode, and the ICAP operates in single-program multiple-data (SPMD) or MIMD mode     

The IXM2 parallel associative processor for AI

Describes the IXM2 associative processor and its main application in speech-to-speech translation. The IXM2 is a semantic memory system machine that began as a faithful implementation of the NETL semantic network machine and grew into a massively parallel SIMD machine that has demonstrated the power of large associative memories. Such processors can support robust performance in speech applications. In fact, the IXM2 with 73 transputers has outperformed a Cray in some language-translation tasks. We selected speech-to-speech translation as our main application because it is one of the grand challenges of massively parallel artificial intelligence. The social implications of successful automatic translation are enormous-e.g. people who speak different languages could communicate in real time by using interpreting telephony     

A parallel processing VLSI BAM engine

In this paper emerging parallel/distributed architectures are explored for the digital VLSI implementation of adaptive bidirectional associative memory (BAM) neural network. A single instruction stream many data stream (SIMD)-based parallel processing architecture, is developed for the adaptive BAM neural network, taking advantage of the inherent parallelism in BAM. This novel neural processor architecture is named the sliding feeder BAM array processor (SLiFBAM). The SLiFBAM processor can be viewed as a two-stroke neural processing engine, It has four operating modes: learn pattern, evaluate pattern, read weight, and write weight. Design of a SLiFBAM VLSI processor chip is also described. By using 2-mum scalable CMOS technology, a SLiFBAM processor chip with 4+4 neurons and eight modules of 256x5 bit local weight-storage SRAM, was integrated on a 6.9x7.4 mm(2) prototype die. The system architecture is highly flexible and modular, enabling the construction of larger BAM networks of up to 252 neurons using multiple SLiFBAM chips.     

A generalized processor mapping technique for array redistribution

In many scientific applications, array redistribution is usually required to enhance data locality and reduce remote memory access in many parallel programs on distributed memory multicomputers. Since the redistribution is performed at runtime, there is a performance trade-off between the efficiency of the new data decomposition for a subsequent phase of an algorithm and the cost of redistributing data among processors. In this paper, we present a generalized processor mapping technique to minimize the amount of data exchange for BLOCK-CYCLIC(kr) to BLOCK-CYCLIC(r) array redistribution and vice versa. The main idea of the generalized processor mapping technique is first to develop mapping functions for computing a new rank of each destination processor. Based on the mapping functions, a new logical sequence of destination processors can be derived. The new logical processor sequence is then used to minimize the amount of data exchange in a redistribution. The generalized processor mapping technique can handle array redistribution with arbitrary source and destination processor sets and can be applied to multidimensional array redistribution. We present a theoretical model to analyze the performance improvement of the generalized processor mapping technique. To evaluate the performance of the proposed technique, we have implemented the generalized processor mapping technique on an IBM SP2 parallel machine. The experimental results show that the generalized processor mapping technique can provide performance improvement over a wide range of redistribution problems     

Hopfield在计算机编程中的应用与研究

Hopfield网络,又称联想记忆网络。文中根据Hopfleld神经网络构造一个应用于计算机代码编程中的联想存储器。联想记忆是该存储器的重要功能,它具有信息记忆和信息联想的特点,能够从不完整的或模糊的信息联想出存储在记忆中的某个完整清晰的信息模式。根据这一原理,用H0pfield联想存储器知识和eclipse插件机制来搭建嵌入在eclipse开发工具中一个知识可拓展的动态帮助插件,实现根据残缺不全的java代码联想到完整的java代码的功能,并进一步阐述Hopfield神经网络在计算机代码编程中的应用前景和发展方向。     

A concurrent architecture for serializable production systems

This paper presents a new production system architecture that takes advantage of modern associative memory devices to allow parallel production firing, concurrent matching, and overlap among matching, selection, and firing of productions. We prove that the results produced by the architecture are correct according to the serializability criterion. A comprehensive event driven simulator is used to evaluate the scaling properties of the new architecture and to compare it with a parallel architecture that does global synchronization before every production firing. We also present measures for the improvement in speed due to the use of associative memories and an estimate for the amount of associative memory needed. Architectural evaluation is facilitated by a new benchmark program that allows for changes in the number of productions, the size of the database, the variance between the sizes of local data clusters, and the ratio between local and global data. Our results indicate that substantial improvements in speed can be achieved with a very modest increase in hardware cost     

联想记忆与人工神经网络

联想记忆是人类记忆的基本方式,本文通过对人类联想记忆的本质及其规律的分析,讨论了如何用人工神经网络的模型来实现这种记忆形式,同时也指出了这种模拟的不足之处及需要解决的问题。     

联想记忆的一种随机理论*

本文提出研究联想记忆的一种随机理论，从数学上证明顺向联想记忆和逆向联想记忆的存在性，给出实现正确联想记忆的充要条件；对于相互干涉项为独立序列和与相关序列和两种情况均给出正确想起概率与网络容量的关系的解析表达式，与以往的工作相比，联想记忆理论通过一种概率途境得到进一步发展。     

Associative Gray Level Pattern Processing using Binary Decomposition and α β Memories

In this note we show how a binary memory can be used to recall gray-level patterns. We take as example the α β associative memories recently proposed in Yáñez, Associative Memories based on order Relations and Binary Operators(In Spanish), PhD Thesis, Center for computing Research, February of 2002, only useful in the binary case. Basically, the idea consists on that given a set of gray-level patterns to be first memorized: (1) Decompose them into their corresponding binary patterns, and (2) Build the corresponding binary associative memory (one memory for each binary layer) with each training pattern set (by layers). A given pattern or a distorted version of it, it is recalled in three steps: (1) Decomposition of the pattern by layers into its binary patterns, (2) Recalling of each one of its binary components, layer by layer also, and (3) Reconstruction of the pattern from the binary patterns already recalled in step 2. The proposed methodology operates at two phases: training and recalling. Conditions for perfect recall of a pattern either from the fundamental set or from a distorted version of one them are also given. Experiments where the efficiency of the proposal is tested are also given.     

A walsh-hadamard based distributed storage device for the associative search of information

A computer model for a distributed associative memory has been developed based on Walsh-Hadamard functions. In this memory device, the information storage is distributed over the entire memory medium and thereby lends itself to parallel comparison of the input with stored data. These inherent economic storage and parallel processing capabilities may be found effective especially in real-time processing of large amount of information. However, overlaying different pieces of data in the same memory medium creates the problem of interference or crosstalk between stored data and may lead to recognition errors. In this paper, a crosstalk reduction technique utilizing the gradient descent procedure is developed first. This minimizes the memory processing error and enhances memory saving. Second, for an efficient implementation of the memory structure, these associative memories are configured in a hierarchical structure which not only expands storage capacity but also utilizes the speed of tree search. Finally, a self-correcting technique is developed which achieves error-free recognition of near neighbors for any training pattern even among the presence of crosstalk.     

A new paradigm for real-time parallel storage and recognition of patterns based on a hierarchical organization of associative memories utilizing Walsh function encoding

A new hierarchical Walsh memory which can store and quickly recognize any number of patterns is proposed. A Walsh function based associative memory was found to be capable of storing and recognizing patterns in parallel via purely a software algorithmic technique (namely, without resorting to parallel hardware) while the memory itself only takes a single pattern space of computer memory, due to the Walsh encoding of each pattern. This type of distributed associative memory lends itself to high speed pattern recognition and has been reported earlier in a single memory version. In this paper, the single memory concept has first been extended to a parallel memory module and then to a tree-shaped hierarchy of these parallel modules that are capable of storing and recognizing any number of patterns for practical large scale data applications exemplified by image and speech recognition. The memory hierarchy was built by successively applying k-means clustering to the training data set. In the proposed architecture, the clustered data subsets are stored respectively into a parallel memory module where the module allocation is optimized using the genetic algorithm to realize a minimal implementation of the memory structure. The system can recognize all the training patterns with 100% accuracy and further, can also generalize on similar data. In order to demonstrate its efficacy with large scale real world data, we stored and recognized over 500 faces while at same time, achieving much reduced recognition time and storage space than template matching.     

尺度空间的联想记忆网络在灰度图中的应用

形态联想记忆网络具有十分优越的抗膨胀噪声或者腐蚀噪声的能力,但抗混合噪声的能力很弱,而在实际中,随机噪声往往是混合型的,既有膨胀噪声又有腐蚀噪声.将形态学尺度空间和形态联想记忆网络相结合,得到了一种新的联想记忆网络,它也具有优越的抗膨胀噪声或者腐蚀噪声的能力,同时它对随机噪声有一定的鲁棒性.通过对含有随机噪声的灰度图像进行自联想记忆和识别处理实验,取得了较为理想的结果,验证了其具有良好的性能.