Hole mobility enhancement in strained-Si p-MOSFETs under high vertical field

The growth of a high quality, step-graded lattice-relaxed SiGe buffer layer on a Si(100) substrate is investigated. p-MOSFETs were fabricated on strained-Si grown on top of the above layer. Carrier confinement at the type-II strained-Si/SiGe buffer interface is observed clearly from the device transconductance and C-V measurements. At high vertical field, compared to bulk silicon, the channel mobility of the strained-Si device with x=0.18 is found to be about 40% and 200% higher at 300 K and 77 K respectively. Measurements on transconductance enhancement are also reported. Data at 77 K provide evidence of two channels and a large enhancement of mobility at high transverse field.     

Fabrication of strained Si channel PMOSFET on thin relaxed Si1−xGex virtual substrate

A novel MBE-grown method using low-temperature Si technology is introduced into the fabrication of strained Si channel PMOSFETs. The thickness of relaxed Si_1−xGe_x epitaxy layer on bulk silicon is reduced to approximate 400 nm (x=0.2). The Ge fraction and relaxation of Si_1−xGe_x film are confirmed by DCXRD (double crystal X-ray diffraction) and the DC characteristics of strined Si channel PMOSFET measured by HP 4155B indicate that hole mobility μ_p has an maximum enhancement of 25% compared to similarly processed bulk Si PMOSFET.     

FABRICATION OF STRAINED-Si CHANNEL P-MOSFET’s ON ULTRA-THIN SiGe VIRTUAL SUBSTRATES

In the ultra-thin relaxed SiGe virtual substrates, a strained-Si channel p-type Metal Oxide Semiconductor Field Effect Transistor （p-MOSFET） is presented. Built on strained-Si/240nm relaxed-Si0.8 Ge0.2/ 100nm Low Temperature Si （LT-Si）/10nm S i buffer was grown by Molecular Beam Epitaxy （MBE）, in which LT-Si layer is used to release stress of the SiGe layer and made it relaxed. Measurement indicates that the strained-Si p-MOSFET＇s （L=4.2μm） transconductance and the hole mobility are enhanced 30% and 50% respectively, compared with that of conventional bulk-Si. The maximum hole mobility for strained-Si device is 140cm^2/Vs. The device performance is comparable to devices achieved on several μm thick composition graded buffers and relaxed-SiGe layer virtual substrates.     

Gas source molecular beam epitaxy grown strained-Si films on step-graded relaxed Si1−xGex for MOS applications

Gas source molecular beam epitaxy has been employed for the growth of a high quality strained-Si layer on a completely relaxed step-graded Si_1−xGe_x buffer layer. As-grown strained-Si layers have been characterized using secondary ion mass spectroscopy, Rutherford backscattering spectroscopy, atomic force microscopy, and spectroscopic ellipsometry for the determination of composition, thickness, crystalline quality, and surface roughness. Heterojunction conduction and valence band offsets (ΔE_c, ΔE_υ) of strained-Si/SiGe heterostructure have been determined from measured threshold voltages of a strained-Si channel p-metal oxide semiconductor field effect transistor (MOSFET) fabricated using grown films. MOS capacitance-voltage profiling has been employed for the extraction of strained-Si layer thickness and apparent doping profile in the device.     

Fabrication and analysis of deep submicron strained-Si n-MOSFET's

Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si_0.8Ge_0.2 heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 μm) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects     

Strain-controlled Si-Ge modulation-doped FET with ultrahigh holemobility

A novel modulation-doped field effect transistor (MODFET) with a strain-controlled Ge channel, p-Si_0.5Ge_0.5/Ge/Si _1-xGe_x, is fabricated by molecular beam epitaxy (MBE). In order to enlarge the valence-band discontinuity, strain at the p-Si_0.5Ge_0.5/Ge interface is controlled by changing the composition of the relaxed Si_1-xGe_x layer. For this MODFET operated at around 77 K, an ultrahigh-field-effect mobility of ~9000 cm²/V-s is obtained     

In-plane transport properties of Si/Si1-xGexstructure and its FET performance by computer simulation

Transport properties of ungated Si/Si_1-xGe_x are studied by an ensemble Monte Carlo technique. The device performance is studied with a quantum hydrodynamic equation method using the Monte Carlo results. The phonon-scattering limited mobility is enhanced over bulk Si, and is found to reach 23000 cm²/Vs at 77 K and 4000 cm²/Vs at 300 K. The saturation velocity is increased slightly compared with the bulk value at both temperatures. A significant velocity overshoot, several times larger than the saturation velocity, is also found. In a typical modulation-doped field-effect-transistor, the calculated transconductance for a 0.18 μm gate device is found to be 300 mS/mm at 300 K. Velocity overshoot in the strained Si channel is observed, and is an important contribution to the transconductance. The inclusion of the quantum correction increases the total current by as much as 15%     

Schottky diode characteristics of Ti on strained-Si

The Schottky barrier height and ideality factor of Ti on p-type strained-Si (grown on a graded relaxed Si_0.82Ge_0.18 buffer layer) were investigated in the temperature range 200–300 K using the current-voltage (I-V) characteristics and were found to be temperature dependent. While the ideality factor decreases with an increase in temperature, the barrier height increases.     

Electron mobility enhancement in strained-Si n-MOSFETs fabricatedon SiGe-on-insulator (SGOI) substrates

We demonstrate electron mobility enhancement in strained-Si n-MOSFETs fabricated on relaxed Si_1-xGe_x-on-insulator (SGOI) substrates with a high Ge content of 25%. The substrates were fabricated by wafer bonding and etch-back utilizing a 20% Ge layer as an etch stop. Epitaxial regrowth was used to produce the upper portion of the Si_0.75Ge_0.26 and the surface strained Si layer. Large-area strained-Si n-MOSFETs were fabricated on this SGOI substrate. The measured electron mobility shows significant enhancement over both the universal mobility and that of co-processed bulk-Si MOSFETs. This SGOI process has a low thermal budget and thus is compatible with a wide range of Ge contents in Si_1-xGe_x layer     

Design of Si/SiGe heterojunction complementarymetal-oxide-semiconductor transistors

An optimized Si/SiGe heterostructure for complementary metal-oxide semiconductor (CMOS) transistor operation is presented. Unlike previous proposals, the design is planar and avoids inversion of the Si layer at the oxide interface. The design consists of a relaxed Si_0.7Ge _0.3 buffer, a strained Si quantum well (the electron channel), and a strained S_1-xGe_x (0.7>x>0.5) quantum well (the hole channel). The channel charge distribution is predicted using a 1-D analytical model and quantum mechanical solutions. Transport is modeled using 2-D drift-diffusion and hydrodynamic numerical simulations. An almost symmetric performance of p- and n-transistors with good short-channel behavior is predicted. Simulated ring oscillators show a 4- to 6-fold reduction in power-delay product compared to bulk Si CMOS at the 0.2-μm channel length generation     

<100>沟道方向对高迁移率双轴应变硅p-MOSFET的作用

双轴应变技术被证实是一种能同时提高电子和空穴迁移率的颇有前景的方法;<100>沟道方向能有效地提升空穴迁移率.研究了在双轴应变和<100>沟道方向的共同作用下的空穴迁移率.双轴应变通过外延生长弛豫SiGe缓冲层来引入,其中,弛豫SiGe缓冲层作为外延底板,对淀积在其上的硅帽层形成拉伸应力.沟道方向的改变通过在版图上45°旋转器件来实现.这种旋转使得沟道方向在(001)表面硅片上从<110>晶向变成了<100>晶向.对比同是<110>沟道的应变硅pMOS和体硅pMOS,迁移率增益达到了130%;此外,在相同的应变硅pMOS中,沟道方向从<110>到(100)的改变使空穴迁移率最大值提升了30%.讨论和分析了这种双轴应变和沟道方向改变的共同作用下迁移率增强的机理.     

High-mobility ultrathin strained Ge MOSFETs on bulk and SOI with low band-to-band tunneling leakage: experiments

For the first time, the tradeoffs between higher mobility (smaller bandgap) channel and lower band-to-band tunneling (BTBT) leakage have been investigated. In particular, through detailed experiments and simulations, the transport and leakage in ultrathin (UT) strained germanium (Ge) MOSFETs on bulk and silicon-on-insulator (SOI) have been examined. In the case of strained Ge MOSFETs on bulk Si, the resulting optimal structure obtained was a UT low-defect 2-nm fully strained Ge epi channel on relaxed Si, with a 4-nm Si cap layer. The fabricated device shows very high mobility enhancements >3.5/spl times/ over bulk Si devices, 2/spl times/ mobility enhancement and >10/spl times/ BTBT reduction over 4-nm strained Ge, and surface channel 50% strained SiGe devices. Strained SiGe MOSFETs having UT (T/sub Ge/<3 nm) very high Ge fraction (/spl sim/ 80%) channel and Si cap (T/sub Si cap/<3 nm) have also been successfully fabricated on thin relaxed SOI substrates (T/sub SOI/=9 nm). The tradeoffs in obtaining a high-mobility (smaller bandgap) channel with low tunneling leakage on UT-SOI have been investigated in detail. The fabricated device shows very high mobility enhancements of >4/spl times/ over bulk Si devices, >2.5/spl times/ over strained silicon directly on insulator (SSDOI; strained to 20% relaxed SiGe) devices, and >1.5/spl times/ over 60% strained SiGe (on relaxed bulk Si) devices.     

DESIGN AND FABRICATION OF Si/SiGe PMOSFETs

Based on theoretical analysis and computer-aided simulation, optimized design prin-ciples for Si/SiGe PMOSFET are given in this paper, which include choice of gate materials, determination of germanium percentage and profile in SiGe channel, optimization of thickness of dioxide and silicon cap layer, and adjustment of threshold voltage.In the light of these principles, a SiGe PMOSFET is designed and fabricated successfully.Measurement indicates that the SiGe PMOSFET‘s(L=2μ同洒45 mS/mm(300K) and 92 mS/mm(77K) ,while that is 33mS/mm (300K) and 39mS/mm (77K) in Si PMOSFET with the same structure.     

Si/SiGe PMOS器件的模拟优化设计与样品研制

通过理论分析与计算机模拟,给出了以提高跨导为目标的Si/SiGe PMOSFET优化设计方法,包括栅材料的选择、沟道层中Ge组分及其分布曲线的确定、栅氧化层及Si盖帽层厚度的优化和阈值电压的调节,基于此已研制出Si/SiGe PMOSFET器件样品.测试结果表明,当沟道长度为2μm时,Si/SiGe PMOS器件的跨导为45mS/mm(300K)和92mS/mm(77K),而相同结构的全硅器件跨导则为33mS/mm(300K)和39mS/mm(77K).     

应变硅n-MOSFET中电子迁移率的增强及其温度特性

采用减压化学气相淀积(RPCVD)技术在弛豫Si_(1-x)Ge_x虚拟衬底上赝晶生长应变硅层,以其为沟道材料制造得到的应变硅n-MOSFET表现出显著的性能提升。研究了通过改变Si_(1-x)Ge_x中Ge的摩尔组分x以改变硅帽层中的应变以及在器件制造流程中通过控制热开销来避免应变硅层发生弛豫等关键问题。在室温下,相对于体硅器件,应变硅器件表现出约87%的低场电子有效迁移率增强,在相同的过驱动电压下,饱和漏端电流增强约72%。在293 K到353 K的温度范围内研究了反型层电子有效迁移率和饱和漏端电流随温度的变化,实验结果表明,当温度升高时应变硅材料的电子迁移率增强倍数保持稳定。     

薄虚拟SiGe衬底上的应变Si pMOSFETs

成功地试制出薄虚拟SiGe衬底上的应变Si pMOSFETs.利用分子束外延技术在100nm低温Si(LT-Si)缓冲层上生长的弛豫虚拟Si0.8Ge0.2衬底可减薄至240nm.低温Si缓冲层用于释放虚拟SiGe衬底的应力,使其应变弛豫.X射线双晶衍射和原子力显微镜测试表明:虚拟SiGe衬底的应变弛豫度为85%,表面平均粗糙度仅为1.02nm.在室温下,应变Si pMOSFETs的最大迁移率达到140cm2/(V·s).器件性能略优于采用几微米厚虚拟SiGe衬底的器件.     

AlGaN/GaN HEMTs on resistive Si(111) substrate grown by gas-sourceMBE

Al_0.3Ga_0.7N/GaN high electron mobility transistor (HEMT) structures have been grown on resistive Si(111) substrate by molecular beam epitaxy (MBE) using ammonia (NH₃). The use of an AlN/GaN intermediate layer allows a resistive buffer layer to be obtained. High sheet carrier density and high electron mobility arc obtained in the channel. A device with 0.5 μm gate length has been realised exhibiting a maximum extrinsic transconductance of 160 mS/mm and drain-source current exceeding 600 mA/mm. Small-signal measurements show f_t of 17 GHz and f_max of 40 GHz     

In0.52Al0.48As/InAs/InxAl1-xAs pseudomorphic HEMT's on InP

The DC and microwave performance of an InAs channel HEMT is reported. Room-temperature electron mobility as high as 20200 cm² /Vs is measured, with a high carrier concentration of 2.7×10 ¹² cm^-2. DC extrinsic transconductance of 714 mS/mm is measured and a unity-current-gain cut-off frequency of 50 GHz is obtained for a 1.1-μm gate length HEMT. The success of achieving superior Hall mobility and device performance is strongly dependent on the In_xAl_1-xAs buffer layer design that changes the lattice constant from lattice-matched In_0.52Al_0.48 As to In_0.75Al_0.25As. The multiple In_0.52Al_0.48As/InAs monolayer superlattices buffer achieves the best performance as compared to the step-graded In_x Al_1-xAs and the uniform In_0.76Al_0.25 As buffer     

Electron and hole mobility enhancement in strained-Si MOSFET's onSiGe-on-insulator substrates fabricated by SIMOX technology

We have newly developed strained-Si MOSFET's on a SiGe-on-insulator (strained-SOI) structure fabricated by separation-by-implanted-oxygen (SIMOX) technology. Their electron and hole mobility characteristics have been experimentally studied and compared to those of control SOI MOSFET's. Using an epitaxial regrowth technique of a strained-Si film on a relaxed-Si_0.9Ge_0.1 layer and the conventional SIMOX process, strained-Si (20 nm thickness) layer on fully relaxed-SiGe (340 nm thickness)-on-buried oxide (100 nm thickness) was formed, and n-and p-channel strained-Si MOSFET's were successfully fabricated. For the first time, the good FET characteristics were obtained in both n-and p-strained-SOI devices. It was found that both electron and hole mobilities in strained-SOI MOSFET's were enhanced, compared to those of control SOI MOSFET's and the universal mobility in Si inversion layer     

DC and RF performance of 0.25 μm p-type SiGe MODFET

The DC and RF performance of a 0.25 μm gate-length p-type SiGe modulation-doped field-effect transistor (MODFET) is reported. The hole channel consists of compressively strained Si_0.3Ge_0.7 layer grown on a relaxed Si_0.7Ge_0.3 buffer on a Si substrate. The combination of high-hole mobility, low-gate leakage current, and improved ohmic contact metallization results in an enhancement of the DC and RF performance. A maximum extrinsic transconductance (g(m_ext)) of 230 mS/mm was measured. A unity current gain cut-off frequency (fT) of 24 GHz and a maximum frequency of oscillation (f_max) of 37 GHz were obtained for these devices