Calibrating On-chip Thermal Sensors in Integrated Circuits: A Design-for-Calibration Approach

With the scaling of technology, thermal issues have started to adversely affect reliability, performance, and robustness of integrated circuits. As a result, many recent research papers have focused on the use of embedded thermal sensors to monitor the temperature profile within the IC and manage the on-chip resources to keep the temperatures within acceptable limits. However, due to increasing process variations and parameter drifts, temperature measurements by these thermal sensors may not be accurate unless these on-chip sensors are calibrated before shipping the devices to the users. Existing calibration methods are either time-consuming or assume that the sensors do not require calibration for they use very large area which makes them insensitive to variations and drifts. In this paper, we propose a design-for-calibration (DFC) approach for calibrating the embedded thermal sensors in the manufacturing environment. Simulation results demonstrate the effectiveness and accuracy of our approach. The impact of uncertainties in parameters on the accuracy of calibration is also investigated in the paper.     

Software Assisted Digital RF Processor (DRP™) for Single-Chip GSM Radio in 90 nm CMOS

This paper proposes and describes a new software and application programming interface view of an RF transceiver. It demonstrates benefits of using highly programmable digital control logic in an RF wireless system realized in a digital nanoscale CMOS process technology. It also describes a microprocessor architecture design in Digital RF Processor (DRP™) and how it controls calibration and compensation for process, temperature and voltage variations of the analog and RF circuits to meet the required RF performance. A few calibration examples to reduce a DCO bias current and improve device reliability, as well as to optimize transmit modulation and receive performance, are given. The presented circuits and techniques have enabled successful implementation of a commercial single-chip GSM radio in 90 nm CMOS.      

Analog VLSI Circuit Implementation of an Adaptive Neuromorphic Olfaction Chip

In this paper, we present the analog circuit design and implementation of the components of an adaptive neuromorphic olfaction chip. A chemical sensor array employing carbon black composite sensing materials with integrated signal processing circuitry forms the front end of the chip. The sensor signal processing circuitry includes a dc offset cancellation circuit to ameliorate loss of measurement range associated with chemical sensors. Drawing inspiration from biological olfactory systems, the analog circuits used to process signals from the on-chip odor sensors make use of temporal "spiking" signals to act as carriers of odor information. An on-chip spike time dependent learning circuit is integrated to dynamically adapt weights for odor detection and classification. All the component subsystems implemented on chip have been successfully tested in silicon     

A New Capacitance-to-Frequency Converter for On-Chip Capacitance Measurement and Calibration in CMOS Technology

In this paper, a new capacitance-to-frequency converter using a charge-based capacitance measurement (CBCM) circuit is proposed for on-chip capacitance measurement and calibration. As compared to conventional capacitor measurement circuits, the proposed technique is able to represent the capacitance in term of the frequency so that the variations can be easily handled in measurement or calibration circuits. Due to its simplicity, the proposed technique is able to achieve high accuracy and flexibility with small silicon area. Designed using standard 180 nm CMOS technology, the core circuit occupies less than 50 μm × 50 μm while consuming less than 60 μW at an input frequency of 10 MHz. Post-layout simulation shows that the circuit exhibits less than 3 % measurement errors for fF to pF capacitances while the functionality has been significantly improved.     

On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation

This work presents the design and the silicon implementation of an on-line energy optimizer unit based on novel analog computation approaches, which is capable of dynamically adjusting power supply voltages and operating frequencies of multiple processing elements on-chip. The optimized voltage/frequency assignments are tailored to the instantaneous workload information on multiple tasks and fully adaptive to variations in process and temperature. The optimizer unit has a response time of less than 50 mus, occupies a silicon area of 0.021 mm²/task and dissipates 2 mW/task.     

Generation of accurate on-chip time constants and stabletransconductances

A method for generating accurately known on-chip time constants and less accurate but stable transistor transconductances over process, power-supply, and temperature variations is presented. The technique uses a constant-g_m bias circuit, which has a resistor that is tuned with a fully integrated CMOS phase-locked loop (PLL) locked to an external frequency reference (normally present in most systems). Other on-chip analog circuits biased using the same constant-g_m bias circuit are also stabilized. The PLL uses a charge-pump structure with three control loops (two digital and one analog) having overlapping ranges with hysteresis to minimize tuning glitches in the steady state. The PLL has a lock range of 135 to 300 MHz, and displays an RMS jitter of 15.6 ps. The transconductances generated from the circuit display a 2.2% variation for a 60°C change in temperature, and a 1.3% variation for a 10% variation in power-supply voltage. The design has been fabricated in a 0.35-μm CMOS process, using an active area of 1200×1200 μm² and draws 5.8 mA from a 3.3-V supply     

Thermal coupling in integrated circuits: application to thermaltesting

The power dissipated by the devices of a circuit can be construed as a signature of the circuit's performance and state. Without disturbing the circuit operation, this power consumption can be monitored by temperature measurements of the silicon die surface via built-in differential temperature sensors. In this paper, dynamic and spatial thermal behavioral characterization of VLSI MOS devices is presented using laser thermoreflectance measurements and on-chip differential temperature sensing circuits. A discussion of the application of built-in differential temperature measurements as an IC test strategy is also presented     

CMOS image sensors: electronic camera-on-a-chip

CMOS active pixel sensors (APS) have performance competitive with charge-coupled device (CCD) technology, and offer advantages in on-chip functionality, system power reduction, cost, and miniaturization. This paper discusses the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed     

Integrated Temperature Sensors for On-Line Thermal Monitoring of Microelectronic Structures

Built-in temperature sensors increase the system reliability by predicting eventual faults caused by excessive chip temperatures. In this paper, simple and efficient built-in temperature sensors for the on-line thermal monitoring of microelectronics structures are introduced. The proposed temperature sensors produce a signal oscillating at a frequency proportional to the temperature of the microelectronics structure and therefore they are compatible to the oscillation-test method. The oscillation-test method is a low-cost and robust test method for mixed-signal integrated circuits based on transforming the circuit under test (CUT) to an oscillator. This paper presents the design and detailed characteristics of the sensors proposed based on the CMOS 1.2 µm technology parameters of Mitel S.C.C. Extensive post-layout simulations show that the oscillation frequency is very sensitive to temperature variations. The sensors proposed require very small power dissipation and silicon area.     

Design strategies and decoupling techniques for reducing theeffects of electrical interference in mixed-mode IC's

A key issue in the successful integration of analog circuits is a stable analog power supply. Traditional on-chip decoupling methods exhibit transients in the supply or voltage drops and power losses. This paper introduces the RLC decoupling method that features an enhanced transient response while being especially suited for low-power, low voltage applications. Both a theoretical and a practical approach are presented together with measurement results. As the benefits of a stable local power supply can be lost by the inadequate connection of two subcircuits with relative variations on the local grounds, a differential approach of signal transfer is proposed. Furthermore, the effect of a good local decoupling can be deteriorated by substrate noise, so some attention is given to this problem too     

Integrated Systems [systems on a chip]

Integrated Systems are defined as batch-fabricated interconnections of complex digital integrated circuits with analog interface circuits and transducers, such as sensors. By providing the cost, performance and reliability levels of monolithic integration, they offer potential advantages over multi-chip modules assembled with packaging technology. This paper studies the required process technology, as well as design, test and packaging issues, for integrating wide varieties of systems. The goal is to delineate the necessary steps in bringing Integrated Systems to market within a realistic period. With monolithic integration as the ultimate aim, a multi-chip entry point is identified that can start system technology on a learning curve of cost reduction using the same scaling principles that drive integrated circuits. Three challenges to be surmounted are identified in streamlining the I/O's and progressing along a learning curve, namely I/O scaling, I/O loading, and full-functional test. The “composite IC” is the entry point. A large chip, containing only global interconnects and power distribution, acts as a silicon backplane. Subsystem-chips, such as digital microprocessors or sensors, are flip-chip mounted using the accuracy of MEMS processing to fabricate “snap-together” physical and electrical interfaces with high reproducibility. While similar to conventional MCM's, this chip-to-chip connection has few compromises over on-chip connections. By keeping the fabrication responsibility within one organization, just as in monolithic chips, there is no need for incoming inspection. Added ESD protection and test-head loading are avoided on interior nodes by a new intra-factory method of testing     

Analog CMOS deterministic Boltzmann circuits

CMOS circuits implementing an analog neural network (ANN) with on-chip deterministic Boltzmann learning (DBL) and capacitive synaptic weight storage have been designed, fabricated, and tested. Weights are refreshed by periodic repetition of the training data. The circuits were used to build a 12-neuron, 132-synapse ANN that performed well in a variety of learning experiments, including a 36-input to 4-output mapping problem. Adaptive systems such as those described here can compensate for imperfections in the components from which they are constructed and therefore can be built using simple silicon area-efficient analog circuits. The test results indicate that deterministic Boltzmann ANNs can be implemented efficiently using analog CMOS circuitry     

CMOS带隙基准电压源的设计

许多模拟电路需要性能较好的带隙基准电压源,如ADC,DAC等.对工艺、电源电压、负载变化不敏感的带隙基准电压源在模拟电路中得到了广泛的应用.现详细分析并说明了设计这样的带隙基准电压源电路需要考虑的问题.     

基于模块电路结构的BP神经网络及其应用研究

本文采用一种简化的BP(Back Propagation)神经网络硬件模块实现方法。该方法利用全电流模式电路组成神经元模块,再用若干模块构成简化的BP神经网络。所提出的模块结构网络系统具有在线学习和在线权值存储能力,且可应用于实现编、解码和二维图像识别。文中提供了PSPICE和高级语言计算机仿真结果。     

A process for the combined fabrication of ion sensors and CMOScircuits

A novel process for the fabrication of ion-selective field-effect transistors (ISFETs) together with CMOS circuits on the same chip is reported. The process is based on a standard 2-μm, n-well, CMOS process, which is only modified starting at the metal interconnect step. The interconnect layer used is tungsten silicide. ISFETs are fabricated with floating polysilicon gates, which are exposed to photolithographic masking and HF etching before silicon nitride is deposited on the wafer. This layer of Si₃N₄ acts both as the pH-sensitive insulator for the ISFETs and as a protection layer for the on-chip circuitry buried beneath it. A source-follower circuit is described that provides an output voltage dependent on the threshold-voltage variations of the sensing transistor     

RF calibration of on-chip DfT chain by DC stimuli and statistical multivariate regression technique

The problem of parameter variability in RF and analog circuits is escalating with CMOS scaling. Consequently every RF chip produced in nano-meter CMOS technologies needs to be tested. On-chip Design for Testability (DfT) features, which are meant to reduce test time and cost also suffer from parameter variability. Therefore, RF calibration of all on-chip test structures is mandatory. In this paper, Artificial Neural Networks (ANN) are employed as a multivariate regression technique to architect a RF calibration scheme for DfT chain using DC- instead of RF (GHz) stimuli. The use of DC stimuli relaxes the package design and on-chip routing that results in test cost reduction. A DfT circuit (RF detector, Test-ADC, Test-DAC and multiplexers) designed in 65 nm CMOS is used to demonstrate the proposed calibration scheme. The simulation results show that the cumulative variation in a DfT circuit due to process and mismatch can be estimated and successfully calibrated, i.e. 25% error due to process variation in DfT circuit can be reduced to 2.5% provided the input test stimuli is large in magnitude. This reduction in error makes parametric tests feasible to classify the bad and good dies especially before expensive RF packaging.     

A low-voltage low-power threshold voltage monitor for CMOS process sensing

In this paper a low-voltage low-power threshold voltage monitor for CMOS process sensing is presented. This circuit works in weak inversion and it can be used as an elementary circuit block for on-chip compensation of the intra-die or inter-die threshold voltage variations in low-power analog and mixed-signal SoC, since it is robust to temperature and power supply voltage variations (similar to the bandgap voltage reference). The proposed threshold voltage monitor has been successfully verified in a standard 0.35-μm n-well CMOS TSMC process. Experimental results have confirmed that the circuit generates an average reference voltage of 758 mV (very close to the typical threshold voltage when extrapolated to absolute zero) for a 950 mV power supply voltage, with a variation of 39 ppm/°C for the −20 to 80°C temperature range.     

An Assessment of µ-Czochralski, Single-Grain Silicon Thin-Film Transistor Technology for Large-Area, Sensor and 3-D Electronic Integration

Single-grain (SG) thin-film transistors (TFTs) fabricated inside location-controlled silicon grains using the mu-Czochralski method are benchmarked for analog and RF applications. Each silicon grain is defined by excimer laser recrystallization of polysilicon. Thin-film transistors may be fabricated in this manner on silicon or low-cost flexible plastic substrates as processing temperatures remain below 350degC, making the SG-TFT a potential enabling technology for large-area highly integrated electronic systems or systems-in-package with low manufacturing cost. Operational amplifier and voltage reference circuits of varying complexity were designed and measured in order to evaluate the effects of channel position and processing variation on analog circuits. A two-stage telescopic cascode operational amplifier fabricated in an experimental 1.5 mum SG-TFT technology demonstrates a DC gain of 55 dB (unity-gain bandwidth of 6.3 MHz), while a prototype CMOS voltage reference with a power supply rejection ratio (PSRR) of 50 dB is also demonstrated. With f_T comparable to single-crystal MOSFETs of comparable gate length, the SG-TFT can also enable RF circuits for wireless applications. A 12 dB gain RF cascode amplifier with on-chip inductors and operating in the 433 MHz ISM band is demonstrated. Excellent agreement with simulations is attained using a modified BSIM-SOI model extracted from measurements of experimental SG-TFT devices.     

片上栅氧经时击穿失效监测电路与方法

 栅氧经时击穿(Time Dependent Dielectric Breakdown(TDDB))等失效机理引起的失效是电路失效的主要原因之一,而这些电路的失效可能会造成灾难性的后果.本文提出了一种片上、能对栅氧经时击穿引起的失效进行实时预报的电路及方法.当栅氧经时击穿引发电路或系统失效时,本监测电路会发出报警信号.本监测电路采用标准的CMOS工艺,只占用很小的芯片面积,同时它只与宿主电路共用电源信号,从而不会给宿主电路带来任何干扰.本监测电路采用0.18μm CMOS工艺实现了投片验证.     

An Activity-Triggered 95.3 dB DR $-$75.6 dB THD CMOS Imaging Sensor With Digital Calibration

Imaging sensors are being used as data acquisition systems in new biomedical applications. These applications require wide dynamic range (WDR), high linearity and high signal-to-noise ratio (SNR), which cannot be met simultaneously by existing CMOS imaging sensors. This paper introduces a new activity-triggered WDR CMOS imaging sensor with very low distortion. The new WDR pixel includes self-resetting circuits to partially quantize the photocurrent in the pixel. The pixel residual analog voltage is further quantized by a low-resolution column-wise ADC. The ADC code and the partially quantized pixel codes are processed by column-wise digital circuits to form WDR images. Calibration circuits are included in the pixel to improve the pixel linearity by a digital calibration method, which requires low calibration overhead. Current-mode difference circuits are included in the pixel to detect activities within the scene so that the imaging sensor captures high quality images only for scenes with intense activity. A proof-of-concept 32 times 32 imaging sensor is fabricated in a 0.35 mum CMOS process. The fill factor of the new pixel is 27%. Silicon measurements show that the new imaging sensor can achieve 95.3 dB dynamic range with low distortion of -75.6 dB after calibration. The maximum SNR of the sensor is 74.5 dB. The imaging sensor runs at frame rate up to 15 Hz.