共查询到15条相似文献,搜索用时 187 毫秒
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提出一种基于提升算法(lifting scheme)实现JPEG2000编码系统中的二维离散小波变换(Discrete Wavelet Transform)的并行阵列式的VLSI结构设计方法.该结构由一个行处理器和一个列处理器组成,行、列处理器通过时分复用同时进行滤波,用优化的移位加操作替代乘法操作,采用嵌入式数据延拓算法处理边界延拓.整个结构采用流水线设计方法,减少了运算量,提高了硬件资源利用率,该结构可应用于JPEG2000图像编码芯片中. 相似文献
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该文提出一种在JPEG2000算法中兼容5/3小波变换和9/7小波变换高效硬件定点实现技术。所提出的技术使用9/7提升小波变换的有界输入有界输出(Bounded Input Bounded Output, BIBO)增益来确定小波变换中间值的存储位深,使用5/3提升小波变换的BIBO增益来确定9/7提升小波变换中量化参数的选择方式和量化的实现方式,最终使用同一存储空间来存放定点5/3提升小波变换和定点9/7提升小波变换系数。该文提出的技术不仅大大节省了JPEG2000算法中小波实现模块中的硬件存储资源和算法计算量,而且也节省了后续基于上下文的位平面算术编码模块和率失真优化截取模块的存储资源和算法计算量。 相似文献
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提出一种基于提升算法实现JPEG2000编码系统中的二维离散小波变换(Discrete Wavelet Transform)的并行阵列式的VLSI结构设计方法.利用该方法所得结构由两个行处理器,一个列处理器以及少量行缓存组成;行列处理器内部是由并行阵列式的处理单元组成;能使行和列滤波器同时进行滤波,用优化的移位加操作替代乘法操作.整个结构采用流水线的设计方法处理,在保证同样的精度下,大大减少了运算量和提高了硬件资源利用率,几乎达到100%,加快了变换速度,也减少了电路的规模.该结构对于N×N大小的图像,处理速度达到O(N2/2)个时钟周期.二维离散小波滤波器结构已经过FPGA验证,并可作为单独的IP核应用于正在开发的JPEG2000图像编解码芯片中. 相似文献
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基于提升格式的离散小波变换比传统的基于卷积的运算量少,易于VLSI实现。本文提出了一种基于提升格式,高效实时实现JPEG2000中9/7双正交离散小波变换滤波器的VLSI结构设计方法。该方法所设计的结构,在保证同样的精度下,减少了运算量,整体运算速度高,硬件花费少,存储需求低,硬件利用率达到100%。本文用Verilog HDL对系统进行硬件描述,并选用Xilinx公司的XCV50e-cs144-8器件在ISE4.1环境下实现了综合。 相似文献
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在JPEG 2000中,无损图像压缩是采用整数5/3小波变换实现的.JPEG 2000也给出了5/3小波基于提升方法的算法.对提升方法的整数5/3小波变换算法进行了研究,针对二维的变换提出一种VLSI结构.该结构由4个模块构成,模块之间并行运行,模块内部采用流水线技术.对多级变换,级间的运算还可交叉,体现了提升方法的优势,较大地提高了硬件效率.其主要优点是消耗资源少且运算速度高,同时也适用于其他整数小波变换. 相似文献
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提出了一种应用于JPEG2000静态图像编码系统的二维离散小波变换(2D-DWT)单元的FPGA实现.分析了2D-DWT算法的特点,提出了一种直接进行二维小波变换的高速算法,克服了传统二维小波变换算法对存储器的频繁访问的缺点.同时,硬件结构具有较高的并行度和吞吐率;运用流水线技术,进一步提高了系统性能,每个时钟能输出4个小波系数.该结构对于N×N的图像,处理速度仅需要(N/2)2个时钟周期.设计经过FPGA验证,可用于实时图像压缩系统中. 相似文献
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HEVC静态图像压缩与JPEG2000性能比较与分析 总被引:1,自引:0,他引:1
基于离散小波变换DWT(Discrete Wavelet Transform)的JPEG 2000代表着静态图像的最高水平.HEVC(High Efficiency Video Coding)提出了一个静态图像压缩档次——Main Still Profile,其帧内编码模式采用多种新的算法实现.通过大量实验比较发现,基于HEVC静态图像压缩比JPEG 2000具有更高的压缩效率,将来有望取代JPEG 2000成为新的静态图像压缩标准. 相似文献
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A VLSI architecture of JPEG2000 encoder 总被引:1,自引:0,他引:1
Leibo Liu Ning Chen Hongying Meng Li Zhang Zhihua Wang Hongyi Chen 《Solid-State Circuits, IEEE Journal of》2004,39(11):2032-2040
This paper proposes a VLSI architecture of JPEG2000 encoder, which functionally consists of two parts: discrete wavelet transform (DWT) and embedded block coding with optimized truncation (EBCOT). For DWT, a spatial combinative lifting algorithm (SCLA)-based scheme with both 5/3 reversible and 9/7 irreversible filters is adopted to reduce 50% and 42% multiplication computations, respectively, compared with the conventional lifting-based implementation (LBI). For EBCOT, a dynamic memory control (DMC) strategy of Tier-1 encoding is adopted to reduce 60% scale of the on-chip wavelet coefficient storage and a subband parallel-processing method is employed to speed up the EBCOT context formation (CF) process; an architecture of Tier-2 encoding is presented to reduce the scale of on-chip bitstream buffering from full-tile size down to three-code-block size and considerably eliminate the iterations of the rate-distortion (RD) truncation. 相似文献
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Yang Guoan Zheng Nanning Guo Shugang 《电子科学学刊(英文版)》2007,24(2):276-284
A new approach for designing the Biorthogonal Wavelet Filter Bank (BWFB) for the purpose of image compression is presented in this letter. The approach is decomposed into two steps. First, an optimal filter bank is designed in theoretical sense based on Vaidyanathan's coding gain criterion in SubBand Coding (SBC) system. Then the above filter bank is optimized based on the criterion of Peak Signal-to-Noise Ratio (PSNR) in JPEG2000 image compression system, resulting in a BWFB in practical application sense. With the approach, a series of BWFB for a specific class of applications related to image compression, such as remote sensing images, can be fast designed. Here, new 5/3 BWFB and 9/7 BWFB are presented based on the above approach for the remote sensing image compression applications. Experiments show that the two filter banks are equally performed with respect to CDF 9/7 and LT 5/3 filter in JPEG2000 standard; at the same time, the coefficients and the lifting parameters of the lifting scheme are all rational, which bring the computational advantage, and the ease for VLSI implementation. 相似文献
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Hongying Meng Zhihua Wang 《Electronics letters》2000,36(21):1766-1767
A new fast spatial combinative lifting algorithm (SCLA) of the wavelet transform using the 9/7 filter for image block compression is proposed. In comparison with its lifting-based implementation, the number of multiplications is reduced by a ratio of 5/12 and the speed of implementation of the wavelet transform is increased 相似文献
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Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform 总被引:6,自引:0,他引:6
Chao-Tsung Huang Po-Chih Tseng Liang-Gee Chen 《Signal Processing, IEEE Transactions on》2004,52(4):1080-1089
In this paper, an efficient very large scale integration (VLSI) architecture, called flipping structure, is proposed for the lifting-based discrete wavelet transform. It can provide a variety of hardware implementations to improve and possibly minimize the critical path as well as the memory requirement of the lifting-based discrete wavelet transform by flipping conventional lifting structures. The precision issues are also analyzed. By case studies of the JPEG2000 default lossy (9,7) filter, an integer (9,7) filter, and the (6,10) filter, the efficiency of the proposed flipping structure is demonstrated. 相似文献