Microdisplay wafer‐flatness metrology by optical interferometry

Abstract— We report a microdisplay wafer‐flatness metrology technique based on digital high‐pass filtering of topography data obtained from a commercial optical interferometer. This technique discriminates against both wafer‐scale bow/warp and pixel‐scale roughness to reveal die‐scale flatness variations that are the most relevant to microdisplay gap uniformity. We report flatness measurements of a variety of live and test silicon wafers supporting VLSI microdisplay circuitry, and show how these measurements correlate with the performance of liquid‐crystal microdisplays assembled from similar wafers. The technique is sensitive to cross‐die flatness variations as small as 25 nm in the presence of wafer bow of tens of microns. The wafer flatness variations that make the greatest contribution to liquid‐crystal cell‐gap non‐uniformity arise from interactions between the chemical mechanical planarization (CMP) process and the VLSI circuit layout. Our metrology technique can help the VLSI designer optimize microdisplay layout, and provides an objective flatness specification for wafers purchased from third‐party foundries.     

An application of AHP and sensitivity analysis for selecting the best slicing machine

Wafer slicing is a complex manufacturing process, complicating efforts to monitor process stability and quality control effectively. This study discusses and develops a manufacturing quality yield model for forecasting 12 in. silicon wafer slicing based on the Analytic Hierarchy Process (AHP) framework. Decision Makers can select evaluation outcomes to identify the most precise machine. Additionally, EWMA control chart is presented to demonstrate and verify the feasibility and effectiveness of the proposed AHP-based algorithm. Finally, sensitivity analysis is performed to test the stability of the priority ranking. Therefore, this work illustrates how the AHP model would be implemented to help engineers determine the manufacturing process yield quickly and effectively.     

Defect-oriented testing and defective-part-level prediction

After an integrated circuit (IC) design is complete, but before first silicon arrives from the manufacturing facility, the design team prepares a set of test patterns to isolate defective parts. Applying this test pattern set to every manufactured part reduces the fraction of defective parts erroneously sold to customers as defect-free parts. This fraction is referred to as the defect level (DL). However, many IC manufacturers quote defective part level, which is obtained by multiplying the defect level by one million to give the number of defective parts per million. Ideally, we could accurately estimate the defective part level by analyzing the circuit structure, the applied test-pattern set, and the manufacturing yield. If the expected defective part level exceeded some specified value, then either the test pattern set or (in extreme cases) the design could be modified to achieve adequate quality. Although the IC industry widely accepts stuck-at fault detection as a key test-quality figure of merit, it is nevertheless necessary to detect other defect types seen in real manufacturing environments. A defective-part-level model combined with a method for choosing test patterns that use site observation can predict defect levels in submicron ICs more accurately than simple stuck-at fault analysis     

Design for manufacturing meets advanced process control: A survey

Nanometer IC designs are increasingly challenged to achieve manufacturing closure, i.e., being fabricated with high product yield due to feature miniaturizations and process variations. Realizing the critical importance of addressing manufacturability/yield during design (which is loosely termed as DFM, design for manufacturing), there has been a surge of research activities recently from both academia and industry under the “DFM” umbrella. While the primary goal of DFM is to enlarge the manufacturing process yield window, DFM needs to work together with advanced process control (APC) to meet such window, which may be shrinking and changing from design to design. The paper will survey the key DFM activities and discuss related advanced process control issues (i.e., the counterpart of manufacturing for design) to provide a holistic perspective on the design and process integration.     

微型应变传感器的设计与制造

把压敏电阻敏感元件、温度补偿电路和高电平放大器,在硅片上采用集成技术制成微型应变传感器,它有电压及频率两种形式的输出。给出了该传感器的设计、制造和测试结果。这种传感器也可以做压力传感器使用,不过在设计几何布局和制造处理上略有不同。     

多晶硅生产DCS控制系统专用功能模块的开发

本文介绍以设备集成化控制策略为依据开发的专用功能模块Transout_50,以实现对多晶硅生产DCS控制系统原料车间液氯储罐的出料控制。     

Full-IC manufacturability check based on dense silicon imaging

State of the art IC manufacturing process is witnessing the situation that the wave- length of stepper is more than twice the minimum feature size (193 nm wavelength vs. 90 nm/65 nm/45 nm feature size). According to the International Technology Roadmap for Semiconductors, this reality of “sub-wavelength lithography” will continue for the next several technology nodes. Optical Proximity Effect (OPE), as a technical terminol- ogy, usually refers to all of the undesired pattern vs. layout d…     

Set based robust design of mechanical systems using the quantifier constraint satisfaction algorithm

Embodiment design is an important phase of the design process where the initial design parameters and their feasible solution spaces with design configurations are decided for the design problem. This article presents a new approach of embodiment design space exploration of the product based on set based design with integration of robustness for the mechanical systems. The approach presented addresses the initial design phase of the mechanical systems design and provides a three step approach based on a formal expression syntax, transformation and evaluation engine and a computational algorithm for performing a domain search for sets of robust solutions for the product designs by taking into the account the variations and uncertainties related to the manufacturing process and material. The approach is based on the design domain exploration and reduction techniques. This is achieved by the utilization and integration of existential and universal quantifiers from the quantifier constraint satisfaction problem (QCSP) for the expression of the parameters and variables related to the product design and robustness. The quantifier notion has been used to develop the consistency check for the existence of a design solution and existence of a robust design solution. In order to compute the developed quantifier approach, an algorithm based on the transformation of the quantifier with interval arithmetic has also been developed. In order to demonstrate the capability of the developed approach, this article includes three examples of mechanical systems from earlier research works that apply the quantifier model and the resolution algorithm to successfully explore the design domain for robust solutions while taking into account different types of variations such as variations in mechanical/material properties, manufacturing variations or variations in geometric dimensions which may be of continuous or discrete type.     

LC4715抗辐射专用门阵列译码器

本文介绍了国产大规模抗辐射专用门阵译码电路的设计及研制过程，并给出部分设计参数和工艺参数及抗辐射指标。     

立式混合机温控系统分析与设计

按照大型立式混合机生产工艺与设备要求，介绍大型立式混合机在进行物料混合生产工艺时的温度自动控制系统的工作特点与设计方法，设计出了满足生产实际要求的结构简单性能优良的温度自动控制系统。     

Causal modelling of semiconductor fabrication

Semiconductor fabrication is the manufacturing process by which wafers of silicon are turned into integrated circuits. Reasoning about how wafers are affected by fabrication operations is an important aspect in getting computers to aid in the diagnosis of manufacturing faults and in the design of new fabrication processes. Our research has been aimed at characterizing the knowledge needed to construct qualitative, causal models that can support diagnosis and design of the processes by which semiconductors are manufactured. This article presents our models of wafer structure and the operations that are used in semiconductor fabrication, and describes how a domain-independent simulator uses these models to determine how the operations affect the wafer structure. We also demonstrate how the causal dependencies recorded by the simulator can be used to diagnose manufacturing faults. We conclude with a comparison of our method of using discrete, causal models to other methods of modelling semiconductor fabrication.     

Fabrication of relief-topographic surfaces with a one-step UV-lithographic process

This paper reports on a study of a methodology for fabrication of arbitrarily shaped silicon structures using technologies common to standard IC manufacturing processes. Particular emphasis is put on the design and use of halftone transmission masks for the lithography step required in the fabrication process of mechanical, optical or electronics components. The design and experimental investigation of gray-tone masks was supported by lithography simulation. Results are presented for both, simulated gray-tone patterns as well as experimental profiles.     

Design of a feature-based order acceptance and scheduling module in an ERP system

Customer-oriented manufacturing competes on timely responses to customer requirements, and precise scheduling control for delivery. This challenge demands engineering design and production planning to be fully integrated via advanced enterprise resource planning (ERP) systems. This paper proposes a generic feature association method and a detailed framework that can unify product and process models in order to satisfy customer orders with small batch sizes and high variations. A conceptual solution is introduced by integrating two traditionally separate feature domains: design configuration features and manufacturing process features. To achieve the proposed method, a customer feature class is suggested for the characterization of customers’ profiles related to the manufacturer. An instantiated customer feature object functionally tracks each customer’s selection of product configurations related to its requirements, specific orders, and production schedules with dynamic associations to the live manufacturing capacity. With the new associative integration method, a preliminary order acceptance system (OAS) prototype system has been implemented within an ERP order management system and its conceptual structure model is demonstrated within a multi-facet feature framework.     

Using Adaptive Circuits to Mitigate Process Variations in a Microprocessor Design

With each successive technology generation, process and environmental variations consume an increasingly large portion of the design envelope. To mitigate the impact of these variations, designs can incorporate adaptive techniques to reduce the impact. At the core of adaptability is the fundamental idea that each piece of silicon is different and will respond differently to stimuli. This poses a significant challenge in testing the product because testing relies on all parts behaving in a predictable manner every time they are tested. This article details adaptive techniques used on a dual-core, 90-nm Itanium microprocessor, and the issues and limitations encountered when testing this design.     

Robust scan-based logic test in VDSM technologies

The customer expects defect-free chips, at consumer prices, making thorough manufacturing test mandatory. With increasing chip density, the addition of say 10,000 gates is no longer of great impact (these would occupy only 0.1 mm² on a 0.18-μm die); satisfying timing requirements and not exceeding package or system power requirements are the principal implementation objectives. The new availability of silicon real estate has transformed the design-for-testability environment. Implementing contemporary application-specific integrated circuit (ASIC) designs based on standard-cell and gate array technologies now requires design flows that incorporate DFT. Robust design for testability in very deep-submicron (VDSM) technologies is essential to volume manufacturing. The most common structural test method is scan-based logic test, which is now the backbone of manufacturing test. Using this method, commercial ATPG tools rely on test-mode reconfiguration of the circuit to a pseudo-combinational one, ensuring its access, controllability, and observability. Each state bit is transformed into a stage (either a flip-flop or master-slave latch pair) of a shift register or scan chain accessible from chip pins. The author points out ways to avoid pitfalls in implementing effect scan-based test. These include modifying register-transfer-level circuit representations for testability, using a single clock edge design, and providing clock control     

M-TEST: A test chip for MEMS material property measurement usingelectrostatically actuated test structures

A set of electrostatically actuated microelectromechanical test structures is presented that meets the emerging need for microelectromechanical systems (MEMS) process monitoring and material property measurement at the wafer level during both process development and manufacturing. When implemented as a test chip or drop-in pattern for MEMS processes, M-Test becomes analogous to the electrical MOSFET test structures (often called E-Test) used for extraction of MOS device parameters. The principle of M-Test is the electrostatic pull-in of three sets of test structures [cantilever beams (CB's), fixed-fixed beams (FB's), and clamped circular diaphragms (CD's)] followed by the extraction of two intermediate quantities (the S and B parameters) that depend on the product of material properties and test structure geometry. The S and B parameters give a direct measure of the process uniformity across an individual wafer and process repeatability between wafers and lots. The extraction of material properties (e.g., Young's modulus, plate modulus, and residual stress) from these S and B parameters is then accomplished using geometric metrology data. Experimental demonstration of M-Test is presented using results from MIT's dielectrically isolated wafer-bonded silicon process. This yielded silicon plate modulus results which agreed with literature values to within ±4%. Guidelines for adapting the method to other MEMS process technologies are presented     

Low‐temperature amorphous‐silicon backplane technology development for flexible displays in a manufacturing pilot‐line environment

Abstract— A low‐temperature amorphous‐silicon (a‐Si:H) thin‐film‐transistor (TFT) backplane technology for high‐information‐content flexible displays has been developed. Backplanes were integrated with frontplane technologies to produce high‐performance active‐matrix reflective electrophoretic ink, reflective cholesteric liquid crystal and emissive OLED flexible‐display technology demonstrators (TDs). Backplanes up to 4 in. on the diagonal have been fabricated on a 6‐in. wafer‐scale pilot line. The critical steps in the evolution of backplane technology, from qualification of baseline low‐temperature (180°C) a‐Si:H process on the 6‐in. line with rigid substrates, to transferring the process to flexible plastic and flexible stainless‐steel substrates, to form factor scale‐up of the TFT arrays, and finally manufacturing scale‐up to a Gen 2 (370 × 470 mm) display‐scale pilot line, will be reviewed.     

Design, fabrication, and testing of silicon microgimbals forsuper-compact rigid disk drives

This paper documents results related to design optimization, fabrication process refinement, and micron-level static/dynamic testing of silicon micromachined microgimbals that have applications in super-compact computer disk drives as well as many other engineering applications of microstructures and microactuators requiring significant out-of-plane motions. The objective of the optimization effort is to increase the in-plane to out-of-plane stiffness ratio in order to maximize compliance and servo bandwidth and to increase the displacement to strain ratio to maximize the shock resistance of the microgimbals, while that of the process modification effort is to simplify in order to reduce manufacturing cost. The testing effort is to characterize both the static and dynamic performance using precision instrumentation in order to compare various prototype designs     

Process and terminations variations aware stability criteria for microwave amplifiers

Two novel process variations aware, necessary and sufficient conditions suitable for implementation in CAD optimizers are proposed to check amplifiers stability. Case studies are presented, showing that the new criteria allow robust amplifier design, under variation of active device immittance parameters in pre‐specified rectangular regions, due to manufacturing tolerances. © 2012 Wiley Periodicals, Inc. Int J RF and Microwave CAE 23: 619–626, 2013.     

A glance of technology efforts for design-for-manufacturing in nano-scale CMOS processes

This paper overviews design for manufacturing （DFM） for IC design in nano-CMOS technologies. Process/device issues relevant to the manufacturability of ICs in advanced CMOS technologies will be presented first before an exploration on process/device modeling for DFM is done. The discussion also covers a brief introduction of DFM-aware of design flow and EDA efforts to better handle the design-manufacturing interface in very large scale IC design environment.