Environment model adaptation for mobile robot exploration

In this work, we propose a methodology to adapt a mobile robot’s environment model during exploration as a means of decreasing the computational complexity associated with information metric evaluation and consequently increasing the speed at which the system is able to plan actions and travel through an unknown region given finite computational resources. Recent advances in exploration compute control actions by optimizing information-theoretic metrics on the robot’s map. These metrics are generally computationally expensive to evaluate, limiting the speed at which a robot is able to explore. To reduce computational cost, we propose keeping two representations of the environment: one full resolution representation for planning and collision checking, and another with a coarse resolution for rapidly evaluating the informativeness of planned actions. To generate the coarse representation, we employ the Principal of Relevant Information from rate distortion theory to compress a robot’s occupancy grid map. We then propose a method for selecting a coarse representation that sacrifices a minimal amount of information about expected future sensor measurements using the Information Bottleneck Method. We outline an adaptive strategy that changes the robot’s environment representation in response to its surroundings to maximize the computational efficiency of exploration. On computationally constrained systems, this reduction in complexity enables planning over longer predictive horizons, leading to faster navigation. We simulate and experimentally evaluate mutual information based exploration through cluttered indoor environments with exploration rates that adapt based on environment complexity leading to an order-of-magnitude increase in the maximum rate of exploration in contrast to non-adaptive techniques given the same finite computational resources.     

Test strategy for the PowerPC 750 microprocessor

Time-to-market goals are intricately entwined with the product testing strategy for a high-performance microprocessor. The result is an on-time product introduction coupled with improved, more effective and thorough testing     

PowerPC发展综述

本文对当今世界微处理器市场上主流产品之一的PowerPC作出历史回顾和基本介绍。分析了PowerPC在微处理器市场的地位 ,列举了近期有关PowerPC新技术新产品的重要事件。最后对PowerPC今后发展趋势作出了笔者的评论和预测     

PowerPC主机处理器的SDRAM接口设计开发

PowerPC主机处理器的外围电路比较复杂，给电路设计和开发带来了一定的困难。该文讨论了SDRAM接口的硬件设计，并通过实例讨论了VxWorks BSP的开发方法，给出了实验结果，文中对芯片组Tsi107的相关寄存器进行了详细说明。     

Superspeculative microarchitecture for beyond AD 2000

Based on their research at Carnegie Mellon University, the authors argue for billion-transistor uniprocessors. They divide the important implementation problems into three components: instruction flow, register dataflow, and memory dataflow. They also argue for trace caches and advanced branch prediction. Their article, however, focuses on using massive speculation at all levels to improve performance. They claim that without this much speculation, future processors will be limited by true data dependences, and will be unable to harvest enough instruction-level parallelism (ILP) to improve performance satisfactorily. Their investigations discovered large speedups on code that have traditionally not been amenable to finding ILP     

基于PowerPC处理器SMP系统的U-Boot移植

引导加载程序是计算机系统加电后运行的第一段程序代码,负责系统硬件的初始化和加载操作系统,它和系统硬件结构密切相关.本文针对一个基于PowerPC处理器的对称多处理系统平台,进行了U-Boot移植.并介绍了对称多处理系统的不同之处和移植方法.     

PowerPC 603, a microprocessor for portable computers

The PowerPC 603 incorporates a variety of features to reduce power dissipation: dynamic idle-time shutdown of separate execution units, low-power cache design, and power considerations for standard cells, data-path elements, and clocking. System-level features include three software-programmable static power management modes and a hardware-programmable phase-lock loop. Operating at 80 MHz, the 603 typically dissipates 2.2 W, while achieving an estimated 75 Specint92 and 85 Specfp92     

Itanium processor microarchitecture

The Itanium processor is the first implementation of the IA-64 instruction set architecture (ISA). The design team optimized the processor to meet a wide range of requirements: high performance on Internet servers and workstations, support for 64-bit addressing, reliability for mission-critical applications, full IA-32 instruction set compatibility in hardware, and scalability across a range of operating systems and platforms. The processor employs EPIC (explicitly parallel instruction computing) design concepts for a tighter coupling between hardware and software. In this design style the hardware-software interface lets the software exploit all available compilation time information and efficiently deliver this information to the hardware. It addresses several fundamental performance bottlenecks in modern computers, such as memory latency, memory address disambiguation, and control flow dependencies     

Validating PowerPC microprocessor custom memories

Due to the high cost of correcting errors in a final product, there is a growing impetus in industry towards methodologies that can yield correct designs in the first manufacturing run. Design validation methodologies that combine simulation techniques with formal reasoning can be effective in ensuring correct operation of software and hardware systems. We show why simulation is necessary to complement formal mathematical reasoning in verifying certain classes of custom designed circuits. We present a validation methodology for PowerPC custom memories based on symbolic simulation     

Evolution of the PowerPC architecture

The PowerPC is a new RISC architecture derived from IBM's POWER architecture. The changes made to POWER simplify implementations, increase clock rates, enable a higher degree of superscalar execution, extend the architecture to 64 bits, and add multiprocessor support. For compatibility with existing software, the developers retained POWER's basic instruction set, opcode assignments, and programming model     

基于共享内存的PowerPC系统BSP设计

板级支持包(BSP)介于主板硬件和操作系统之间,其功能与PC机上的BIOS相类似,主要完成硬件初始化并切换到相应的操作系统.因此它要求程序员不仅对软件而且对硬件和操作系统都要有一定的了解.该文介绍了基于共享内存的PowerPC系统BSP的程序设计,并已成功运行在PowerPC7447A处理器平台上.     

关于PowerPC处理器技术的研究综述

基于不同型号的PowerPC处理器,对PowerPC处理器的研究现状进行系统综述。针对目前工厂在PowerPC处理器技术方面的不足,为满足后续含PowerPC处理器的航电产品深修需要,从研究必要性、研究原则、功能分析以及研究方案几个方面,对基于MPC7410处理器系统板的研制进行系统诠释。     

PowerPC主机处理器的网口设计开发

设计了PowerPC主机处理器的网口，给出了硬件和VxWorks的BSP实现及调试方法。其中网口的设计是基于PCI总线，具有通用性。     

Itanium 2 processor microarchitecture

The Itanium 2 processor extends the processing power of the Itanium processor family with a capable and balanced microarchitecture. Executing up to six instructions at a time, it provides both performance and binary compatibility for Itanium-based applications and operating systems.     

多PowerPC 7400/7410处理器体系架构研究

PowerPC 7400/7410处理器是新一代的PowerPC G4处理器,带有高性能的AltiVec单元,其大小为128bits,该单元有利于处理高吞吐量的数据,因此可用来满足完成数字信号处理的要求,成为DSP的强有力替代品.该文通过对4个PowerPC处理器的3种并行体系架构分析和在雷达数字信号处理的性能比较下提出了改进参考模型,以供研究.     

AltiVec extension to PowerPC accelerates media processing

There is a clear trend in personal computing toward multimedia-rich applications. These applications will incorporate a wide variety of multimedia technologies, including audio and video compression, 2D image processing, 3D graphics, speech and handwriting recognition, media mining, and narrow/broadband signal processing for communication. In response to this demand, major microprocessor vendors have announced architectural extensions to their general-purpose processors in an effort to improve their multimedia performance. Intel extended IA-32 with MMX and SSE (alias KNI), Sun enhanced Sparc with VIS, Hewlett-Packard added MAX to its PA-RISC architecture, Silicon Graphics extended the MIPS architecture with MDMX, and Digital (now Compaq) added MVI to Alpha. This article describes the most recent, and what we believe to be the most comprehensive, addition to this list: PowerPC's AltiVec, AltiVec speeds not only media processing but also nearly any application in which data parallelism exists, as demonstrated by a cycle-accurate simulation of Motorola's MPC 7400, the heart of Apple G4 systems