High injection effects on noise characteristics of Si BJTs and SiGe HBTs

We present a physically based comparison of the current spectral densities in a SiGe heterojunction bipolar transistors (HBT) and a Si bipolar junction transistor (BJT) of identical geometry and doping levels, based on the direct evaluation of emitter, base and collector current fluctuations. An ensemble Monte Carlo (EMC) simulator self-consistently coupled with a 2D Poisson solver has been employed for the calculations. In the studied bias range, the largest reduction of the RF current noise values in the HBT as compared with the BJT derives from the spectral density of base current fluctuations, S_JB, and from the spectra of the cross-correlation between emitter and base current fluctuations, S_JBJE. This is due to the fact that the base current in the HBT is strongly reduced as a consequence of the lower gap of the SiGe base. At low injection, the collector spectral density S_JC exhibits a typical shot noise response while S_JB is governed by thermal noise. At high injection, the presence of hot carriers in the base–collector junction (which are less important in the HBT than in the BJT due to the SiGe/Si hetero-interface), the high carrier concentration in the base and the base push-out provokes the deviation of S_JC from the pure shot behavior. Under these conditions, the S_JB term can be neglected in the total noise analysis of the HBT for lower values of J_C, than in the BJT due to the Ge content benefits.     

Reliability and performance scaling of very high speed SiGe HBTs

We discuss the SiGe HBT structural changes required for very high performance. The increase in collector concentration, affecting current density and avalanche current, appears to be the most fundamental concern for reliability. In device design, a narrow emitter and reduced poly–single-crystal interfacial oxide are important elements in minimizing device parameter shifts. From the application point of view, avalanche hot-carriers appear to present new constraints, which may be managed through limiting voltage (to 1.5×–2× BV_CEO), or through circuit designs robust to base current parameter shifts.     

Applications and processing of SiGe and SiGe:C for high-speed HBT devices

The continued growth of high-speed-digital data transmission and wireless communications technology has motivated increased integration levels for ICs serving these markets. Further, the increasing use of portable wireless communications tools requiring long battery lifetimes necessitates low power consumption by the semiconductor devices within these tools. The SiGe and SiGe:C materials systems provide solutions to both of these market needs in that they are fully monolithically integratible with Si BiCMOS technology. Also, the use of SiGe or SiGe:C HBTs for the high-frequency bipolar elements in the BiCMOS circuits results in greatly decreased power consumption when compared to Si BJT devices.Either a DFT (graded Ge content across the base) or a true HBT (constant Ge content across the base) bipolar transistor can be fabricated using SiGe or SiGe:C. Historically, the graded profile has been favored in the industry since the average Ge content in the pseudomorphic base is less than that of a true HBT and, therefore, the DFT is tolerant of higher thermal budget processing after deposition of the base. The inclusion of small amounts of C (e.g. <0.5%) in SiGe is effective in suppressing the diffusion of B such that very narrow extremely heavily doped base regions can be built. Thus the f_T and f_max of a SiGe:C HBT/DFT are capable of being much higher than that of a SiGe HBT/DFT.The growth of the base region can be accomplished by either nonselective mixed deposition or by selective epitaxy. The nonselective process has the advantage of reduced complexity, higher deposition rate and, therefore, higher productivity than the selective epitaxy process. The selective epi process, however, requires fewer changes to an existing fabrication sequence in order to accommodate SiGe or SiGe:C HBT/DFT devices into the BiCMOS circuit.     

TCAD modeling of NPN-SI-BJT electrical performance improvement through SiGe extrinsic stress layer

The impact of introducing a SiGe stress layer formed over the extrinsic base and adjacent to the intrinsic base of NPN-Si-BJT device on the electrical properties and frequency response has been studied using TCAD modeling. Approximately 42% improvement in f_t and 13% improvement in f_max have been achieved for the strained NPN-Si-BJT device in comparison with an equivalent standard conventional BJT device. In addition to that, an enhancement of the collector current by almost three times has been achieved. The same approach has been applied for NPN-SiGe-HBT device to clarify the impact of the extrinsic SiGe stress on the device's performance using TCAD modeling. Simulation results have shown that applying the SiGe stress layer on the base region of the HBT device is less efficient in comparison with the BJT device, as the SiGe base is already stressed due to the existence of Ge at the base. Approximately 5% improvement in f_max and 3% improvement in f_t have been achieved for the strained HBT device in comparison with an equivalent standard conventional HBT device.     

Extraction of small-signal equivalent circuit model parameters for Si/SiGe HBT using S-parameters measurements and one geometrical information

A physical and simple method is proposed to extract the hybrid-π small-signal equivalent circuit model of Si/SiGe heterojunction bipolar transistor (HBT). In this method, we use test (dummy) structures to extract by means of fitting techniques the extrinsic bias-independent parameters representing the contact pads plus the transmission line connections to the core of the active device. All intrinsic bias-dependent parameters are calculated analytically from S-parameters only. The ratio of the area of the emitter contact to base area is used to solve the base–collector feedback problem due to the distributed nature of the base. Using this physical (geometry) constraint instead of the measured direct current (DC) information helps to get more reliable parameters and easier calculations. When we applied this methodology, a good agreement is obtained between the modelled S-parameters with the corresponding measured ones over the broad band from 40 MHz to 20.02 GHz. The error for three different bias points was less than 1.2%.     

Characteristics degradation of the SiGe HBT under electromagnetic field stress

This paper describes a new reliability study in SiGe Heterojunction Bipolar Transistors (HBTs) by which the electromagnetic field aggression effects can be identified. Base current deviation mechanism with current gain degradation is studied for the first time. Reverse Gummel plots and capacitance characterizations indicate that the electromagnetic field stress induces traps not only at the emitter–base spacer’s oxide, but also at the collector–base spacer’s oxide. These traps induce generation/recombination centers, and leads to excess non-ideal base currents. Two-dimensional physical simulations have been used to analyse the impact of this degradation mechanism on the device behavior. As a consequence of introducing surface recombination centers at emitter–base and collector–base spacer’s oxide, a non-ideal base current rises up in agreement with the experimental data extracted. As the density of interface traps increases, the charge contributed by these interface states causes a broadening in the base current response and the capacitances deviation.     

Reliability investigation of InGaP/GaAs HBTs under current and temperature stress

The reliability of InGaP/GaAs N–p–n heterojunction bipolar transistors (HBTs) with different base metal contact systems (Au/Zn/Au, Ti/Au, Ti/Pt/Au and the novel Ti/ZrB₂/Au) under current and temperature stress is studied in this paper. We further report results of current stress on three p-GaAs doping impurities namely Zn, Be and C. The effect of O⁺/H⁺ and O⁺/He⁺ ions, used in the fabrication of planar self-aligned HBTs, is also investigated in the stability of device dc current gain. The instability phenomena typical of each factors and their effects on the HBT characteristics are reported.     

Generation–recombination noise in bipolar transistors

The generation–recombination (g–r) noise in bipolar junction transistors (BJTs) is due to the deep-level impurities in the p–n junctions. The larger the amplitude of g–r noise, the worse the quality of BJTs, so that measuring the amplitude of the g–r noise is way of estimating the reliability of BJTs. In some papers, it is assumed that the amplitude of g–r noise is proportional to the square of base current (I_b²), but in a few papers it has been reported that this relation is more complex. In this paper the amplitude of g–r noise versus base current is discussed, the theoretical and experiment results demonstrate that the g–r noise and burst noise signal may be observed only in a certain range of base current, and the law S(f)∝I_b² is not valid. It means that we must measure g–r noise and observe burst noise signal over a wide range of base current to estimate the concentration of deep-level impurities in p–n junction and hence the reliability of BJTs.     

<Emphasis Type="Italic">f</Emphasis><Subscript>T</Subscript> × <Emphasis Type="Italic">BV</Emphasis><Subscript>cbo</Subscript> product modeling for SiGe:C HBTs

The specific aspects of SiGe:C HBT process and device simulation using TCAD are discussed. Cut-off frequency f _T and collector junction breakdown voltage BV _cbo dependences on carbon concentration in SiGe base area are investigated. The boron and carbon profiles in SiGe base are obtained to provide a trade-off between gain, cut-off frequency and break-down voltage. High values of f _T × BV _cbo product were achieved.     

Investigation of deep traps in silicon–germanium epitaxial base bipolar transistors with a single polysilicon quasi self-aligned architecture

The electrical properties of Si/Si_1−xGe_x bipolar transistors have been analysed at temperatures ranging from 77 to 500 K. The investigated SiGe base transistors were fabricated using a BiCMOS single-polysilicon quasi self-aligned process, where base implant had been replaced by selective epitaxy on the base active area. At low temperature, static current–voltage measurements show a degradation of base current ideality, whereas collector current remains ideal over the whole temperature range. By studying forward and reverse currents at emitter–base and base–collector junctions, we have established that deep levels were involved in conduction phenomena at these junctions. Detailed measurements using capacitance transient spectroscopy (with different reverse and filling pulse voltages and different filling pulse durations) have revealed the presence of two deep levels along the periphery of the emitter. These deep levels have been found with identical characteristics at both junctions. It is demonstrated that these traps are most probably induced by the extrinsic base implantation.     

Evaluation of SiGe:C HBT intrinsic reliability using conventional and step stress methodologies

The reliability of SiGe:C HBT devices fabricated using the Freescale’s 0.35-μm RF-BICMOS process was evaluated using both conventional and step stress methodologies. This device technology was assessed to determine its capability for various power amplifier applications (e.g., WLAN, Bluetooth, and cellular phone), which are more demanding than conventional circuit designs. The step stress method was developed to allow a rapid evaluation of product reliability, as well as, a quick method to monitor product reliability. For all tests the collector current I_C and collector voltage V_C were kept constant throughout the test, and the current gain β (I_C/I_B) was continuously monitored. The nominal bias condition was V_C = 3.5-V and J_C = 50-kA/cm² (or 0.5-mA/μm²). The “failure criterion” for all reliability evaluations was −10% degradation in β from the initial value at the start of each stress test or interval. The median time to failure (MTTF) at a junction temperature (T_JCN) of 150 °C for the conventional stress test was 1.86E6-h, and the thermal activation energy was 1.33-eV. In contrast for the temperature step stress tests the combined results gave an MTTF at T_JCN = 150 °C of 5.2E6-h and a thermal activation energy of 1.44-eV. Considering the differences in the two test methods, these results are quite close to one another. The intrinsic reliability of this device at the nominal bias condition and T_JCN = 150 °C is more than adequate for a 5-year system life.     

Experimental study of bias dependence of pulsed laser-induced single-event transient in SiGe HBT

This work presents a comprehensive investigation of single-event transient (SET) in SiGe HBT induced by pulsed laser irradiation at different bias conditions. The impacts of collector voltage V_CC and base voltage V_B on SET are compared and discussed. Experimental results show that SET in SiGe HBT highly depends on the applied bias conditions during irradiation. The underlying physical mechanisms are analyzed in detail. It is found that the variation of collector transient current approximately satisfies an ideal exponential discharge law. The additional discharge path plays a significant role in collector charge collection and discharge time constant once the transistors arrive at the reverse-active mode.     

Recombination in the Ge-spiked monoemitter of the SiGe:C HBTs

A SiGe spike in the monoemitter of a SiGe:C HBT locally increases the recombination rate. The narrower energy bandgap of SiGe compared to Si increases the minority charge storage, resulting in higher recombination rate. The SiGe spike acts as a virtual contact and increases the base current. This results in lower current gain, and hence higher BV_CEO. This paper studies the physical mechanism for this higher recombination rate in the SiGe spike, and it calculates the minority carrier lifetime in the SiGe spike.     

Study of hot-carrier effects on power RF LDMOS device reliability

This paper reports comparative reliability of the hot carrier induced electrical performance degradation in power RF LDMOS transistors after RF life-tests and novel methods for accelerated ageing tests under various conditions (electrical and/or thermal stress): thermal shock tests (TST, air–air test) and thermal cycling tests (TCT, air–air test) under various conditions (with and without DC bias, TST cold and hot, different channel current I_DS and different extremes temperatures ΔT values). It is important to understand the effects of the reliability degradation mechanisms on the S-parameters and in turn on static and dynamic parameters. The analysis of the experimental results is presented and the physical processes responsible for the observed degradation at different stress conditions are studied by means of 2D ATLAS-SILVACO simulations. The RF performance degradation of hot-carrier effects power RF LDMOS transistors can be explained by the transconductance and miller capacitance shifts, which are resulted from the interface state generation and trapped electrons, thereafter results in a build up of negative charge at Si/SiO₂ interface.     

SiGe HBT低噪声放大器的设计与制造

该文设计和制作了一款单片集成硅锗异质结双极晶体管(SiGe HBT)低噪声放大器(LNA)。由于放大器采用复合型电阻负反馈结构,所以可灵活调整不同反馈电阻,同时获得合适的偏置、良好的端口匹配和低的噪声系数。基于0.35 m Si CMOS平面工艺制定了放大器单芯片集成的工艺流程。为了进一步降低放大器的噪声系数,在制作放大器中SiGe器件时,采用钛硅合金(TiSi2)来减小晶体管基极电阻。由于没有使用占片面积大的螺旋电感,最终研制出的SiGe HBT LNA芯片面积仅为0.282 mm2。测试结果表明,在工作频带0.2-1.2 GHz内,LNA噪声系数低至2.5 dB,增益高达26.7 dB,输入输出端口反射系数分别小于-7.4 dB和-10 dB。     

SiGe/SiHBT异质界面与pn结界面的相对位移的影响

从模拟和实验两方面研究了SiGe/Si HBT发射结中pn结界面和SiGe/Si界面的相对位置对器件的电流增益和频率特性的影响.发现两界面偏离时器件性能会变差.尤其是当pn结位于SiGe/Si界面之前仅几十?就足以产生相当高的电子寄生势垒,严重恶化器件的性能.据此分析了基区B杂质的偏析和外扩对器件的影响以及SiGe/Si隔离层的作用.     

Reliability issues in III–V compound semiconductor devices: optical devices and GaAs-based HBTs

This paper reviews the current status of reliability issues in III–V optical devices, semiconductor lasers and light emitting diodes, and GaAs-based heterojunction bipolar transistors (HBTs). First, material issues in III–V alloy semiconductors and our current understanding of degradation in III–V semiconductor lasers and light emitting diodes are systematically presented. Generation of defects and thermal instability are among these issues for these systems. Defects introduced during crystal growth are classified into two types: interface defects and bulk defects. Defects belonging to the former type are stacking faults, V-shaped dislocations, dislocation clusters, microtwins, inclusions, and misfit dislocations, and the latter group includes precipitates and dislocation loops. Defects in the substrate can also be propagated into the epi-layer. Structural imperfections due to thermal instability are also found. They are quasi-periodic modulated structures due to spinodal decomposition of the crystal either at the liquid–solid interface or growth surface, and atomic ordering which also occurs on the growth surface through migration and reconstruction of the deposited atoms. Three major degradation modes of optical devices, rapid degradation, gradual degradation, and catastrophic failure, are discussed. For rapid degradation, recombination-enhanced dislocation climb and glide are responsible for degradation. Differences in the ease with which these phenomena occur in different heterostructures are presented. Based on the results, dominant parameters involved in the phenomena are discussed. Gradual degradation takes place presumably due to recombination enhanced point defect reaction in GaAlAs/GaAs-based optical devices. This mode is also enhanced by the internal stress due to lattice mismatch. However, we do not observe this mode in InGaAsP/InP-based optical devices. Catastrophic failure is found to be due to catastrophic optical damage at a mirror or at a defect in GaAlAs/GaAs double-heterostructure (DH) lasers, but not in InGaAsP/InP DH lasers. In each degradation mode, the role of defects in the degradation and methods of elimination of degradation are discussed. Secondly, we review the current status of two major reliability issues in GaAs-based HBTs, particularly InGaP/GaAs HBTs: degradation in current gain (β) and variation of turn-on voltage (V_be). In the case of AlGaAs/GaAs HBTs, the β gradually decreased, then drastically degraded. After degradation, the device exhibits an increase in base current I_b, which has an ideality factor n≈2 in the Gummel plot. The activation energy for the degradation was estimated to be 0.6 ± 0.1 eV. On the other hand, in InGaP/GaAs HBTs, much higher reliability than in AlGaAs/GaAs HBTs was achieved although the degradation mode is similar. The estimated E_a and time to failure for InGaP/GaAs HBTs are 2.0 ± 0.2 eV and 10⁶ h at T_j = 200°C, respectively, which are the highest values ever reported. We also review previously proposed degradation mechanisms for GaAs-based HBTs: hydrogen reactivation, microtwin-like defect formation, dark defect formation and carbon precipitation. TEM observation of a degraded InGaP/GaAs HBT indicated that there are at least two possible degradation mechanisms: formation of carbon precipitates in the base region and migration of metallic impurities from the base electrode to the base region. The second issue is concerned with the exponential increase in V_be with operating time. The mechanism for the increase in V_be has been clarified based on reactivation of passivated carbon acceptors in the base region during operation. If the device suffers from H⁺ isolation, V_be rapidly decreases at the initial stage, then exponentially increases. The first stage of V_be variation can be explained by the fact that a high density of hydrogen atoms migrating from the isolation region to the intrinsic base region, passivate the carbon atoms at the initial stage. From these results, one can expect that the use of He⁺ as an implant instead of H⁺ can solve this problem.     

SiGe-HBT中雪崩击穿效应对电流电压特性的影响

本文报道了一个在较宽温度范围内能精确描述6H SiC JEFT性能(包括亚阈区)的器件模型，器件的电流电压特性由包含少数几个物理模型参数连续统一的解析表达式表述.该模型也包括了串联电阻效应、沟道中电子速度饱和效应、饱和区的有限输出电导、温度决定的模型参数等效应.载流子的计算考虑了SiC中杂质能级特点，采用两级电离模型，模拟了典型结构器件的高温特性，结果和实验符合很好.     

0.1 - 110 GHz在片去嵌技术

研究了0.1 - 110 GHz S参数在片去嵌技术,给出了输入、输出端口非对称下的直通-反射-传输线（TRL）和传输线-反射-匹配（LRM）的去嵌算法求解结果。在 InP衬底上设计了TRL和LRM去嵌标准件,采用两种无源元件验证了去嵌结果的正确性,并且对TRL和LRM在0.1-110 GHz范围内的去嵌准确性进行对比。通过在0.1 - 40 GHz运用 LRM方法,和在75 - 110 GHz运用TRL方法,获得了有源器件HBT两频带内的本征S参数,并对去嵌前和去嵌后提取的小信号电流增益及单向功率增益进行对比。通过插值,可得出待测件0.1 - 110 GHz完整的S参数。     

A new empirical extrapolation method for time-dependent dielectric breakdown reliability projections of thin SiO2 and nitride–oxide dielectrics

The results of an investigation of time-dependent dielectric breakdown (TDDB) of thin gate oxide and nitride–oxide (N–O) films are presented for a wide range of fields and temperatures. It was found that TDDB of both gate oxide and N–O films followed a power-law dependence of mean value of average leakage current (I_avg). An empirical extrapolation model using average leakage current as a major parameter was proposed based on experimental results. This proposed lifetime model has been successful to predict dielectric reliability. It could continuously fit the entire breakdown data from both wafer level and module level stress. The extrapolation from wafer level data to module data was excellent. The power of current versus TDDB showed exponential dependence on oxide thickness. This proposed TDDB projection methodology also worked for N–O films with an abrupt current increase in the I–V curve at a certain voltage well below the breakdown voltage, while the conventional models clearly failed to fit all data from this region. The observation of TDDB dependence of the current may open a new window for oxide lifetime projections and provide some insights into the nature of oxide breakdown and its implications for reliability studies.