A new approach to sizing analog CMOS building blocks using pre-compiled neural network models

There has been a constant endeavor towards improving the available circuit design automation tools to match technological advancements in the electronic industry. However, inadequate research efforts in the analog domain are holding back the exploitation of advanced technologies. A dearth of design expertise in the analog domain is the principal driving force for the growth of Design Automation (DA) tools. Transistor sizing is one of the most crucial steps in the analog IC design. In this paper, we put forward a new computer aided design framework for the sizing of transistors in MOS Integrated Circuit (IC) amplifiers by incorporating powerful modeling capabilities of Artificial Neural Networks (ANN). ANNs have proven to be efficient and accurate modeling tools in several applications. The proposed tool is capable of directly computing transistor related design parameters, of the MOS IC amplifier and associated peripheral circuitry. The proposed tool thus avoids several time-consuming simulations and/or tuning runs at the very bottom level of analog IC amplifier implementation, using a given CMOS process. It also reduces manual intervention in the design process, thus enhancing the automation of the design process. This paper presents design examples of several analog IC functional modules that are developed and verified successfully.     

基于神经网络与证据理论的模拟电路故障诊断

论述了利用多类电量测试信息、应用神经网络与D-S证据理论实现模拟电路故障诊断的基本原理,提出了一种基于可测点电压与不同测试频率下的电路增益经决策层信息融合的故障诊断新方法.分别利用此两类测试信息,各用一个独立的改进BP网络对电路进行初步诊断,再运用所提融合诊断算法实现故障定位.模拟实验结果表明:所提方法对硬故障与元件参数偏移较小的软故障均适用,故障定位准确率高.     

A programmable analog neural network chip

A generic chip is implemented in CMOS to facilitate studying networks by building them in analog VLSI. By utilizing the well-known properties of charge storage and charge injection in a novel way, the authors have achieved a high enough level of complexity (>10³ weights and 10 bits of analog depth) to be interesting, in spite of the limitation of a modest 6.00×3.5-mm² die size required by a multiproject fabrication run. If the cell were optimized to represent fixed-weight networks by eliminating weight decay and bidirectional weight changes, the density could easily be increased by a factor of 2 with no loss in resolution. Once a weight change vector has been written to the RAM cells, charge transfers can be clocked at a rate of 2 MHz, corresponding to peak learning rates of 2×10⁹ weight changes/second and exceeding the throughput of `neural network accelerators' by two orders of magnitude     

基于神经网络信息融合技术的模拟电路故障诊断

研究了神经网络信息融合技术在模拟电路故障诊断中的应用。利用BP神经网络建立信息融合中心,对多传感器数据进行融合处理,减少模拟电路故障诊断的不确定性。对标准电路的输出电压与电源电流特征信息,及两者融合信息的故障诊断性能比较,表明神经网络信息融合方法用于模拟电路故障诊断是有效和可行的。     

Basic circuits for multi-valued sequential logic

Multi-valued logic circuits were presented as an alternative to well known binary logic. It has the potential of reducing the number of active elements and interconnection lines. More data may be transferred trough a single wire using logic signals having more than two levels. However, in spite of their potential advantages, developments in multi-valued systems are not satisfactory. In particular, it is very difficult to find circuits to implement the multilevel sequential circuits. The flip-flop is the basic building block of sequential circuits and may be used to design sequential circuits such as counter/dividers and other sequential circuits. In this regard, a new multilevel flip-flop, called the AB flip-flop, was developed and published by the authors recently (Sarica and Morgul, Electron Lett 47(5):297–298, 2011). In this paper we present a new latch and restoration circuit which improves the performance of the previously designed flip-flop circuit. It is also shown that any sequential circuit may be implemented by using this flip-flop.     

A new systematic design approach for low-power analog integrated circuits

In this paper, a new design approach for systematic design and optimization of low-power analog integrated circuits is presented based on the proper combination of a simulation-equation based optimization algorithm using geometric programming as an optimization approach and HSPICE as a simulation and verification tool by a knowledge-based transistor sizing tool which uses physical-based gm/I_D characteristic in all regions of transistor operation to increase the accuracy in a reasonable simulation time. The proposed design methodology is successfully used for automated design and optimization of an operational amplifier with hybrid-cascode compensation using 0.18 μm CMOS technology parameters with the main purpose of minimizing the power consumption of the circuit.     

基于径向基函数神经网络的模拟/混合电路故障诊断

径向基函数神经网络是一种前馈型神经网络,具有较强的函数逼近能力和分类能力,学习速度快等优点.本文采用幅值恒定的正弦信号源进行模拟电路的故障仿真,从频域提取输出信号波形的特征值建立故障字典,应用径向基函数神经网络的这些优点进行响应分析和故障诊断,能够实现快速故障诊断及定位,具有准确率高的特点.     

Two analog counters for neural network implementation

Simple analog circuits which are useful for the implementation of the synchronous Boltzmann machine learning algorithms are presented. A simple charge-transfer-based analog counter is described. The authors give a functional model of its behavior and analyze the differences between this model and the counter implementation. They also present simulation results and the test of a prototype. Along the same lines, they study a switched-current-based counter, which achieves better results (dynamic range, linearity) through higher complexity     

A modular T-mode design approach for analog neural network hardwareimplementations

A modular transconductance-mode (T-mode) design approach is presented for analog hardware implementations of neural networks. This design approach is used to build a modular bidirectional associative memory network. The authors show that the size of the whole system can be increased by interconnecting more modular chips. It is also shown that by changing the interconnection strategy different neural network systems can be implemented, such as a Hopfield network, a winner-take-all network, a simplified ART 1 network, or a constrained optimization network. Experimentally measured results from CMOS 2-μm double-metal, double-polysilicon prototypes (MOSIS) are presented     

An analog continuous-time neural network

An analog continuous-time neural network is described. Building blocks which include the capability for on-chip learning and an example network are described and test results are presented. We are using analog nonvolatile CMOS floating-gate memories for storage of the neural weights. The floating-gate memories are programmed by illuminating the entire chip with ultraviolet light. The subthreshold operation of the CMOS transistor in analog VLSI has a very low power dissipation which can be utilized to build larger computational systems, e.g., neural networks. The experimental results show that the floating-gate memories are promising, and that the building blocks are operating as separate units; however, especially the time constants involved in the computations of the continuous-time analog neural network should be studied further.     

Analog electronic neural network circuits

It is argued that the large interconnectivity and the precision required in neural network models present novel opportunities for analog computing. Analog circuits for a wide variety of problems such as pattern matching, optimization, and learning have been proposed and a few have been built. Most of the circuits built so far are relatively small, exploratory designs. Circuits implementing several different neural algorithms, namely, template matching, associative memory, learning, and two-dimensional resistor networks inspired by the architecture of the retina are discussed. The most mature circuits are those for template matching, and chips performing this function are now being applied to pattern-recognition problems. Examples of analog implementation are examined     

Evolutionary derivation of optimal test sets for neural network based analog and mixed signal circuits fault diagnosis approach

Testing issues are becoming more and more important with the quick development of both digital and analog circuit industry. In this paper, we study the utilization of evolutionary algorithms for optimal input vectors derivation of neural network based analog and mixed signal circuits fault diagnosis approach and compare the results with normal method. We have introduced a new procedure which uses the n-detection test set concept and selects the input samples in a way that for each case of fault injection, there will be at least n sample to activate that fault. This procedure performs the optimization in two ways. The first one called speed method generates samples in a way that acceptable decision strength and lower training phase duration would be achieved. The second one called stamina method generates samples in a way that best decision strength and higher training phase duration would be achieved. Experimental results demonstrate that the obtained input voltages yields fault diagnosis with increased fault coverage and high decision strength.     

Short-open calibration technique for field theory-based parameter extraction of lumped elements of planar integrated circuits

A generalized short-open calibration (SOC) technique is developed toward complete field theory-based deembedding and lumped-element extraction of equivalent-circuit models for planar integrated circuits from admittance-type method of moments (MoM) simulations. With reference to the modal expansion modeling of a rectangular waveguide discontinuity, our investigation at first is to show the physical reason why there exist two aspects of numerical error in a deterministic MoM regarding a microstrip step discontinuity as the showcase in this study. In this SOC scheme, the identified two error sources are put together as a single error term or box for each feed line and then characterized by defining and evaluating two self-consistent calibration standards in the MoM, namely, short and open elements. As such, the core circuit model of the step discontinuity is effectively extracted by removing out two error terms. Subsequently, geometry- and frequency-dependent characteristics of the SOC technique are studied and discussed to demonstrate its effectiveness and accurateness as compared with the conventional transmission-line deembedding technique. After a series of validations by static analysis and measured results, the SOC scheme is used to model symmetrical and asymmetrical microstrip step discontinuities in terms of their equivalent dynamic circuit model over a wide frequency range.     

Physically realistic fault models for analog CMOS neural networks

A general methodology for the development of physically realistic fault models for VLSI neural networks is presented. The derived fault models are explained and characterized in detail. The application of this methodology to an analog CMOS implementation of fixed-weight (i.e., pretrained), binary-valued neural networks is reported. It is demonstrated that these techniques can be used to accurately evaluate defect sensitivities in VLSI neural network circuitry. It is also shown that this information can be used to guide the design of circuitry which fully utilizes a neural network's potential for defect tolerance     

A neural network algorithm for testing stuck-open faults in CMOS combinational circuits

In this article, an automatic test pattern generation technique using neural network models for stuck-open faults in CMOS combinational circuits is presented. For a gate level fault model of stuck-open faults in CMOS circuits, SR(slow-rise) and SF(slow-fall) gate transition faults we develop a neural network representation. A neural network computation technique for generating robust test patterns for stuck-open faults is given. The main result is extending previous efforts in stuck-at test pattern generation to stuck-open test pattern generation using neural network models. A second result is an extension of the technique to robust test pattern generation.     

A programmable analog cellular neural network CMOS chip for highspeed image processing

A high speed analog image processor chip is presented. It is based on the cellular neural network architecture. The implementation of an analog programmable CNN-chip in a standard CMOS technology is discussed. The control parameters or templates in all cells are under direct user control and are tunable over a continuous value range from 1/4 to 4. This tuning property is implemented with a compact current scaling circuit based on MOS transistors operating in the linear region. A 4×4 CNN prototype system has been designed in a 2.4 μm CMOS technology and successfully tested. The cell density is 380 cells/cm² and the cell time constant is 10 μs. The current drain for a typical template is 40 μA/cell. The real-time image processing capabilities of the system are demonstrated. From this prototype it is estimated that a 128×128 fully programmable analog image processing system can be integrated on a single chip using a standard digital submicron CMOS technology. This work demonstrates that powerful high speed programmable analog processing systems can be built using standard CMOS technologies     

Testing of programmable analog neural network chips

Artificial neural network chips can achieve high-speed performance in solving complex computational problems for signal and information processing applications. These chips contain regular circuit units such as synapse matrices that interconnect linear arrays of input and output neurons. The neurons and synapses may be implemented in an analog or digital design style. Although the neural processing has some degree of fault tolerance, a significant percentage of processing defects can result in catastrophic failure of the neural network processors. Systematic testing of these arrays of circuitry is of great importance in order to assure the quality and reliability of VLSI neural network processor chips. The proposed testing method consists of parametric test and behavioral test. Two programmable analog neural chips have been designed and fabricated. The systematic approach used to test the chips is described, and measurement results on parametric test are presented.This research was partially supported by DARPA under Contract MDA 972-90-C-0037 and by National Science Foundation under Grant MIP-8904172.     

Programmable-weight building blocks for analog VLSI neural network processors

Although the neural network paradigms have the intrinsic potential for parallel operations, a traditional computer cannot fully exploit it because of the serial hardware configuration. By using the analog circuit design approach, a large amount of parallel functional units can be realized in a small silicon area. In addition, appropriate accuracy requirements for neural operation can be satisfied. Components for a general-purpose neural chip have been designed and fabricated. Dynamically adjusted weight value storage provides programmable capability. Possible reconfigurable schemes for a general-purpose neural chip are also presented. Test of the prototype neural chip has been successfully conducted and an expected result has been achieved.     

基于GRU网络的互联网信息挖掘

Web已经发展为世界上最大的公共数据来源,从海量异构、半结构化的Web页面中提取特定信息逐渐成为数据挖掘的重要任务。目前信息提取任务研究的重心正在逐渐转向深度学习领域,本文提出基于双向GRU(Gated Recurrent Unit)的深度神经网络模型进行Web信息提取,解决序列长距离依赖问题,采用词嵌入结合字符嵌入算法加强语义表达,减少冗余文本干扰,双向模型充分利用文本上下文,快速、准确地对输入序列实现特定信息提取。