Characteristics of a 1.2-µm CMOS technology fabricated on an RF-heated zone-melting recrystallized SOI

0.7-5-µm CMOSFET's were fabricated on SOI which was recrystallized using an RF-heated zone-melting recrystallization (RFZMR) method. The leakage currents of n-channel MOSFET's having gate lengths between 5- and 0.7-µm range between 10^-14and 10^-12A/µm and show no dependence on channel length. Those of the p-channel MOSFET's were 10^-14-10^-12A/µm when the gate lengths were longer than 1.2 µm, and increased when the gate lengths were shorter than 1.0 µm. The propagation delay time of the CMOSFET inverter was 0.13 ns per stage at a supply voltage of 3.5 V.     

Formation of TiN/TiSi2/p+-Si/n-Si by rapid thermal annealing (RTA) silicon implanted with boron through titanium

A low temperature method of fabricating conductive (3.5 Ω/ sq.) p⁺/n junction diodes possessing excellentI-Vcharacteristics with reverse-bias leakage less than -3 nA.cm^-2at -5 V is described. Single crystal n-type 〈100〉 Si is implanted with 60 keV¹¹B+through 0.028-µm thick sputtered Ti film. Rapid thermal annealing (RTA) in an N2ambient simultaneously forms a 0.36-µm deep p⁺/n junction and a 0.063-µm thick bilayer of TiN and TiSi2with a resistivity of 22 µΩ.cm. The electrical properties of these diodes are not degraded by annealing for 30 min at 500°C, suggesting that the outer layer of TiN is an effective diffusion barrier between TiSi2and Al.     

Mo- and Ti-silicided low-resistance shallow junctions formed using the ion implantation through metal technique

Mo-and Ti-silicided junctions were formed using the ITM technique, which consists of ion implantation through metal (ITM) to induce metal-Si interface mixing and subsequent thermal annealing. Double ion implantation, using nondopant ions (Si or Ar) implantation for the metal-Si interface mixing and dopant ion (As or B) implantation for doping, has resulted in ultrashallow ( ≤ 0.1-µm) p⁺-n or n⁺-p junctions with ∼30-Ω sheet resistance for Mo-silicided junctions and ∼5.5-Ω sheet resistance for Ti-silicided junctions. The leakage current levels for the Mo-silicided n⁺-p junctions (0.1-µm junction depth) and the Mo-silicided p⁺-n junction (0.16-µm junction depth) are comparable to that for unsilicided n⁺-p junction with greater junction depth ( ∼0.25 µm).     

Ga0.4In0.6As/Al0.55In0.45As pseudomorphic modulation-doped field-effect transistors

High-performance pseudomorphic Ga0.4In0.6As/ Al0.55In0.45As modulation-doped field-effect transistors (MODFET's) grown by MBE on InP have been fabricated and characterized. DC transconductances as high as 271, 227, and 197 mS/mm were obtained at 300K for 1.6-µm and 2.9-µm gate-length enhancement-mode and 2-µm depletion-mode devices, respectively. An average electron velocity as high as 2.36 × 10⁷cm/s has been inferred for the 1.6-µm devices, which is higher than previously reported values for 1-µm gate-length Ga0.47In0.53As/Al0.48In0.52As MODFET's. The higher bandgap Al0.55In0.45As pseudomorphic barrier also offers the advantages of a larger conduction-band discontinuity and a higher Schottky barrier height.     

Direct measurement of stray magnetic field distributions from a magnetic bubble domain in yttrium orthoferrite with a micro Hall element

The stray magnetic field distributions from an isolated magnetic bubble domain of about 150-µm diameter in YFeO3are measured by a micro Hall element made of a single crystal InSb with active dimensions of 5 × 5 × 2.6 µm³. Experimental results for an isolated bubble domain show fair agreement with the theoretical ones for a cylindrical bubble domain.     

Utilization of NiSi2as an interconnect material for VLSI

The applicability of NiSi2as an interconnect material was investigated using narrow (5 µm- × 2600-µm) lines. 2500-Å-thick silicide lines were thermally oxidized to form a passivation layer of SiO2for the next metallization level. Isolation of more than 50 V for 2200-Å SiO2is achieved. The interconnect resistivity following the oxidation is 1.2-1.4 Ω. The maximum current capability of the lines was found to be > 5 × 10⁶A/cm²and their stability under prolonged high current densities was demonstrated. We propose a scheme to increase the local metallization-level density using NiSi2as an interconnect.     

Monolithic silicon mosaics for far-infrared imaging

Monolithic detector mosaics were constructed for image sensing at wavelengths from three to 30 µm. The mosaics use impurity photoconduction in silicon to sense infrared radiation. Operation in the 25 to 40°K temperature range is obtained with closed-cycle cooling. Photosensor elements, spaced on 32 mil centers, are formed by solid-state diffusion, and a junction diode is constructed in series with each photoresistor to reduce crosstalk. The integrated 30-by-30 mosaics have crossedX-Yelectrodes for direct-wire readout of picture elements. Performance of individual elements is described. At 25°K, a detectivity of 1 × 10⁸cm Hz^1/2/W per element is found using 10.6 µm CO2laser radiation. The quantum efficiency at 10.6 µm is about 7 percent, and the response time is observed to be less than 0.2 µs. Uniformity and crosstalk data on prototype arrays are presented, and the integration of these arrays with cryogenic amplifier and scanning circuits is discussed.     

Normally-off InGaAs junction field-effect transistor with InGaAs buffer layer

InGaAs junction field-effect transistors (JFET's) with 1-µm gate length were successfully fabricated with an n⁺-InGaAs active layer (8 × 10¹⁶cm^-3) and an undoped InGaAs buffer layer grown on semi-insulating InP:Fe substrate by liquid-phase epitaxy. The device showed good pinch-off behavior with a threshold voltage of 0.25 V, a low drain current of 1 µA at zero gate-source voltage, and a very high transconductance of 553 mS/mm at room temperature. This is one of the highest transconductance values ever reported for a 1-µm gate-length FET.     

A study of high-speed normally off and normally on Al0.5Ga0.5As heterojunction gate GaAs FET's (HJFET)

The dc, small-signal microwave, and large-signal switching performance of normally off and normally on Al0.5Ga0.5As gate heterojunction GaAs field-effect transistors (HJFET) with submicrometer gate lengths are reported. The structure of both types of devices comprises an n-type 10¹⁷-cm^-3Sn-doped active layer on a Cr-doped GaAs substrate, a p-type 10¹⁸-cm^-3Ge-doped Al0.5Ga0.5As gate layer and a p⁺-type 5 × 10¹⁸-cm^-3Ge-doped GaAs "contact and cap" layer on the top of the gate. The gate structure is obtained by selectively etching the p⁺-type GaAs and Al0.5Ga0.5As. Undercutting of the Al0.5Ga0.5As layer results in submicrometer gate lengths, and the resulting p⁺-GaAs overhang is used to self-align the source and the drain with respect to the gate. Normally off GaAs FET's with 0.5- to 0.7-µm long heterojunction gates exhibit maximum available power gains (MAG) of about 9 dB at 2 GHz. Large-signal pulse measurements indicate an intrinsic propagation delay of 40 ps with an arbitrarily chosen 100-Ω drain load resistance in a 50-Ω microstrip circuit. Normally on FET's with submicrometer gate lengths (∼0.6 µm) having a total gate periphery of 300 µm and a corresponding dc transconductance of 20-30 mmhos exhibit a MAG of 9.5 dB at 8 GHz. The internal propagation delay time measured under the same conditions as above is about 20 ps.     

Interaction of 10.6-µm radiation with current carriers in germanium

The absorption of 10.6-µm energy by excess carriers in germanium is used to study carrier density profiles within the bulk of intrinsic materials. Excess carriers are injected into blocks of germanium. The material is probed by an optical beam from a CO2laser and the energy in the exit ray is measured to determine carrier absorption. Carrier density in the material is found to correspond to two distinct patterns. The determination of carrier cross section is discussed.     

Hybrid IRCCD imaging array

A hybrid IRCCD for high background application has been successfully fabricated. The device consists of fifty Hg0.7Cd0.3Te detector diodes of 50-µm × 50-µm sensitive areas and a silicon CCD maltiplexer with input circuits on 40-µm centers having bucket background subtraction and blooming protection circuits. The noise-equivalent power (NEP) of the IRCCD is 5 × 10^-14W-Hz^-1/2at background photon flux level of 4 × 10¹⁵photons . cm^-2s^-1, integration time of 2 × 10^-5s, and clock frequency of 3 × 10⁶Hz. The noise source of the detector diodes limits the IRCCD performance. The IRCCD is also evaluated with the real-time raster-scanned thermal images displayed on a CRT monitor. Two-dimensional images are generated by using a scanning mirror. A fixed-pattern noise is reduced by comparison of an object video to the reference video stored in a memory. A noise-equivalent temperature difference of the system is 0.6°C at a frame rate of 30 Hz. Instantaneous field of view is 1 mrad × 1 mrad and the field of view of the system is 12° × 5.7°.     

High-transconductance p-channel modulation-doped AlGaAs/GaAs heterostructure FET's

p-channel modulation-doped AlGaAs-GaAs heterostructure FET's (p-HFET's) employing two-dimensional hole gas (2DHG) were fabricated under various geometrical device parameter conditions. The p-HFET characteristics were measured at 300 and 77 K for the following three device-parameter ranges: the gate length Lg(1-320 µm), the gate-source distance Lgs(0.5-5 µm), and the layer thickness dt(35-58 nm) of AlGaAs beneath the gate. Based on the obtained results, a high-performance enhancement-mode p-HFET was fabricated with the following parameters:L_{g} = 1µm,L_{gs} = 0.5µm, andd_{t} = 35nm. The achieved extrinsic transconductance gmwas 75 mS . mm^-1at 77 K. This experimental result indicates that a gmgreater than 200 mS . mm^-1at 77 K Can be obtained in 1-µm gate p-HFET devices.     

Boron ion implantation in silicon through selectively deposited tungsten films

The effect of implanting boron into silicon through thin selective tungsten films and annealing to form silicided p⁺-n junctions is investigated. A rate limited thickness of 0.011-µm tungsten is shown to have the equivalent stopping power of 0.08-µm oxide and be similarly ineffective in eliminating axial boron channeling. Nonetheless, junction diodes as shallow as 0.25µm with sheet resistances of 7 Ω, exhibiting nearly idealI-Vcharacteristics from -40 to 100°C, are fabricated. Analysis of the areal and perimeter leakage currents suggests that defects at the WSi2-SiO2interface are the contributing generation-recombination sites.     

Electron beam direct writing technology applied to 512 kbit ROM with 1 µm geometry

A 512 kbit read-only memory (ROM) to store Chinese ideographs has been fabricated using variable-shaped electron beam and dry-etching lithography. 1.0-µm minimum line width was used to delineate device area spacings smaller than those obtained with conventional design rules using photoimaging techniques. SiO2, Si3N4, and polysilicon etchings were accomplished by reactive sputter techniques with CF4+ H2and CCl3F gases using negative electron beam resist PGMA and positive resist AZ-2400. Al etching was carried out by plasma with CCl4gas using negative electron beam resist NER-1. The alignment marks detectability and their locating accuracy were improved by properly using the basis arithmetic operations, subtraction and summation, in backscatter signal processings. 6.6 mm × 8.9 mm chip-by-chip alignment yielded about 0.2-µm level-to-level registration accuracy. Memory cell size and chip size are 5.2 µm × 8.4 µm and 6.6 mm × 8.9 mm, respectively; access time and power dissipation are 400 ns and 800 mW, respectively.     

Formation of shallow p+-n junctions using boron-nitride solid diffusion source

Shallow p⁺-n junctions on the order of 0.1-µm deep have been fabricated using boron-nitride (BN) solid diffusion sources. The process combines the hydrogen-injection method and rapid thermal processing (RTP). Sheet resistivities, in ranges from 50 to 130 Ω/sq with junction depths from 0.1 to 0.19 µm, are possible in this technique. Diode characteristics of 0.11-µm junctions show low reverse leakage current, of the order of 10 nA/cm², indicating the possibility of this method to form PMOS source-drain contacts.     

0.4-µm gate-length devices fabricated by contrast-enhanced lithography

This letter describes the fabrication of submicrometer polysilicon-gate MOS devices by an advanced optical process called contrast enhancement. Functional devices having gate lengths as small as 0.4 µm were fabricated with this process. Contrast-enhanced lithography (CEL) allows usable photoresist patterns to be fabricated at smaller dimensions than is possible with conventional resist. The simultaneous replication of mask dimensions for isolated lines at 0.35 µm and above was achieved in this work using a single exposure on an Optimetrix 10:1 DSW system. Contrast enhancement has been applied to the fabrication of n-channel MOS devices having gate lengths from 0.4 to 1.5 µm in steps of 0.1 µm. Long-channel devices were also fabricated. The transconductance of the 0.4-µm devices is 40 mS/mm at Vds= 5 V. Threshold voltages (Vds= 0) are nearly independent of gate length, ranging from 1.21 to 1.31 V over the 7.5- to 0.4-µm range in gate length. The effective mobility for long-channel devices is 430 cm²/V.s.     

An Hg0.3Cd0.7Te avalanche photodiode for optical-fiber transmission systems at λ = 1.3 µm

The purpose of this paper is the characterization of Hg0.3Cd0.7Te avalanche photodiodes at γ = 1.3 µm. These devices are manufactured by tile Société Anonyme des Télécommunications. The multiplication noise for these APD's is measured. The value of the ratiok= β/α is deduced from noise measurements, β and α being, respectively, the hole and electron ionization coefficients. It is shown that these HgCdTe APD's are promising candidates for detectors of 1.3-µm optical communication.     

GaAs MESFET fabrication using maskless ion implantation

A 2000-Å-diameter focused-ion beam from a Au-Si liquid-metal-alloy ion source was used to implant the doped regions of GaAs metal-semiconductor gate field-effect transistors. An Al stopping layer on the wafer was used to trap the Au ions. The 140-keV Si⁺⁺beam component was deflected under computer control to implant 8 × 50 µm active channel regions and 16 × 50 µm contact regions. The devices were metallized using conventional lithography. DC electrical characteristics of the 1.5-µm-gate-length devices are comparable to those of conventionally processed devices of identical geometry.     

Limitations on injection efficiency in power devices

In this paper the mechanisms of bandgap narrowing, Shockley-Read-Hall (SRH) recombination, Auger recombination, and carrier-carrier and carrier-lattice scattering are included in an exact one-dimensional model of a bipolar transistor. The transistor is used as a vehicle for studying the relative importance of each of these phenomena in determining emitter efficiency in devices with emitter junction depths of 1 µm to 8 µm. It is shown that bandgap narrowing is the dominant influence for devices with shallow emitters of 2 µm or less and that SRH recombination dominates for emitter depths greater than 4 µm. Calculations are also presented showing the effects of the emitter surface concentration and high-level injection on the current gain for devices with emitter junction depths of 1 µm to 8 µm. It is shown that there is an optimum surface concentration of 5 × 10¹⁹cm^-3for the 1-µm emitter depth but no optimum under 10²¹cm^-3for devices with emitter depths greater than 4 µm.     

GaInAsP/InP fast, high-radiance, 1.05-1.3-µm wavelength LED's with efficient lens coupling to small numerical aperture Silica optical fibers

Power levels up to 100 µW have been launched from GaInAsP LED's with 14-µm-diameter emitting regions into low-loss small numerical aperture (NA) silica fibers at a dc drive level of only 25 mA. A maximum launch power of 206 µW at 100-mA dc was obtained from slightly larger devices. The high coupling efficiency was achieved using truncated spheres of Ti2O3:SiO2glass as microlenses. Gains over the butt coupled case exceeded a factor of twelve for the small-area devices. The high operating current densities (2-20 kA/cm²) for the small-area devices resulted in modulation bandwidths extending to beyond 300 MHz (-3 dB optical). The surface-emitting LED's showed an enhanced performance over edge-emitting LED's fabricated from similar material. Linewidths of the devices, which were prepared by liquid-phase epitaxy with step followed by ramp cooling, were approximately 3 kT. Even with the relatively broad linewidth, material dispersion limits in silica fibers exceeding 1 GHz . km around 1.3 µm are predicted. These devices are suitable for long-haul, wide-bandwidth fiber links operating in the 1.3-µm window.