A 5.2-GHz CMOS receiver with 62-dB image rejection

A 5.2-GHz CMOS receiver employs a double downconversion heterodyne architecture with a local oscillator frequency of 2.6 GHz and applies offset cancellation to the baseband amplifiers. Placing the image around the zero frequency, the receiver achieves an image rejection of 62 dB with no external components while minimizing the flicker noise upconversion in the first mixing operation. Realized in a 0.25-μm digital CMOS technology, the circuit exhibits a noise figure of 6.4 dB, an IP₃ of -15 dBm, and a voltage conversion gain of 43 dB, while draining 29 mW from a 2.5-V supply     

10 GHz dual-conversion low-IF downconverter with microwave and analogue quadrature generators

A 10 GHz dual-conversion low-IF downconverter using 0.18-mum CMOS technology is demonstrated. The high-frequency quadrature RF and LO₁ signals are generated by broadside-coupled quadrature couplers while a two-section polyphase filter is utilised for the low-frequency LO₂ quadrature signal generation. As a result, the demonstrated downconverter achieves a conversion gain of 7 dB, IP_{1 dB} of -16 dBm, IIP₃ of -5 dBm and noise figure of 26 dB at a 1.8 V supply. The image-rejection ratio of the first/second image signal is 33/42 dB for IF frequency ranging from 10 to 60 MHz, respectively.     

An Ultra-Wideband High-Linearity CMOS Mixer With New Wideband Active Baluns

A 2-11-GHz high linearity CMOS down-conversion mixer with wideband active baluns using 0.18-mum CMOS technology is demonstrated in this paper. The mixer employs a folded cascode Gilbert cell topology and on-chip broadband active baluns. The folded cascode approach is adopted to increase the output swing, and the linearity is enhanced by a harmonic distortion canceling technique derived from the harmonic balance analysis. The proposed configuration shows the highest IIP₃ and IP_{1 dB}, and exhibits more compact size than most published studies. A broadband active balun is used to generate wideband differential signals, together with the derivation of a closed-form expression for the phase imbalance. This single-ended wideband mixer has the conversion gain of 6.9plusmn1.5 dB, input 1-dB compression point (IP_{1 dB}) of - 3.5 dBm, single-sideband noise figure of 15.5 dB, and third-order input intercept point (IIP₃) of 6.5 dBm under the power consumption of 25.7 mW from a 1.8-V power supply. The chip area is 0.85 x 0.57 mm².     

10-GHz Highly Symmetrical Sub-Harmonic Gilbert Mixer Using GaInP/GaAs HBT Technology

A 10-GHz sub-harmonic Gilbert mixer is demonstrated using GaInP/GaAs hetero-junction bipolar transistor technology. The local oscillator (LO) signal time-delay path in the sub-harmonic LO stage is compensated using the fully symmetrical stacked-LO doubler; therefore, the balance of the sub-harmonic LO stage, the radio frequency to intermediate frequency isolation, and IIP₂ are improved. The demonstrated 10-GHz sub-harmonic mixer achieves 10 dB conversion gain, IP_1dB of -12 dBm, IIP₃ of 2 dBm and IIP₂ of 33 dBm     

80-GHz Tuned Amplifier in Bulk CMOS

An 80-GHz six-stage common source tuned amplifier has been demonstrated using low leakage (higher V_T) NMOS transistors of a 65-nm digital CMOS process with six metal levels. It achieves power gain of 12 dB at 80 GHz with a 3-dB bandwidth of 6 GHz, noise figures (NF's) lower than 10.5 dB at frequencies between 75 and 81 GHz with the lowest NF of 9 dB. IP_{1 dB} is -21 dBm and IIP3 is -11.5 dBm. The amplifier consumes 27 mA from a 1.2 V supply. At V_DD = 1.5 V and 33 mA bias current, NF is less than 9.5 dB within the 3-dB bandwidth and reaches a minimum of 8 dB at 80 GHz.     

A Novel Linearization Method of CMOS Drive Amplifier Using IMD Canceller

A novel linearization method for CMOS drive amplifier using intermodulation distortion (IMD) canceller is presented. The IMD cancellation method is composed of a cascode main amplifier and a common-source IMD canceller. The additional common-source amplifier generates IMD3 signals with 180deg phase difference against the IMD3 of the cascode main amplifier. The linear drive amplifier is designed and fabricated by CMOS 0.18 mum process. The output IP₃ of +13 dBm is achieved with the power gain of +11.6 dB, the output P_{1 dB} of + 5.5 dBm, and the power-added efficiency of 21%.     

Single-Chip W-band SiGe HBT Transceivers and Receivers for Doppler Radar and Millimeter-Wave Imaging

This paper presents the first single-chip direct-conversion 77-85 GHz transceiver fabricated in SiGe HBT technology, intended for Doppler radar and millimeter-wave imaging, particularly within the automotive radar band of 77-81 GHz. A 1.3 mm times 0.9 mm 86-96 GHz receiver is also presented. The transceiver, fabricated in a 130 nm SiGe HBT technology with f_T/f_MAX of 230/300 GHz, consumes 780 mW, and occupies 1.3 mm times 0.9 mm of die area. Furthermore, it achieves 40 dB conversion gain in the receiver at 82 GHz, a 3 dB bandwidth extending from 77 to 85 GHz at 25degC, and covering the entire 77-81 GHz band up to 100degC, record 3.85 dB DSB noise figure measured at 82 GHz LO and 1 GHz IF, and an IP_1dB of -35 dBm. The transmitter provides + 11.5 dBm of saturated output power at 77 GHz, and a divide64 static frequency divider is included on-die. Successful detection of a Doppler shift of 30 Hz at a range of 6 m is shown. The 86-96 GHz receiver achieves 31 dB conversion gain, a 3 dB bandwidth of 10 GHz, and 5.2 dB DSB noise figure at 96 GHz LO and 1 GHz IF, and -99 dBc/Hz phase noise at 1 MHz offset. System-level layout and integration techniques that address the challenges of low-voltage transceiver implementation are also discussed.     

Broadband single- and double-balanced resistive HEMT monolithicmixers

A double-balanced (DB) 3-18 GHz and a single-balanced (SB) 2-16 GHz resistive HEMT monolithic mixer have been successfully developed. The DB mixer consists of a AlGaAs/InGaAs HEMT quad, an active LO balun, and two passive baluns for RF and IF. At 16 dBm LO power, this mixer achieves the conversion losses of 7.5-9 dB for 4-13 GHz RF and 7.5-11 dB for 3-18 GHz RF. The SB mixer consists of a pair of AlGaAs/InGaAs HEMT's, an active LO balun, a passive IF balun and a passive RF power divider. At 16 dBm LO power, this mixer achieves the conversion losses of 8-10 dB for 4-15 GHz RF and 8-11 dB for 2-16 GHz RF. The simulated conversion losses of both mixers are very much in agreement with the measured results. Also, the DB mixer achieves a third-order input intercept (IP₃) of +19.5 to +27.5 dBm for a 7-18 GHz RF and 1 GHz IF at a LO drive of 16 dBm while the SB mixer achieves an input IP ₃ of +20 to +28.5 dBm for 2 to 16 GHz RF and 1 GHz IF at a 16 dBm LO power. The bandwidth of the RF and LO frequencies are approximately 6:1 for the DB mixer and 8:1 for the SB mixer. The DB mixer of this work is believed to be the first reported DB resistive HEMT MMIC mixer covering such a broad bandwidth     

A Low-Cost and Low-Power CMOS Receiver Front-End for MB-OFDM Ultra-Wideband Systems

This paper presents an RF receiver front-end for MB-OFDM-based ultra-wideband (UWB) systems. The receiver occupies only 0.35 mm² in a 0.18 mum CMOS process and consists of a low-noise amplifier, downconverter and a bandpass filter. There are no on-chip inductors and the receiver requires no off-chip matching components. The measured receiver gain is 21 dB, noise figure is less than 6.6 dB, input IIP₃ is -5.6 dBm, and the receiver consumes 19.5 mA from a 2.3 V supply. The receiver covers all the MB-OFDM bands from 3.1 to 8 GHz     

Design and performance of octave S/C band MMICT/R modules for multi-function phased arrays

A complex wideband transmit/receive module that achieves performance levels superior to any MMIC module is described. Peak performance within the octave 3.0 to 6.0 GHz band includes a power output of 21 W at S-band and 19 W at C-band, a noise figure of 3.9 to 5.0 dB, 30 to 38 dB of receive gain, 25 to 26 dBm output IP₃, 40 dB of gain control in 256 steps, dual receive channels with independent amplitude and phase control, and an 8-bit phase shifter with less than 1 degree calibrated RMS phase error. Total GaAs area is 146 mm² with 170 mm of total gate periphery. The module incorporates a compact digital interface, requires only three supply voltages, and utilizes advanced packaging techniques, resulting in a size compatible with a grating lobe free grid spacing     

Noise model of InP-InGaAs SHBTs for RF circuit design

A scalable small-signal and noise model of InP-InGaAs single heterojunction bipolar transistors was developed. Effects which become important at higher frequencies such as the correlation between base and collector current noise and frequency-dependent base current noise are taken into account. We will show that these effects are significant at frequencies higher than 40 GHz and can no longer be neglected. Our model also includes the effects of the different emission coefficients of the base and collector currents. Using this improved model, a direct-coupled, lumped broad-band amplifier was designed. We completely characterized the fabricated circuit with respect to small-signal, noise, and linearity behavior. A -3-dB bandwidth of 50 GHz with a dc gain of 9.8 dB and a gain-peaking of only 1.2 dB were achieved. All these values agree very well with the simulation results. The noise figure is 7.5 dB over a large frequency range. In the frequency range from 2 to 50 GHz, the third-order intercept point IP₃ and 1-dB compression point at the output have values from 17 to 10 dBm and 3 to 0 dBm, respectively     

A 50 to 70 GHz Power Amplifier Using 90 nm CMOS Technology

A 50 to 70 GHz wideband power amplifier (PA) is developed in MS/RF 90 nm 1P9M CMOS process. This PA achieves a measured P_sat of 13.8 dBm, P_{1 dB} of 10.3 dBm, power added efficiency (PAE) of 12.6%, and linear power gain of 30 dB at 60 GHz under V_DD biased at 1.8 V. When V_DD is biased at 3 V, it exhibits P_sat of 18 dBm, P_{1 dB} of 12 dBm, PAE of 15%, and linear gain of 32.4 dB at 60 GHz. The MMIC PA also has a wide 3 dB bandwidth from 50 to 70 GHz, with a chip size of 0.66 times 0.5 mm². To the author's knowledge, this PA demonstrates the highest output power, with the highest gain among the reported CMOS PAs in V-band.     

A temperature-dependent nonlinear analysis of GaN/AlGaN HEMTs usingVolterra series

Gain and intermodulation distortion of an AlGaN/GaN device operating at RF have been analyzed using a general Volterra series representation. The circuit model to represent the GaN FET is obtained from a physics-based analysis. Theoretical current-voltage characteristics are in excellent agreement with the experimental data. For a 1 μm×500 μm Al_0.15Ga_0.85N/GaN FET, the calculated output power, power-added efficiency, and gain are 25 dBm, 13%, and 10.1 dB, respectively, at 15-dBm input power, and are in excellent agreement with experimental data. The output referred third-order intercept point (OIP₃) is 39.9 dBm at 350 K and 33 dBm at 650 K. These are in agreement with the simulated results from Cadence, which are 39.34 and 35.7 dBm, respectively. At 3 GHz, third-order intermodulation distortion IM₃ for 10-dBm output power is -72 dB at 300 K and -56 dB at 600 K. At 300 K, IM₃ is -66 dB at 5 GHz and -51 dB at 10 GHz. For the same frequencies, IM ₃ increases to -49.3 and -40 dB, respectively, at 600 K     

Broadband monolithic passive baluns and monolithic double-balancedmixer

The design and fabrication of four broadband monolithic passive baluns including CPW Marchand, multilayer MS Marchand, planar-transformer and broadside-coupled line baluns are presented. Operational frequencies range from 1.5 GHz to 24 GHz. Maximum relative bandwidths in excess of 3:1 are achieved. Simulated performances using full wave electromagnetic analysis are shown to agree with the measured results. Two accurate equivalent circuit models constructed from either electromagnetic simulated or measured S-parameters are developed for the MS Marchand and transformer baluns making the optimization of baluns and circuit design using the baluns much more efficient. The design of monolithic double-balanced diode mixer using two planar-transformer baluns is also presented. Without DC bias, the mixer shows a minimum conversion loss of 6 dB with the RF at 5 GHz and a LO drive of 15 dBm at 4 GHz. The measured input IP₃ of this mixer is better than 15 dBm over the 4 to 5.75 GHz frequency band     

A Fully Integrated Ultra-Low Insertion Loss T/R Switch for 802.11b/g/n Application in 90 nm CMOS Process

A 30 dBm ultra-low insertion loss CMOS transmit-receive switch fully integrated with an 802.11b/g/n transceiver front-end is demonstrated. The switch achieves an insertion loss of 0.4 dB in transmit mode and 0.1 dB in receive mode. The entire receiver chain from antenna to baseband output achieves a measured noise figure of 3.6 dB at 2.4 GHz. The switch has a P_1dB greater than 30 dBm by employing a substrate isolation technique without using deep n-well technology. The switch employs a 1.2 V supply and occupies 0.02 mm² of die area.     

2.488 Gb/s-318 km repeaterless transmission using erbium-dopedfiber amplifiers in a direct-detection system

The authors have achieved a 2.488 Gb/s, 318 km repeaterless transmission without any fiber dispersion penalty through a nondispersion-shifted fiber in a direct detection system. The system was loss limited with a T-R power budget of 57 dB. Three key components enabled the authors to achieve this result: (1) a Ti:LiNbO₃ external amplitude modulator enabling a dispersion-free transmission, (2) erbium-doped fiber amplifiers increasing the transmitting power to +16 dBm, and (3) an erbium-doped fiber preamplifier enabling a high-receiver sensitivity of -4.1 dBm for 10^-9 BER. To the author's knowledge, this result is the longest repeaterless transmission span length ever reported for direct detection at this bit rate. From the experimental results and a theoretical model, the authors identified the sources of the receiver sensitivity degradation from the quantum limit (-48.6 dBm) and estimated the practically achievable receiver sensitivity of ~-44 dBm (~-124 photons/bit) for 2.5 Gb/s optical preamplifier detection     

A Broadband Low-Cost Direct-Conversion Receiver Front-End in 90 nm CMOS

Transistors in aggressively scaled CMOS technologies have f_T greater than 150 GHz, which exceeds requirements for most existing commercial applications below 10 GHz. Excess transistor performance can be traded-off for cost by designing out inductors. This paper presents a prototype which exploits the speed of transistors to design highly integrated broadband receiver front-ends. The inductor-less prototype operates from 2 to 5.8 GHz and dissipates 85 mW at 5 GHz while occupying 0.2 mm² active area. It provides 44 dB of gain, 3.4 dB double side band noise figure, 21 dBm in-band IIP3 in the highest gain mode and 15 dB input matching.     

High-speed monolithic silicon photoreceivers on high resistivityand SOI substrates

We compare monolithic silicon optical receivers fabricated on high resistivity and silicon-on-insulator (SOI) substrates. Each receiver consisted of a lateral p-i-n photodiode and an NMOS transimpedance preamplifier. At a drain voltage (V_DD) of 3.5 V, a photodiode voltage (V_PD) of 30 V, and a wavelength of 850 nm, the high resistivity receiver exhibited sensitivities of -31.9 dBm at 622 Mb/s and -23.2 dBm at the maximum operating speed of 1.0 Gb/s. At V_DD =5 V and V_PD=20 V, the sensitivity of the SOI receiver was -26.1 dBm at 622 Mb/s, -20.2 dBm at 1.0 Gb/s and -12.2 dBm at the maximum speed of 2.0 Gb/s. Single supply operation at 5 V and 3 V was also demonstrated for the SOI receiver. Methods for extending the speed and improving the sensitivity characteristics in more advanced technologies with lower supply voltages are discussed     

1.2V and 8.6mW CMOS differential receiver front-end with 24 dB gain and -11dBm IRCP

A 60 GHz CMOS differential receiver front-end has been demonstrated by using a novel transformer-folded-cascade (Origami) circuit architecture with high gain (24 dB without buffer amplifier), high linearity (-11 dBm input referred P_{1 dB} compression point, or IRCP), low power dissipation (4.3 mW/arm) and small die area (0.022 mm²)     

A high-IP3 RF receiver chip set for mobile radio base stations upto 2 GHz

We present a monolithically integrated high third-order intercept point (IP3) radio frequency (RF) receiver chip set for mobile radio base stations up to 2 GHz, in a 25-GHz f_T Si bipolar production technology. The chip set consists of a RF preamplifier, active mixer circuits, and an intermediate frequency (IF) limiter. The preamplifier gain is 12 dB, the noise figure is 5.5 dB at 900 MHz, and the output (OIP3) is up to +24 dBm depending on supply voltage. The two different mixers provide a conversion gain of 1.5 dB up to 3 dB, an OIP3 in the range of +21 dBm up to +29 dBm, and a minimal single sideband (SSB) noise figure of 13 dB. The IF limiter shows an excellent limiting characteristic at 10 dBm output power and has a high bandwidth of more than 1 GHz