Design of a New High Speed Amplifier Circuit for the Analog Subsystems

A high speed CMOS amplifier circuit with a new architecture especially suited for analog subsystems and a simple high speed CMOS comparator utilizing the proposed CMOS amplifier circuit are presented. The proposed circuit is simulated using 0.35 m process parameters. The configuration results in several performance improvements over a typical CMOS differential to single ended amplifier. Design details and simulation results show that the newly designed CMOS amplifier circuit and the high speed CMOS comparator are applicable to high speed analog subsystems, especially the flash A/D converter.     

DB-driver: a low power CMOS bootstrapped differential cross-coupled driver

This paper for the first time reports the design of a high speed and low power differential cross-coupled bootstrapped CMOS driver circuit. The circuit design style, based on the proposed differential cross-coupled bootstrapped driver achieves high performance low core area, and fast full-swing operation, even in spite of the fact that the magnitude of the threshold voltage of the CMOS devices cannot be scaled down with the scaling of the power supply voltage. The proposed driver is implemented on 0.13?µm CMOS technology with a power supply of 1.2?V. It is 34% faster and provides 8% less core area when compared to a base-line circuit using an indirect bootstrap technique. In addition, the proposed driver reduces the power consumption by 35%. The superior performance of the proposed circuit over the other differential cross-coupled bootstrapped CMOS driver circuit, for the applications that require high performance, has been verified with post-layout simulation.     

Versatile high voltage level shift and driver for MEMS applications

A high voltage (>50 V) driver with a simple interface to 5 V or 3.3 V conventional CMOS is described. Unlike previous such circuits, the static current is zero for full CMOS compatibility. The circuit has been realised on a multi-sourced high voltage CMOS process.     

CMOS掉电保护电路

介绍了一种提高单片机运行可靠性的片内掉电保护电路，该电路可以检测电源电压的降低状况，并按规定的要求在电源电压降至下限阈值时启动内部复位产生器，从而复位ＣＰＵ并保证使其处于复位状态直至电源电压恢复正常。该ＣＭＯＳ掉电保护电路由取样电阻、１．２Ｖ参考电压源和ＣＭＯＳ电压比较器组成，并结合片内复位逻辑完成掉电保护功能。     

一种长波红外光导探测器CMOS电路设计

CMOS 电路是高输入阻抗,而长波红外光导探测器是低阻抗,实现低阻抗红外光导探测器与CMOS 电路的良好匹配,是目前长波红外探测器高性能成像的关键技术。文中设计了一种能在低温下工作的低阻抗红外光导探测器CMOS 电路,差分放大器采用正负电源供电,在输入级采用桥式输入方式,该电路第一级采用1M的负反馈电阻实现信号放大,第二级放大采用正端放大方式,输入级、第一级放大、第二级放大均采用直接耦合方式。测试结果表明,该放大器与长波红外低输入阻抗光导探测器连接后能正常工作,总放大倍数大于1 万倍,3 dB 带宽大于4 kHz,等效输入电压噪声小于1.5 V,有效地解决了低阻抗光导探测器与高阻CMOS 电路的匹配问题。     

CMOS宽带互阻放大电路

介绍了用ＣＭＯＳ电流反馈放大器构成互阻放大器的基本原理。该互阻放大器具有宽频带、高增益、低功耗的特点,实用于Ｉ－Ｖ转换。文中给出设计指导思想,并给出模拟结果。     

2.5-V bipolar/CMOS circuits for 0.25-μm BiCMOS technology

An ECL circuit with an active pull-down device, operated from a CMOS supply voltage, is described as a high-speed digital circuit for a 0.25-μm BiCMOS technology. A pair of ECL/CMOS level converters with built-in logic capability is presented for effective intermixing of ECL with CMOS circuits. Using a 2.5-V supply and a reduced-swing BiNMOS buffer, the ECL circuit has reduced power dissipation, while still providing good speed. A design example shows the implementation of complex logic by emitter and collector dottings and the selective use of ECL circuits to achieve high performance     

一种新型低温漂带隙基准源的分析与设计

本文提出一种高电源抑制比、低温漂和版图面积较小的CMOS带隙基准电压源。该基准采用T型结构的核心电路来减小电路中用来产生负温度系数电流的电阻,进而减小电路的版图面积。电路采用SMIC 0.18μm CMOS工艺进行设计,设计的电路只采用一阶温度补偿,在Cadence Spectre环境下仿真结果表明在0-100℃的范围内温漂系数为1.4ppm/℃。     

基于新型启动电路的高电源抑制带隙基准源

设计了一种基于新型启动电路的高电源抑制(PSR)的带隙基准电压源。启动电路可以在300ns的时间内使电路进入工作状态,同时可在10ns的时间内完全关断电路。可控的启动电路增加了电路使用的灵活性。本基准电路基于新加坡Chartered0.25μmN阱CMOS工艺实现,已应用于射频调谐器当中。测试结果表明,基准电压源在低频段的电源抑制PSR≈123dB,高频段PSR>50dB,电路采用一阶温度补偿技术,在0～100℃的温度范围内输出基准电压的温度系数(TC)约为12ppm/℃。     

高电源抑制比的CMOS亚阈值多输出电压基准

基于工作在亚阈值区的MOS器件,运用CMOS电流模基准对CATA和PTAT电流求和的思想．提出一种具有低温漂系数、高电源抑制比（PSRR）的CMOS电压基准源,该电路可同时提供多个输出基准电压,且输出电压可调。该基准源基于CSMC0．5μm标准CMOS工艺,充分利用预调节电路并改进电流模基准核心电路。使整个电路的电源抑制比在低频时达到122dB,温度系数（TC）在0-100℃的温度范围内约7ppm／℃。     

Low-voltage high-performance voltage-mode and current-mode WTA circuits based on flipped voltage followers

A new low-voltage CMOS winner-take-all (WTA) circuit is presented. The proposed circuit exhibits a linear increase of complexity with the number of inputs at the rate of only three transistors per input and it is based on a modified version of the common source scheme. In this case, each input follower is enhanced by local shunt feedback to increase its gain and to reduce its output impedance. Simulations demonstrate the potential of the circuit to operate at very high speed, with high precision and with a supply voltage close to a transistor's threshold voltage. Experimental verification of the circuit using a 0.5-/spl mu/m CMOS technology is also provided.     

2.5 V CMOS circuit techniques for a 200 MHz superscalar RISCprocessor

Novel 2.5 V CMOS circuit techniques including a noise tolerant precharge (NTP) circuit and a leakless buffer circuit are applied to a floating point macrocell for a 200 MHz superscalar RISC processor. The NTP circuit has two advantages: high noise immunity and high speed. Floating point operations can be executed in a two cycle latency using the high speed NTP circuit. The leakless buffer circuit with NMOS transmission gate in 128 floating point registers makes possible both high integration and low power dissipation, since the circuit causes no leak current without precharging the number of read lines. The processor makes use of 0.3 μm CMOS technology with a 2.5 V power supply and four metal layers. The floating point macrocell has 380 thousand transistors and dissipates 350 mW at 200 MHz. The peak performance of the floating point macrocell is 400 MFLOPS     

CMOS源极跟随缓冲电路

提出用 CMOS源极跟随缓冲电路以较少的电路段数快速驱动大电容负载 .HSPICE模拟结果表明 ,在负载电容为基本栅电容的 10 0倍及 6 0 0 0倍时 ,CMOS源极跟随缓冲电路具有高于多段倒相器缓冲电路的负载驱动能力 ,且占有面积小 .从而较好地解决了高速驱动芯片内各种数据传输及外部负载的问题 .该电路结构简单 ,易于实现 ,且制作工艺与标准 CMOS工艺完全兼容 .     

A novel PWM control for a bi-directional full-bridge DC–DC converter with smooth conversion mode transitions

A novel CMOS integrated pulse-width modulation (PWM) control circuit allowing smooth transitions between conversion modes in full-bridge based bi-directional DC–DC converters operating at high switching frequencies is presented. The novel PWM control circuit is able to drive full-bridge based DC–DC converters performing step-down (i.e. buck) and step-up (i.e. boost) voltage conversion in both directions, thus allowing charging and discharging of the batteries in mobile systems. It provides smooth transitions between buck, buck-boost and boost modes. Additionally, the novel PWM control loop circuit uses a symmetrical triangular carrier, which overcomes the necessity of using an output phasing circuit previously required in PWM controllers based on sawtooth oscillators. The novel PWM control also enables to build bi-directional DC–DC converters operating at high switching frequencies (i.e. up to 10?MHz and above). Finally, the proposed PWM control circuit also allows the use of an average lossless inductor-current sensor for sensing the average load current even at very high switching frequencies. In this article, the proposed PWM control circuit is modelled and the integrated CMOS schematic is given. The corresponding theory is analysed and presented in detail. The circuit simulations realised in the Cadence Spectre software with a commercially available 0.18?µm mixed-signal CMOS technology from UMC are shown. The PWM control circuit was implemented in a monolithic integrated bi-directional CMOS DC–DC converter ASIC prototype. The fabricated prototype was tested experimentally and has shown performances in accordance with the theory.     

CMOS源极跟随缓冲电路

提出用CMOS源极跟随缓冲电路以较少的电路段数快速驱动大电容负载．HSPICE模拟结果表明,在负载电容为基本栅电容的100倍及6000倍时,CMOS源极跟随缓冲电路具有高于多段倒相器缓冲电路的负载驱动能力,且占有面积小．从而较好地解决了高速驱动芯片内各种数据传输及外部负载的问题．该电路结构简单,易于实现,且制作工艺与标准CMOS工艺完全兼容．     

双栅双应变沟道全耗尽SOI CMOS的瞬态特性分析

在提出双栅双应变沟道全耗尽SOl MOSFET新结构的基础上,模拟了沟道长度为25nm时基于新结构的CMOS瞬态特性.结果表明,单栅工作模式下,传统应变SiGe(或应变Si)器件的CMOS电路只能实现上升(或下降)时间的改善,而基于新结构的CMOS电路能同时实现上升和下降时间的缩短;双栅模式下,CMOS电路的上升和下降时间较单栅模式有了更进一步的改善,电路性能得以显著提高.     

Low voltage bandgap reference with closed loop curvature compensation

A new low-voltage CMOS bandgap reference (BGR) that achieves high temperature stability is proposed. It feeds back the output voltage to the curvature compensation circuit that constitutes a closed loop circuit to cancel the logarithmic term of voltage VBE. Meanwhile a low voltage amplifier with the 0.5μm low threshold technology is designed for the BGR. A high temperature stability BGR circuit is fabricated in the CSMC 0.5μm CMOS tech-nology. The measured result shows that the BGR can operate down to 1 V, while the temperature coefficient and line regulation are only 9 ppm/℃ and 1.2 mV/V, respectively.     

CMOS四象限乘法器的精确设计

本文提出了一种新型CMOS四象限乘法器,它基于MOSFET的电流-电压平方律模型,采用电压比例电路及四管单元乘法电路使乘法器能精确完成乘法运算。该乘法器的电路结构简单、精确度高及实现四象限相乘的特点,使之在CMOS通信集成电路,信号处理及运算电子系统中有广阔的应用前景。文中对电路的结构进行了详细分析和设计,并给出了HSPICE-Ⅱ模拟结果。     

A new DDCC based memristor emulator circuit and its applications

Memristor is a new passive circuit element. The interaction of the memristor with other circuit elements is important for designers. In this paper, new memristor emulator circuit is designed using DDCC (differential difference current conveyor) based on CMOS. It is realized that the proposed emulator causes less complexity compared to other designed emulator circuits. Compatibility of memristor with CMOSs and its operation ability at high frequencies are very important for circuit design based on memristor. The emulator based on CMOS can manage to provide these two fundamental properties successfully. In order to test the proposed emulator, it is connected to memristor with both ways, serial and parallel, than MC circuit is analyzed and results are shown at the end of the paper.     

A CMOS current-mode log(x) and log(1/x) functions generator

A novel Complementary Metal Oxide Semiconductor (CMOS) current-mode low-voltage and low-power controllable logarithmic function circuit is presented. The proposed design utilises one Operational Transconductance Amplifier (OTA) and two PMOS transistors biased in weak inversion region. The proposed design provides high dynamic range, controllable amplitude, high accuracy and is insensitive to temperature variations. The circuit operates on a ±0.6 V power supply and consumes 0.3 μW. The functionality of the proposed circuit was verified using HSPICE with 0.35 μm 2P4M CMOS process technology.