Modeling of tunneling currents through HfO/sub 2/ and (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ gate stacks

We present a physical modeling of tunneling currents through ultrathin high-/spl kappa/ gate stacks, which includes an ultrathin interface layer, both electron and hole quantization in the substrate and gate electrode, and energy band offsets between high-/spl kappa/ dielectrics and Si determined from high-resolution XPS. Excellent agreements between simulated and experimentally measured tunneling currents have been obtained for chemical vapor deposited and physical vapor deposited HfO/sub 2/ with and without NH/sub 3/-based interface layers, and ALD Al/sub 2/O/sub 3/ gate stacks with different EOT and bias polarities. This model is applied to more thermally stable (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ gate stacks in order to project their scalability for future CMOS applications.     

Lanthanide (Tb)-doped HfO/sub 2/ for high-density MIM capacitors

A high-density metal-insulator-metal (MIM) capacitor with a lanthanide-doped HfO/sub 2/ dielectric prepared by physical vapor deposition (PVD) is presented for the first time. A significant improvement was shown in both the voltage coefficient of capacitance (VCC) and the leakage current density of MIM capacitor, yet the high capacitance density of HfO/sub 2/ dielectrics was maintained by achieving the doping of Tb with an optimum concentration in HfO/sub 2/. This technique allows utilizing thinner dielectric film in MIM capacitors and achieving a capacitance density as high as 13.3 fF//spl mu/m/sup 2/ with leakage current and VCC values that fully meet requirements from year 2005 for radio frequency (RF) bypass capacitors applications.     

Metal-insulator-metal RF bypass capacitor using niobium oxide (Nb/sub 2/O/sub 5/) with HfO/sub 2//Al/sub 2/O/sub 3/ barriers

A high capacitance density (C/sub density/) metal-insulator-metal (MIM) capacitor with niobium pentoxide (Nb/sub 2/O/sub 5/) whose k value is higher than 40, is developed for integrated RF bypass or decoupling capacitor application. Nb/sub 2/O/sub 5/ MIM with HfO/sub 2//Al/sub 2/O/sub 3/ barriers delivers a high C/sub density/ of >17 fF//spl mu/m/sup 2/ with excellent RF properties, while maintaining comparable leakage current and reliability properties with other high-k dielectrics. The capacitance from the dielectric is shown to be stable up to 20 GHz, and resonant frequency of 4.2 GHz and Q of 50 (at 1 GHz) is demonstrated when the capacitor is integrated using Cu-BEOL process.     

High-performance MIM capacitor using ALD high-k HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectrics

For the first time, we successfully fabricated and demonstrated high performance metal-insulator-metal (MIM) capacitors with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectric using atomic layer deposition (ALD) technique. Our data indicates that the laminate MIM capacitor can provide high capacitance density of 12.8 fF//spl mu/m/sup 2/ from 10 kHz up to 20 GHz, very low leakage current of 3.2 /spl times/ 10/sup -8/ A/cm/sup 2/ at 3.3 V, small linear voltage coefficient of capacitance of 240 ppm/V together with quadratic one of 1830 ppm/V/sup 2/, temperature coefficient of capacitance of 182 ppm//spl deg/C, and high breakdown field of /spl sim/6 MV/cm as well as promising reliability. As a result, the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is a very promising candidate for next generation MIM capacitor for radio frequency and mixed signal integrated circuit applications.     

A high-density MIM capacitor (13 fF//spl mu/m/sup 2/) using ALD HfO/sub 2/ dielectrics

Metal-insulator-metal (MIM) capacitors with different HfO/sub 2/ thickness have been investigated. The results show that both the capacitance density and voltage coefficients of capacitance (VCCs) increase with decreasing HfO/sub 2/ thickness. In addition, it is found that the VCCs decrease logarithmically with increasing thickness. Furthermore, the MIM capacitor with 10-nm HfO/sub 2/ shows a record high capacitance density of 13 fF//spl mu/m/sup 2/ and a VCC of 607 ppm/V, which can meet the requirement of the International Technology Roadmap for Semiconductors. It can also provide a low leakage current of 5.95 /spl times/ 10/sup -8/A/cm/sup 2/ at room temperature at 1 V, low tangent values below 0.05, and a small frequency dependence. These results indicate that the devices are suitable for use in silicon integrated circuit applications.     

RF, DC, and reliability characteristics of ALD HfO/sub 2/-Al/sub 2/O/sub 3/ laminate MIM capacitors for Si RF IC applications

High-performance metal-insulator-metal capacitors using atomic layer-deposited HfO/sub 2/-Al/sub 2/O/sub 3/ laminate are fabricated and characterized for RF and mixed-signal applications. The laminate capacitor can offer high capacitance density (12.8 fF//spl mu/m/sup 2/) up to 20 GHz, low leakage current of 4.9/spl times/10/sup -8/ A/cm/sup 2/ at 2 V and 125/spl deg/C, and small linear voltage coefficient of capacitance of 211 ppm/V at 1 MHz, which can easily satisfy RF capacitor requirements for year 2007 according to the International Technology Roadmap for Semiconductors. In addition, effects of constant voltage stress and temperature on leakage current and voltage linearity are comprehensively investigated, and dependences of quadratic voltage coefficient of capacitance (/spl alpha/) on frequency and thickness are also demonstrated. Meanwhile, the underlying mechanisms are also discussed.     

Improvement of voltage linearity in high-/spl kappa/ MIM capacitors using HfO/sub 2/-SiO/sub 2/ stacked dielectric

It is demonstrated that the voltage coefficients of capacitance (VCC) in high-/spl kappa/ metal-insulator-metal (MIM) capacitors can be actively engineered and voltage linearity can be significantly improved maintaining high capacitance density, by using a stacked insulator structure of high-/spl kappa/ and SiO/sub 2/ dielectrics. A MIM capacitor with capacitance density of 6 fF/spl mu/m/sup 2/ and quadratic VCC of only 14 ppm/V/sup 2/ has been demonstrated together with excellent frequency and temperature dependence (temperature coefficients of capacitance of 54 ppm /spl deg/C) as well as low leakage current of less than 10 nA/cm/sup 2/ up to 4 V at 125 /spl deg/C.     

MOS capacitors on epitaxial Ge-Si/sub 1-x/Ge/sub x/ with high-/spl kappa/ dielectrics using RPCVD

We report the successful growth of MOS capacitor stacks with low temperature strained epitaxial Ge or Si/sub 1-x/Ge/sub x/(x=0.9) layer directly on Si substrates, and with HfO/sub 2/(EOT=9.7 /spl Aring/) as high-/spl kappa/ dielectrics, both using a novel remote plasma-assisted chemical vapor deposition technique. These novel MOS capacitors, which were fabricated entirely at or below 400/spl deg/C, exhibit normal capacitance-voltage and current-voltage characteristics.     

Very high density RF MIM capacitors (17 fF//spl mu/m/sup 2/) using high-/spl kappa/ Al/sub 2/O/sub 3/ doped Ta/sub 2/O/sub 5/ dielectrics

Using high-/spl kappa/ Al/sub 2/O/sub 3/ doped Ta/sub 2/O/sub 5/ dielectric, we have obtained record high MIM capacitance density of 17 fF//spl mu/m/sup 2/ at 100 kHz, small 5% capacitance reduction to RF frequency range, and low leakage current density of 8.9/spl times/10/sup -7/ A/cm/sup 2/. In combination of both high capacitor density and low leakage current density, a very low leakage current of 5.2/spl times/10/sup -12/ A is calculated for a typical large 10 pF capacitor used in RF IC that is even smaller than that of a deep sub-/spl mu/m MOSFET. This very high capacitance density with good MIM capacitor characteristics can significantly reduce the chip size of RF ICs.     

Evidence and understanding of ALD HfO/sub 2/-Al/sub 2/O/sub 3/ laminate MIM capacitors outperforming sandwich counterparts

Metal-insulator-metal capacitors with atomic-layer-deposited HfO/sub 2/-Al/sub 2/O/sub 3/ laminated and sandwiched dielectrics have been compared, for the first time, for analog circuit applications. The experimental results indicate that significant improvements can be obtained using the laminated dielectrics, including an extremely low leakage current of 1/spl times/10/sup -9/ A/cm/sup 2/ at 3.3V and 125/spl deg/C, a high breakdown electric field of /spl sim/3.3MV/cm at 125/spl deg/C, good polarity-independent electrical characteristics, while retaining relatively high capacitance density of 3.13 fF//spl mu/m/sup 2/ as well as voltage coefficients of capacitance as low as -80 ppm/V and 100 ppm/V/sup 2/ at 100 kHz. The underlying mechanism is likely due to alternate insertions of Al/sub 2/O/sub 3/ layers that reduce the thickness of each HfO/sub 2/ layer, hereby efficiently inhibiting HfO/sub 2/ crystallization, and blocking extensions of grain boundary channels from top to bottom as well as to achieve good interfacial quality.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-K dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-K dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/ A(2-5 /spl times/ 10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8 /spl times/ 10/sup 17/ cm/sup -3/ eV/sup -1/ to 1, 3 /spl times/ 10/sup 19/ cm/sup -3/ eV/sup -1/ somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-K/gate stacks, relative comparison among them and to the Si-SiO/sub 2/ system.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-/spl kappa/ dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-/spl kappa/ dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/A(2-5/spl times/10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8/spl times/10/sup 17/ cm/sup -3/eV/sup -1/ to 1.3/spl times/10/sup 19/ cm/sup -3/eV/sup -1/, somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-/spl kappa//gate stacks, relative comparison among them and to the Si--SiO/sub 2/ system.     

Integrated high-/spl kappa/ (/spl kappa/ /spl sim/19) MIM capacitor with Cu/low-/spl kappa/ interconnects for RF application

We demonstrate a high-performance metal-high /spl kappa/ insulator-metal (MIM) capacitor integrated with a Cu/low-/spl kappa/ backend interconnection. The high-/spl kappa/ used was laminated HfO/sub 2/-Al/sub 2/O/sub 3/ with effective /spl kappa/ /spl sim/19 and the low-/spl kappa/ dielectric used was Black Diamond with /spl kappa/ /spl sim/2.9. The MIM capacitor (/spl sim/13.4 fF//spl mu/m/sup 2/) achieved a Q-factor /spl sim/53 at 2.5 GHz and 11.7 pF. The resonant frequency f/sub r/ was 21% higher in comparison to an equivalently integrated Si/sub 3/N/sub 4/-MIM capacitor (/spl sim/0.93 fF//spl mu/m/sup 2/) having similar capacitance 11.2 pF. The impacts of high-/spl kappa/ insulator and low-/spl kappa/ interconnect dielectric on the mechanism for resonant frequency improvement are distinguished using equivalent circuit analysis. This letter suggests that integrated high-/spl kappa/ MIM could be a promising alternative capacitor structure for future high-performance RF applications.     

High-density MIM capacitors using AlTaO/sub x/ dielectrics

The authors have obtained good MIM capacitor integrity of high-capacitance density of 10 fF//spl mu/m/sup 2/ using high-/spl kappa/ AlTaO/sub x/ fabricated at 400/spl deg/C. In addition, small voltage dependence of capacitance of <600 ppm (quadratic voltage coefficient of only 130 ppm/V/sup 2/) is obtained at 1 GHz using their mathematical derivation from measured high-frequency S parameters. These good results ensure the high-/spl kappa/ AlTaO/sub x/ MIM capacitor technology is useful for high-precision circuits operated at the RF frequency regime.     

A novel high-/spl kappa/ SONOS memory using TaN/Al/sub 2/O/sub 3//Ta/sub 2/O/sub 5//HfO/sub 2//Si structure for fast speed and long retention operation

A novel high-/spl kappa/ silicon-oxide-nitride-oxide-silicon (SONOS)-type memory using TaN/Al/sub 2/O/sub 3//Ta/sub 2/O/sub 5//HfO/sub 2//Si (MATHS) structure is reported for the first time. Such MATHS devices can keep the advantages of our previously reported TaN/HfO/sub 2//Ta/sub 2/O/sub 5//HfO/sub 2//Si device structure to obtain a better tradeoff between long retention and fast programming as compared to traditional SONOS devices. While at the same time by replacing hafnium oxide (HfO/sub 2/) with aluminum oxide (Al/sub 2/O/sub 3/) for the top blocking layer, better blocking efficiency can be achieved due to Al/sub 2/O/sub 3/'s much larger barrier height, resulting in greatly improved memory window and faster programming. The fabricated devices exhibit a fast program and erase speed, excellent ten-year retention and superior endurance up to 10/sup 5/ stress cycles at a tunnel oxide of only 9.5 /spl Aring/ equivalent oxide thickness.     

Path to the measurement of positive gain on the 1315-nm transition of atomic iodine pumped by O/sub 2/(a/sup 1//spl Delta/) produced in an electric discharge

Laser action at 1315 nm on the I(/sup 2/P/sub 1/2/)/spl rarr/I(/sup 2/P/sub 3/2/) transition of atomic iodine is conventionally obtained by a near-resonant energy transfer from O/sub 2/(a/sup 1//spl Delta/) which is produced using wet-solution chemistry. The system difficulties of chemically producing O/sub 2/(a/sup 1//spl Delta/) have motivated investigations into gas phase methods to produce O/sub 2/(a/sup 1//spl Delta/) using low-pressure electric discharges. We report on the path that led to the measurement of positive gain on the 1315-nm transition of atomic iodine where the O/sub 2/(a/sup 1//spl Delta/) was produced in a flowing electric discharge. Atomic oxygen was found to play both positive and deleterious roles in this system, and as such the excess atomic oxygen was scavenged by NO/sub 2/ to minimize the deleterious effects. The discharge production of O/sub 2/(a/sup 1//spl Delta/) was enhanced by the addition of a small proportion of NO to lower the ionization threshold of the gas mixture. The electric discharge was upstream of a continuously flowing supersonic cavity, which was employed to lower the temperature of the flow and shift the equilibrium of atomic iodine more in favor of the I(/sup 2/P/sub 1/2/) state. A tunable diode laser system capable of scanning the entire line shape of the (3,4) hyperfine transition of iodine provided the gain measurements.     

PVD HfO/sub 2/ for high-precision MIM capacitor applications

Metal-insulator-metal (MIM) capacitors are fabricated using sputtered HfO/sub 2/ with Ta and TaN for top and bottom electrodes, respectively. High-capacitance densities from 4.7 to 8.1 fF//spl mu/m/sup 2/ have been achieved while maintaining the leakage current densities around 1 /spl times/ 10/sup -8/ A/cm/sup 2/ within the normal circuit bias conditions. A guideline for the insulator thickness and its dielectric constant has been obtained by analyzing the tradeoff between the linearity coefficient and the capacitance density.     

High breakdown voltage (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P/InGaAs quasi-enhancement-mode pHEMT with field-plate technology

A high breakdown voltage and a high turn-on voltage (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P/InGaAs quasi-enhancement-mode (E-mode) pseudomorphic HEMT (pHEMTs) with field-plate (FP) process is reported for the first time. Between gate and drain terminal, the transistor has a FP metal of 1 /spl mu/m, which is connected to a source terminal. The fabricated 0.5/spl times/150 /spl mu/m/sup 2/ device can be operated with gate voltage up to 1.6 V owing to its high Schottky turn-on voltage (V/sub ON/=0.85 V), which corresponds to a high drain-to-source current (I/sub ds/) of 420 mA/mm when drain-to-source voltage (V/sub ds/) is 3.5 V. By adopting the FP technology and large barrier height (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P layer design, the device achieved a high breakdown voltage of -47 V. The measured maximum transconductance, current gain cutoff frequency and maximum oscillation frequency are 370 mS/mm, 22 GHz , and 85 GHz, respectively. Under 5.2-GHz operation, a 15.2 dBm (220 mW/mm) and a 17.8 dBm (405 mW/mm) saturated output power can be achieved when drain voltage are 3.5 and 20 V. These characteristics demonstrate that the field-plated (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P E-mode pHEMTs have great potential for microwave power device applications.     

HfO/sub 2/ MIS capacitor with copper gate electrode

Metal-insulator-semiconductor capacitors were fabricated using atomic vapor deposition HfO/sub 2/ dielectric with sputtered copper (Cu) and aluminum (Al) gate electrodes. The counterparts with SiO/sub 2/ dielectric were also fabricated for comparison. Bias-temperature stress and charge-to-breakdown (Q/sub BD/) test were conducted to examine the stability and reliability of these capacitors. In contrast with the high Cu drift rate in an SiO/sub 2/ dielectric, Cu in contact with HfO/sub 2/ seems to be very stable. The HfO/sub 2/ capacitors with a Cu-gate also depict higher capacitance without showing any reliability degradation, compared to the Al-gate counterparts. These results indicate that HfO/sub 2/ with its considerably high density of 9.68 g/cm/sup 3/ is acting as a good barrier to Cu diffusion, and it thus appears feasible to integrate Cu metal with the post-gate-dielectric ultralarge-scale integration manufacturing processes.     

High-performance Pt/SrBi/sub 2/Ta/sub 2/O/sub 9//HfO/sub 2//Si structure for nondestructive readout memory

Metal-ferroelectric-insulator-semiconductor (MFIS) capacitors with 390-nm-thick SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT) ferroelectric film and 8-nm-thick hafnium oxide (HfO/sub 2/) layer on silicon substrate have been fabricated and characterized. It is demonstrated for the first time that the MFIS stack exhibits a large memory window of around 1.08 V at an operation voltage of 3.5 V. Moreover, the MFIS memory structure suffers only 18% degradation in the memory window after 10/sup 9/ switching cycles. The excellent performance is attributed to the formation of well-crystallized SBT perovskite thin film on top of the HfO/sub 2/ buffer layer, as evidenced by the distinctive sharp peaks in X-ray diffraction (XRD) spectra. In addition to its relatively high /spl kappa/ value, HfO/sub 2/ also serves as a good seed layer for SBT crystallization, making the proposed Pt/SrBi/sub 2/Ta/sub 2/O/sub 9//HfO/sub 2//Si structure ideally suitable for low-voltage and high-performance ferroelectric memories.