A comprehensive study of hot carrier stress-induced drain leakagecurrent degradation in thin-oxide n-MOSFETs

The mechanisms and characteristics of hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFETs are investigated. Both interface trap and oxide charge effects are analyzed. Various drain leakage current components at zero V_gs such as drain-to source subthreshold leakage, band-to-band tunneling current, and interface trap-induced leakage are taken into account. The trap-assisted drain leakage mechanisms include charge sequential tunneling current, thermionic-field emission current, and Shockley-Read-Hall generation current. The dependence of drain leakage current on supply voltage, temperature, and oxide thickness is characterized. Our result shows that the trap-assisted leakage may become a dominant drain leakage mechanism as supply voltage is reduced. In addition, a strong oxide thickness dependence of drain leakage degradation is observed. In ultra-thin gate oxide (30 Å) n-MOSFETs, drain leakage current degradation is attributed mostly to interface trap creation, while in thicker oxide (53 Å) devices, the drain leakage current exhibits two-stage degradation, a power law degradation rate in the initial stage due to interface trap generation, followed by an accelerated degradation rate in the second stage caused by oxide charge creation     

A study of the effects of tunneling currents and reliability of sub-2 nm gate oxides on scaled n-MOSFETs

This work examined various components of direct gate tunneling currents and analyzed reliability of ultrathin gate oxides (1.4–2 nm) in scaled n-metal-oxide-semiconductor field effective transistor (MOSFETs). Direct gate tunneling current components were studied both experimentally and theoretically. In addition to gate tunneling currents, oxide reliability was investigated as well. Constant voltage stressing was applied to the gate oxides. The oxide breakdown behaviors were observed and their effects on device performance were studied. The ultrathin oxides in scaled n-MOSFETs used in this study showed distinct breakdown behavior and strong location dependence. No “soft” breakdown was seen for 1.5 nm oxide with small area, implying the importance of using small and more realistic MOS devices for ultrathin oxide reliability study instead of using large area devices. Higher frequency of oxide breakdowns in the source/drain extension to the gate overlap region was then observed in the channel region. Possible explanations to the observed breakdown behaviors were proposed based on the quantum mechanical effects and point-contact model for electron conduction in the oxide during the breakdown. It was concluded that the source/drain extension to the gate overlap regions have strong effects on the device performance in terms of both gate tunneling currents and oxide reliability.     

Low frequency noise in nMOSFETs with subnanometer EOT hafnium-based gate dielectrics

This paper focuses on the noise behavior of nMOSFETs with high-k gate dielectrics (SiON/HfO₂) with an equivalent oxide thickness of 0.92 nm and using metal (TiN/TaN) as gate material. From the linear dependence of the normalized drain noise on the gate voltage overdrive we conclude that the 1/f noise is dictated by mobility fluctuations. This behavior is mainly ascribed to the reduced mobility due to the low interfacial thickness of 0.4 nm and the Hf-related defects. The gate current is more sensitive to RTS noise with respect to the drain current noise. Cross-correlation measurements between drain and gate noise are used as a tool for discriminating between noise mechanisms which generate different fluctuation levels at the gate and drain terminal.     

热载流子应力下n-MOSFET线性漏电流的退化

研究了不同沟道和栅氧化层厚度的n-M O S器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响。实验发现衬底正偏压对沟长0.135μm,栅氧化层厚度2.5 nm器件的线性漏电流退化的影响比沟长0.25μm,栅氧化层厚度5 nm器件更强。分析结果表明,随着器件沟长继续缩短和栅氧化层减薄,由于衬底正偏置导致的阈值电压减小、增强的寄生NPN晶体管效应、沟道热电子与碰撞电离空穴复合所产生的高能光子以及热电子直接隧穿超薄栅氧化层产生的高能光子可能打断S i-S iO2界面的弱键产生界面陷阱,加速n-M O S器件线性漏电流的退化。     

Hysteresis behavior in 85-nm channel length vertical n-MOSFETsgrown by MBE

Vertical n-MOSFETs with channel lengths of 85 nm have been grown by MBE. For drain-to-source voltages V_DS>3.3 V, these transistors exhibit hysteresis behavior similar to the reported behavior of fully depleted SOI-MOSFETs. Our results also show a gate voltage controlled turn-off of the drain current when the transistor is operating in the hysteresis mode. We have analyzed this behavior in vertical n-MOSFETs using 2-D device simulation and our results show a threshold value for the hole concentration across the source-channel junction which is required for the forward biasing of this junction. For a transistor operating in the hysteresis mode, we show that the potential barrier height for electron injection across the source-channel junction increases for increasing negative gate voltages during retrace. This results in a gate controlled turn-off of the drain current for SOI and vertical n-MOSFETs operating in the regenerative mode     

Low frequency noise in thin gate oxide MOSFETs

Low frequency, 1/f, noise of the drain current, I_D, fluctuations was measured on a series of Si MOSFETs with the gate oxide thickness, t_ox, varied from 25 to 40 Å by steps of 5 Å. The salient point of this work is a demonstration that, at sufficiently low I_D intensities, a mean low noise level in the MOSFETs is reduced as the gate oxide becomes thinner. This is explained assuming that the noise originates from the electron capture/release on Si/SiO₂ interface/border traps. The flat band voltage fluctuations, observable as noise, are linked then to the oxide charge fluctuations by a factor, that is inversely proportional to the gate capacitance, C_ox, and thus proportional to t_ox. At higher I_D, the results are more complicated, as the access resistance noise is also involved. We provide an interpretation of the ensemble of the data and show that the noise analysis can furnish quantitative estimates of several device characteristics. Device degradation and its consequences for the low frequency noise at higher current levels are also discussed.     

Oxide thickness dependent compact model of channel noise for E-mode AlGaN/GaN MOS-HEMT

In this paper, a compact channel noise model for gate recessed enhancement mode GaN based MOS-HEMT which is valid for all regions of operation is proposed. The compact noise model consists of high frequency thermal noise and low frequency flicker noise. The drain current, which is one of the most important parameters for compact noise model is developed by incorporating interface and oxide traps, mobility degradation due to vertical electric field, velocity saturation effect and self-heating effect. The flicker noise model is derived by considering mobility and carrier fluctuation due to traps present in both oxide and interface layer. The thermal noise and flicker noise models are validated by comparing the results with TCAD simulation and experimental results from literature respectively. Effect of thermal and flicker noise power spectral density (PSD) variation with different oxide thickness has also been analyzed.     

High-frequency noise of the junction field-effect transistor

Based on Geurst's treatment of the high-frequency value of the admittances of the junction field-effect transistor, the high-frequency noise of the device has been computed, assuming that the noise source is of thermal origin. By applying an appropriate series expansion of the current it is possible to express the noise of the drain and gate current in terms of known quantities, as steady-state transconductance, gate capacitance, and frequency. At low frequencies the noise spectrum of the drain current is independent of the frequency and is much larger than the noise of the gate current; however, at high frequencies the noise spectra of the gate and drain current both vary by ω²and are of the same order of magnitude.     

A novel 4H-SiC MESFET by lateral insulator region to improve the DC and RF characteristics

In this paper, a novel recessed gate metal–semiconductor field-effect transistor (RG-MESFET) is presented by modifying the depletion region and the electric field. The proposed structure improves the breakdown voltage, drain current and high frequency characteristics by embedding a lateral insulator region between drain and gate while is placed laterally into the metal gate and a silicon well exactly under the insulator region. We called this new structure as modified recess gate MESFET (MRG-MESFET). The radio frequency and direct current (DC) characteristics of the proposed structure is studied using numerical simulations and compared with a conventional MESFET (C-MESFET). The breakdown voltage, drain current DC transconductance and maximum power density of the proposed structure increase by 27%, 16.5%, 15% and 48%, respectively, relative to the C-MESFET. Also, the gate-source capacitance and the minimum noise figure of the proposed structure improve relative to the C-MESFET. The proposed structure can be used for high breakdown voltage, high saturation drain current, high DC transconductance, high power, high frequency, and low noise applications.     

MOSFET's in the 0°K approximation: Static characteristics of MOSFET's in the 0°K approximation

The static electrical characteristics below current saturation of MOSFET's with degenerate source and drain regions are calculated for operation at 0°K. The expression for current takes the same form as at room temperature although the flat-band voltage and the voltage across the depletion region at threshold are altered slightly. Potential hills occur in the channel if the gate does not overlap source and drain or if the oxide thickness is increased in the overlap regions. Although these barriers do not affect operation appreciably at room temperature, at 0°K a finite drain voltage (source-drain threshold voltage) is required to initiate conduction. This threshold voltage is included in the theory and the theory is compared with experimental results on p-channel enhancement mode MOSFET's at 4·2°K using hole mobility in the channel as a matching parameter. The channel hole mobility (assumed constant along the channel) is found to be relatively independent of gate voltage but to increase with increasing (negative) drain voltage. Values ranging between 500 and 1000 cm²/V-sec are deduced for drain voltages ranging from ?1·2 V to ?7 V. This compares to channel hole mobility values of 200–300 cm²/V-sec at room temperature. It is found that the channel width is on the order of 30–50 Å—appreciably less than that at room temperature.     

Partially depleted SOI MOSFETs under uniaxial tensile strain

The effects of tensile uniaxial strain on the DC performance of partially-depleted silicon-on-insulator n and p-channel MOSFETs as a function of orientation and gate length are reported. The drain current of the n-MOSFETs increases for both longitudinal and transverse strain orientations with respect to the current flow direction. In the n-MOSFET, longitudinal strain provides greater enhancement than transverse strain. In contrast, for p-MOSFETs, longitudinal strain decreases the current while transverse strain increases the drain current. The magnitude of the fractional change in drain current decreases as gate length is reduced from 20 to 0.35 /spl mu/m. These phenomena are consistent with those of bulk silicon MOSFETs and are shown to be qualitatively correlated with the piezoresistance coefficients of the Si inversion layer. Analysis of the linear drain current versus gate voltage characteristics shows that the threshold voltage is independent of strain while the change in drain current tracks with the change in effective electron and hole mobility. Closer examination shows that as the gate length is reduced from 20 to 0.35 /spl mu/m, the relative increase in low-field electron and hole mobility is constant for transverse strain and generally decreases with gate length for longitudinal strain.     

Low frequency noise sources in InAlAs/InGaAs MODFETs

Detailed analysis of the 1/f low-frequency noise (LFN) in In/sub 0.52/Al/sub 0.48/As/InGaAs MODFET structures is performed, for low drain bias (below pinch-off voltage), in order to identify the physical origin and the location of the noise sources responsible for drain current fluctuations in the frequency range 0.1 Hz-10/sup 5/ Hz. Experimental data were analyzed with the support of a general modeling of the 1/f LFN induced by traps distributed within the different layers and interfaces which constitute the heterostructures. Comparative noise measurements are performed on a variety of structures with different barrier (InAIAs, InP) and different channel (InGaAs lattice matched to InP, strained InGaAs, InP) materials. It is concluded that the dominant low frequency noise sources of InAlAs/InGaAs MODFET transistors in the ON state are generated by deep traps distributed within the "bulk" InAlAs barrier and buffer layers. For reverse gate bias, the gate current appears to be the dominant contribution to the channel LFN, whereas both the gate current and the drain and source ohmic contacts are the dominant sources of noise when the device is biased strongly in the ON state. Heterojunction FET's on InP substrate with InP barrier and buffer layers show significantly lower LFN and appear to be more suitable for applications such as nonlinear circuits that have noise upconversion.     

Dynamic hot-carrier induced degradation in n-channel polysilicon thin-film transistors

The effects of hot-carriers under dynamic stress on the transfer characteristics and the noise performance of n-channel polysilicon thin-film transistors are analysed. The observed decrease in the on-state current is directly related to the mobility of a damaged region extended over a length of about 0.53 μm beside the drain, which is evaluated through analysis of the transfer characteristics at low drain voltage. The mobility degradation in the damaged region is due to the formation of traps located near the polysilicon/gate oxide interface as evidenced by the 1/f noise measurements.     

Analytical bias dependent noise model for InP HEMT's

A practical device model for both high frequency small signal and noise behavior of InP-HEMT's depending on both gate and drain voltage has been developed. The model is based on the two-piece linear approximation using charge control and saturation velocity models. Combining large signal model and analytical expressions for the noise source parameter P, R, and C, an analytical bias-dependent noise model can be obtained. For implementation into high frequency simulation software, the exact calculated bias dependence was mathematically fitted by elementary functions. It could be shown that lowest noise is observed when the drain current for maximum gain is reduced to a third while the drain voltage is reduced to the start of the saturation region V_ds =0.6 V. Modeling scaling effects of the noise behavior shows that lowest noise is observed for a gate width of 1×40 μm. Multi-finger layouts are preferable for gate widths above 70 μm. Furthermore it is shown, that the optimum width of each finger decreases with the number of fingers     

Stress induced gate–drain leakage current in ultra-thin gate oxide

Ultra-thin gate oxide reliability, in large area MOSFETs, can be monitored by measuring the gate current when the substrate is depleted. When the channel length is scaled down, the tunneling current associated with the source/drain extension region (SDE) to the gate–overlap regions can dominate the gate current. In N-MOSFETs, as a function of the negative gate voltage two components of the gate–drain leakage current should be considered, the first for V_FB < V_G < 0 V and the second for V_G < V_FB. These components are studied in this work before and after voltage stresses. The aim of this work is to see whether this gate–drain current can be used to monitor the oxide degradation above or near the source and/or drain extension region in N-MOSFETs. It is important because the most serious circuit-killing breakdown occurs above or near the drain (or source) extension region. Finally, we show that it is necessary, before explaining the gate LVSILC curves obtained after stresses on short-channel devices, to verify which is the dominate current at low voltage.     

Device reliability study of AlGaN/GaN high electron mobility transistors under high gate and channel electric fields via low frequency noise spectroscopy

A set of different short term stress conditions are applied to AlGaN/GaN high electron mobility transistors and changes in the electronic behaviour of the gate stack and channel region are investigated by simultaneous gate and drain current low frequency noise measurements. Permanent degradation of gate current noise is observed during high gate reverse bias stress which is linked to defect creation in the gate edges. In the channel region a permanent degradation of drain noise is observed after a relatively high drain voltage stress in the ON-state. This is attributed to an increase in the trap density at the AlGaN/GaN interface under the gated part of the channel. It was found that self-heating alone does not cause any permanent degradation to the channel or gate stack. OFF-state stress also does not affect the gate stack or the channel.     

Random telegraph noise and leakage current in smart power technology DMOS devices

Random telegraph signal (RTS) noise, analyzed in time and frequency domains, and leakage current are studied in smart power technology double-diffused metal oxide semiconductor (DMOS) field effect transistors. The RTS noise is strongly correlated with the presence of an excess leakage current in the device. The observed drain current (gate bias) dependencies of relative (absolute) RTS amplitude and gate voltage dependence of RTS mean pulse widths suggest that the RTS noise sources are located under the gate and in the drain-body region. A model, where the multicell DMOS structure is considered as parallel connection of submicron MOSFETs, is proposed to account for the results.     

A new lifetime prediction method for hot-carrier degradation in n-MOSFETs with ultrathin gate oxides under Vg=Vd

Hot-carrier degradation of n-MOSFETs at high gate voltages (V_g=V_d) is examined. A new lifetime prediction method is developed based on the universal power law between the degradation of saturated drain current (dI_dsat) and the product of the injected charge fluence times the gate current, which is independent of gate or drain voltages. This method is applied to 4 and 5 nm n-MOSFETs and lifetimes are estimated under their operation conditions. It is applicable to n-MOSFETs with ultrathin gate oxides.     

New observation and the modeling of gate and drain currents inoff-state P-MOSFET's

The work reports new observations concerning the gate and drain currents measured at off-state conditions in buried-type p-channel LDD MOSFET devices. Detailed investigation of the observed phenomena reveals that 1) the drain current can be separated into two distinct components: band-to-band tunneling in the gate-to-drain overlap region and collection of holes generated via impact ionization by electrons inside the oxide; and 2) the gate current can be separated into two distinct components: the hot electron injection into the oxide and the Fowler-Nordheim electron tunneling through the oxide, At low negative drain voltage, the dominant component of the drain current is the hole generation inside the oxide. At high negative drain voltage, the drain current is essentially due to band-to-band tunneling, and it is correlated with the hot-electron injection-induced gate current     

On the time-dependent degradation of LDD n-MOSFETs under hot-carrier stress

A unified model for hot-carrier-induced degradation in LDD n-MOSFETs is presented. A novel oxide spacer charge pumping method enables interface trap generation in the spacer and overlap/channel regions to be distinctly separated. An excellent correlation between trap generation in the spacer region and linear drain current degradation at high gate voltage is observed. Moreover, trap generation in the overlap/channel region is found to correlate well with linear drain current degradation at low gate voltage. The results point unambiguously to a two-mechanism degradation model involving drain resistance increase by trap generation in the spacer region, and carrier mobility reduction by trap generation in the overlap/channel region. The combined effect of a time-independent lateral electron temperature profile and a finite density of interface trap precursors within the LDD region leads to a self-limiting degradation behavior. This insight forms the basis of a time-dependent trap generation model, which indicates the existence of a single degradation curve. The fact that the degradation curves at different stress drain voltages fall onto a time-scaled version of the single degradation curve provides strong support for the model. This also offers a straightforward and yet accurate means by which the hot-carrier lifetime corresponding to a specific failure criterion may be extracted. Finally, a power-law relationship between hot-carrier lifetime and substrate current is also observed for the LDD devices, thus preserving the physical essence based on which earlier lifetime models for conventional drain devices are established.