Linear voltage-to-current converters with current reuse technique

This paper proposes a linear voltage-to-cur-rent converter with current reuse technique to reduce circuit power consumption without deteriorating its linearity and bandwidth. The proposed circuit is designed using 0.18???m CMOS process parameters from TSMC. Simulation results show that the total harmonic distortion (THD) of the proposed circuit with a 2.5-V input amplitude is less than 1% for input frequency up to 200?MHz under a 1.8-V supply voltage. The total current consumption is 10.8?mA.     

An intelligent multiplexer/driver integrated circuit for animplantable multichannel blood flowmeter

A custom CMOS integrated circuit that extends the current implantable single-channel ultrasonic pulse Doppler blood flowmeter to three channels is discussed. By operating on a single 2.7-V battery with three existing custom bipolar ICs, the integrated circuit serves as an RF command receiver, controls the channel-multiplexing sequence, and multiplexes the piezoelectric transducers. A round-trip channel isolation of 38 dB is achieved with a novel transducer-multiplexing circuit that employs three on-chip power transistors for 6-MHz transducer excitation. Each power transistor is capable of switching a current of 200 mA with an on-resistance of 3 Ω and transition times of 10 ns. The power consumption in the implanted portion of the three-channel flowmeter is only 0.8 mW higher than the 30 mW in the single-channel flowmeter     

A 1-V operating 256-kb full-CMOS SRAM

A 1-V operating 256-kb full-CMOS SRAM to be used in 1.5-V battery-based applications is presented. A reference word line and address transition detection (ATD) are used as timing control techniques to achieve adjustable timing of critical signals with a 1.5-V battery. The key circuit of the pulse sequence block is the ATD pulse generator circuit. The authors use a newly modified Schmitt trigger delay circuit. To reduce supply line noise in the chip, they needed to lower the peak of bit-line charge-up current. This was done by applying a divided word-line technique and a newly adopted staggered bit-line equalizing pulse technique. The design used a single-polysilicon and double-aluminum process with a full-CMOS memory cell of 8.5 μm×12.8 μm. The chip size is 6.0 mm×9.0 mm     

Two-dimensional power-line selection scheme for lowsubthreshold-current multi-gigabit DRAM's

A two-dimensional power-line selection scheme for an iterative CMOS circuit block is proposed to reduce the subthreshold current. In this scheme, a block is divided into sub-blocks in a two-dimensional arrangement and selectively energized by two-dimensional power-line selection. It is shown to be suitable for dual word-line structure, particularly because of its single sub-word line activation. This scheme achieves a very large reduction of active current to one sixteenth, from 116 mA to 22 mA for a 1-V 16-Gb DRAM with dual word-line structure, while maintaining a speed comparable to existing multi-megabit DRAM's. The proposed scheme is promising for reducing the active power of future multi-gigabit DRAM's     

A monolithic 70-V subscriber line interface circuit

The design of a new monolithic 70-V BIMOS line interface circuit (BLIC), developed as a direct interface to the subscriber line, is described. This is the basic analog segment of a new subscriber-line interface circuit (SLIC). The LSI chip has been designed using a 70-V BIMOS process, combining high- and low-voltage bipolar transistors (70 and 15 V) with CMOS (15-V) transistors all using the same junction depths. The LSI chip meets stringent requirements on several specifications and performs ten basic functions.     

A broadband high-voltage SLIC for a splitter- and transformerlesscombined ADSL-Lite/POTS linecard

A monolithic broadband subscriber line interface circuit (B-SLIC) has been integrated in the smart power technology SPT170B, combining the functionality of an analog 150-V ringing SLIC with that of a line driver for ADSL-Lite data signals. Thus the B-SLIC is the key circuit for the realization of a very compact integrated voice data (IVD) central office linecard that neither needs analog filters (“POTS-splitter”) nor transformers or relays. In spite of the fundamental voltage/frequency tradeoff, the B-SLIC is able to feed high dc or ring voltages to the line, while simultaneously acting as voice and data transceiver. Total harmonic distortion values are below -60 dB even for a high 25-V_pp/550-kHz sine wave signal into a 200 Ω load; ADSL-signal-based multitone power ratio (MTPR) measurements also yield results better than 60 dB. Power dissipation in simultaneous voice and data operation is about 2.2 W     

A CMOS Readout Circuit for SOI Resonant Accelerometer With 4-$mu rm g$ Bias Stability and 20-$ murm g/sqrt{{hbox{Hz}}}$ Resolution

A fully differential CMOS readout circuit for SOI resonant accelerometer is reported. The readout circuit is essentially an oscillator, consisting of an oscillator and a low noise automatic amplitude control (AAC) loop. A differential sense resonator is proposed to facilitate fully differential circuit topology and improves the SNR under a 3.3-V supply. A second-order AAC loop filter and a novel chopper stabilized rectifier are employed in the AAC loop to remove the noises, in particular, the 1/f noise, and to minimize the phase noise caused by the amplitude stiffening effect. The strong driving feedthrough is avoided by separating the drive and sense operation in the time domain, while using the same electrodes. The complete resonant accelerometer operates under a 3.3-V supply and achieves 140-Hz/g scaling factor, 20 mug/radicHz resolution and 4 mug bias stability. The readout circuit draws 7 mA under 3.3-V supply.     

Design of high speed LVDS transceiver ICs

The design of low-power LVDS(low voltage differential signaling) transceiver ICs is presented.The LVDS transmitter integrates a common-mode feedback control on chip,while a specially designed pre-charge circuit is proposed to improve the speed of the circuit,making the highest data rate up to 622 Mb/s.For the LVDS receiver design, the performance degradation issues are solved when handling the large input common mode voltages of the conventional LVDS receivers.In addition,the LVDS receiver also supports ...     

An output-capacitor-free low-dropout regulator with subthreshold slew-rate enhancement technique

A low power output-capacitor-free low-dropout (LDO) regulator, with subthreshold slew-rate enhancement technique, has been proposed and simulated using a standard 0.18 μm CMOS process in this paper. By utilizing such a technique, proposed LDO is able to achieve a fast transient response. Simulation results verify that the recovery time is as short as 7 μs and the maximum undershoot and overshoot are as low as 55 mV and 30 mV, respectively. In addition, the slew-rate enhancement circuit works in the subthreshold region at steady state, and proposed LDO consumes a 46.4-μA quiescent current to provide a maximum 100-mA load with a minimum 0.2-V dropout voltage. Besides, excellent line and load regulations are obtained and the values are 0.37 mV/V and 2 μV/mA, respectively.     

A High Voltage Line Driver for Subscriber Loop Interfaces in a Low Voltage Submicron BiCMOS Technology

This paper presents a 30 V line driver for short loop subscriber line interface circuit applications. The high voltage line drivers was implemented in a low-voltage 0.8 m BiCMOS process using 30 V extended-drain MOS transistors, fully compatible with the low voltage technology. Using a Quasi-Current Mirror architecture for the output stage, the line driver is capable of delivering more than 30 mA current into the lines with an idle current as low as 1 mA, satisfying the short loop requirements. With less than 0.24 mm² area, the circuit can be easily integrated with low-voltage circuitry on a single chip.     

96-GHz static frequency divider in SiGe bipolar technology

A static frequency divider designed in a 210-GHz f/sub T/, 0.13-/spl mu/m SiGe bipolar technology is reported. At a -5.5-V power supply, the circuit consumes 44 mA per latch (140 mA total for the chip, with input-output stages). With single-ended sine wave clock input, the divider is operational from 7.5 to 91.6 GHz. Differential clocking under the same conditions extends the frequency range to 96.6 GHz. At -5.0 V and 100 mA total current (28 mA per latch), the divider operates from 2 to 85.2 GHz (single-ended sine wave input).     

A 12-mW ADC delta-sigma modulator with 80 dB of dynamic rangeintegrated in a single-chip Bluetooth transceiver

This paper presents a switched-capacitor multibit ADC delta-sigma modulator for baseband demodulation integrated in a single-chip Bluetooth radio-modem transceiver that achieves 77 dB of signal-to-noise-plus-distortion ratio (SINAD) and 80 dB of dynamic range over a 500-kHz bandwidth with a 32-MHz sample rate. The 1-mm² circuit is implemented in a 0.35-μm BiCMOS SOI process and consumes 4.4 mA of current from a 2.7-V supply     

A low-power 15-GHz frequency divider in a 0.8-μm silicon bipolartechnology

In this paper, we present a low-power static frequency divider with a divide ratio of eight. It operates up to 15 GHz, consuming only 22 mA from a 3.6-V supply. The chip is manufactured in a 0.8-μm silicon bipolar production technology with a cutoff frequency of 25 GHz. The circuit has a single-ended input and output and is mounted in a six-pin SOT363 plastic package     

A 1.57-GHz fully integrated very low-phase-noise quadrature VCO

A very low-phase-noise quadrature voltage-controlled oscillator is presented, featuring an inherently better figure of merit than existing architectures. Through an improved circuit schematic and a special layout technique, the phase noise of the circuit can be lowered. The circuit draws 15 mA from a 2-V supply. The phase noise is -133.5 dBc/Hz at 600 kHz and the tuning range is 24% wide at a center frequency of 1.57 GHz     

An integrated CMOS current-sensing circuit for low-Voltage current-mode buck regulator

An integrated current-sensing circuit for low-voltage buck regulator is presented. The minimum achievable supply voltage of the proposed current-sensing circuit is 1.2 V implemented in a CMOS technology with V/sub TH/=0.85 V, and the current-sensing accuracy is higher than 94%. With the developed current-sensing circuit, a buck regulator, which is able to operate at a 1.2-V supply, is implemented. A maximum output current of 120 mA and power-conversion efficiency higher than 89% are achieved.     

A low-Voltage 10-bit CMOS DAC in 0.01-mm/sup 2/ die area

A low-voltage 10-bit digital-to-analog converter (DAC) for static/dc operation is fabricated in a standard 0.18-/spl mu/m CMOS process. The DAC is optimized for large integrated circuit systems where possibly dozens of such DAC would be employed for the purpose of digitally controlled analog circuit calibration. The DAC occupies 110 /spl mu/m/spl times/94 /spl mu/m die area. A segmented R-2R architecture is used for the DAC core in order to maximize matching accuracy for a minimal use of die area. A pseudocommon centroid layout is introduced to overcome the layout restrictions of conventional common centroid techniques. A linear current mirror is proposed in order to achieve linear output current with reduced voltage headroom. The measured differential nonlinearity by integral nonlinearity (DNL/INL) is better than 0.7/0.75 LSB and 0.8/2 LSB for 1.8-V and 1.4-V power supplies, respectively. The DAC remains monotonic (|DNL|<1 LSB) as INL reaches 4 LSB down to 1.3-V operation. The DAC consumes 2.2 mA of current at all supply voltage settings.     

A 900-MHz 1-V CMOS frequency synthesizer

A 900-MHz 1-V frequency synthesizer has been fabricated in a standard 0.35-μm CMOS technology. The frequency synthesizer consists of a divide-by-128/129 and 64/65 dual-modulus prescaler, phase-frequency detector, charge pump, and voltage-doubler circuit with an external voltage-controlled oscillator (VCO) and passive loop filter. The on-chip voltage-doubler circuit converts the 1-V supply voltage to the higher voltage which supplies the prescaler internally. In this way, the 900-MHz 1-V frequency synthesizer with an external VCO can be achieved. The measured phase noise is -112.7 dBc/Hz at a 100-kHz offset from the carrier, and the synthesizer dissipates 3.56 mW (not including VCOs) from a single 1-V supply when the switching frequency of the on-chip voltage doubler is 200 kHz and the power efficiency of the voltage doubler is 77.8%. The total chip area occupies 0.73 mm²     

A low-voltage switched-current delta-sigma modulator

This paper presents the design of a fully differential switched-current delta-sigma modulator using a single 3.3-V power-supply voltage. At system level, we tailor the modulator structure considering the similarity and difference of switched-capacitor and switched-current realizations. At circuit level, we propose a new switched-current memory cell and integrator with improved common mode feedback, without which low power-supply-voltage operation would not be possible. The whole modulator was implemented in a 0.8-μm double-metal digital CMOS process. It occupies an active area of 0.53×0.48 mm² and consumes a current of 0.6 mA from a single 3.3-V power supply. The measured dynamic range is over 10 b     

具有快速瞬态响应和低静态电流的CMOS低漏失稳压器设计

 设计了一种具有快速瞬态响应能力的低漏失稳压器,利用提出的一种瞬态响应加速(Transient Response Enhancement,TRE)电路,有效地提高了稳压器的瞬态响应速度,而且瞬态响应速度的提高并不增加静态电流.设计的LDO电路采用0.5μm标准CMOS工艺投片验证,芯片面积为0.49mm².该LDO空载下的静态电流仅23μA,最大带载200mA.在1μF输出电容、200mA/100ns负载阶跃变化时的最大瞬态输出电压变化量小于3.5％.     

An 11 GHz 3-V SiGe voltage controlled oscillator with integratedresonator

A 10.5- to 11-GHz fully monolithic voltage controlled oscillator circuit implemented in a standard SiGe bipolar technology is presented. An oscillator phase noise of -78 to -87 dBc/Hz is achieved at 100-kHz offset. The tuning range is close to 5% with an on-chip varactor-tuned resonator and for a control voltage of 0 to 3 V. The circuit draws less than 8 mA from a 3-V supply including the reference branch bias current