Mathematical simulation of the influence of the doping concentration on the drain current of an SOI field-effect hall sensor

The influence of the doping concentration in the active layer and in the bulk substrate on the drain current of a silicon-on-insulator (SOI) field-effect Hall sensor (FEHS) using Sentaurus TCAD is studied. At the initial stage, the numerical model is corrected by comparing the transfer current-voltage characteristics of the calculation and the experimentally measured SOI FEHS sample. It is shown that, under low concentrations in the active layer, the drain current depends on the capacity of the front gate, while the doping concentration in the bulk substrate affects the drain current only when the device is operating in depletion mode.     

A partially insulated field-effect transistor (PiFET) as a candidate for scaled transistors

Highly manufacturable partially insulated field-effect transistors (PiFETs) were fabricated by using Si-SiGe epitaxial growth and selective SiGe etch process. Owing to these technologies, pseudo-silicon-on-insulator (SOI) structures, partially insulating oxide (PiOX) under source/drain (PUSD) and PiOX under channel (PUC), could be easily realized with excellent structural and process advantages. We are demonstrating their preliminary characteristics and properties. Especially, in the PUSD PiFET, junction capacitance, leakage current, and DIBL in bulk devices could be reduced and the floating body problem in SOI devices was also cleared without any area penalty. Thus, this PiFET structure can be a promising candidate for the future DRAM cell transistor.     

Field-effect transistor with nanowire channel based on heterogeneously doped SOI

The article presents production methods and test results of field-effect transistor based on silicon nanowire made of heterogeneously arsenic-doped silicon on insulator (SOI). Dopant concentration has been varied over the depth of the silicon layer with a depth of 100 nm from higher than 10²⁰ cm^?3 to about 10¹⁷ cm^?3. The field-effect transistor was manufactured from SOI using electron beam lithography and reactive ion etching. The upper highly conducting part of silicon layer has been used as a substrate for input electrodes and contact pads. The lower sublayer has been used for the formation of semiconductor nanowire. The current-voltage and gate characteristics of the transistor have been measured at 77 and 300 K. The possibility of using a field-effect transistor based on silicon nanowire as a highly sensitive local field-effect and charge sensor with nanometric spatial resolution for application in various fields of physics, technology and medicine has been analyzed.     

Efficiency of SOI-like structures for reducing the thermal resistance in thin-film SOI power LDMOSFETs

Silicon-on-insulator (SOI)-like structures to remove the heat from the active silicon layer in thin-film SOI power lateral double diffused MOS field-effect transistors have been recently reported. This paper provides an experimental demonstration of their efficiency. For this purpose, a heater-sensor system based on poly-Si and platinum resistor stripes, respectively, has been integrated in thermal contact with the active silicon layer under study. The thermal resistance reduction due to the contact-through-buried-oxide technique and the SOI-multilayer substrates have been analyzed at steady state using different SOI layer thicknesses and heat source lengths, in accordance with the state-of-the-art. In addition, experimental results are supported by those extracted from numerical simulation of the heater-sensor system.     

基于SOS/SOI绝缘衬底的Si/SiGe HBT设计

着重讨论了衬底阻抗对HBT器件频率性能的劣化机制。基于双口网络理论，定量分析了fT和fm与衬底电阻率的关系；采用SOS／SOI绝缘衬底和自行设计的岛型膈离方法，抑制了绝大多数容性寄生参数；同时，围绕绝缘衬底进行Si／Si GeHBT的横向／纵向结构设计，开发出发射极自对准工艺方法，用于降低接触电阻和一定特征尺寸下的结面积，提高了HBT的频率性能。     

SOI LDMOSFET with Up and Down Extended Stepped Drift Region

To increase the breakdown voltage and decrease the ON resistance, a silicon-on-insulator (SOI) lateral double-diffused metal–oxide–semiconductor field-effect transistor (LDMOSFET) in which the drift region extends to the up and down oxides in a step shape is proposed. This up and down extended stepped drift SOI (UDESD-SOI) structure demonstrates a modified lateral electric field distribution with additional peaks as well as a decrease of the usual peaks near the drain and gate. Two-dimensional (2D) simulations were used to compare the characteristics of the proposed UDESD-SOI structure with those of other structures, viz. down extended stepped drift SOI (DESD-SOI), up extended stepped drift SOI (UESD-SOI), and conventional SOI (C-SOI). Under the same conditions, the breakdown voltage of the UDESD-SOI structure was nearly 35%, 117%, and 318% higher compared with the DESD-SOI, UESD-SOI, and C-SOI structure, respectively. To determine the optimum parameters for the UDESD-SOI structure leading to the highest breakdown voltage, a comparative study was performed to investigate the effect of the doping concentration in the drift region, buried oxide (BOX) thickness, and thickness of up and down extended steps (T ₁ and T ₂, respectively). In addition, the drain current (ON resistance) of the UDESD-SOI structure was found to be 13%, 43%, and 229% higher (16%, 65%, and 257% lower) than the values for the DESD-SOI, UESD-SOI, and C-SOI structure, respectively.     

Use of zone-melting recrystallization to fabricate a three-dimensional structure incorporating power bipolar and field-effect transistors

Three-dimensional (3-D) structures have been fabricated incorporating power bipolar transistors in a Si substrate and metal-oxide-semiconductor field-effect transistors (MOSFET's) in an overlying silicon-on-insulator (SOI) film that was zone-melting recrystallized with a graphite strip heater. Both N-P-N and P-N-P bipolar transistors were used. The N-P-N devices exhibited no significant change in transistor characteristics after zone-melting recrystallization (ZMR), while the P-N-P devices showed a substantial reduction in breakdown voltage. The MOSFET's exhibited electron mobilities comparable to those in similar devices fabricated in single-crystal Si wafers. The bipolar transistor yield is approximately 90 percent. The unusually high device quality and yield for 3-D structures obtained by the ZMR technique demonstrates the feasibility of fabricating monolithic structures incorporating both logic functions and relatively high-current high-voltage power switches.     

Numerical study of self-heating effects of MOSFETs fabricated on SOAN substrate

A two-dimensional numerical analysis is performed to investigate the self-heating effects of metal-oxide-silicon field-effect transistors (MOSFETs) fabricated in silicon-on-aluminum nitride (SOAN) substrate. The electrical characteristics and temperature distribution are simulated and compared to those of bulk and standard silicon-on-insulator (SOI) MOSFETs. The SOAN devices are shown to have good leakage and subthreshold characteristics. Furthermore, the channel temperature and negative differential resistance are reduced during high-temperature operation, suggesting that SOAN can mitigate the self-heating penalty effectively. Our study suggests that AlN is a suitable alternative to silicon dioxide as the buried dielectric in SOI, and expands the applications of SOI to high temperature.     

Strained quantum well modulation-doped ingasb/algasb structures grown by molecular beam epitaxy

Strained single quantum well InGaSb/AlGaSb structures for field-effect transistor applications have been grown by molecular beam epitaxy. Modulation-doped p-type structures have been characterized by a variety of techniques, including Hall effect, Shubnikov-de Haas measurements, and cyclotron resonance. These structures exhibit improved hole transport in comparison to similar GaSb/ AlGaSb structures as a result of strain-splitting of the valence band. P-channel field-effect transistors fabricated in this system exhibited a maximum transconductance of 51 and 161 mS/mm at 300 and 77K, respectively, for a 1.2 μm gate-length device.     

场引晶体管理论:Ⅺ.双极电化电流(薄及厚、纯及不纯基体,单及双MOS栅极)

场引晶体管本质双极,包括电子和空穴表面和体积沟道和电流,一或多个外加横向控制电场.自1952年Shockley发明,55年来它被认为单极场引晶体管,因电子电流理论用多余内部和边界条件,不可避免忽略空穴电流.多余条件,诸如电中性和常空穴电化电势,导致仅用电子电流算内部和终端电学特性的错误解.当忽略的空穴电流与电子电流可比,可在亚阈值区和强反型区,错误解有巨大误差.本文描述普适理论,含有电子和空穴沟道和电流.用z轴宽度方向均匀的直角平行六面体(x,Y,z)晶体管,薄或厚、纯或杂基体,一或二块MOS栅极,描述两维效应及电势、电子空穴电化电势的正确内部和边界条件.没用多余条件,导出四种常用MOS晶体管,直流电流电压特性完备解析方程:半无限厚不纯基上一块栅极(传统的Bulk MOSFET),与体硅以氧化物绝缘的不纯硅薄层上一块栅极(SOI),在沉积到绝缘玻璃的不纯硅薄层上一块栅极(SOI TFT),和薄纯基上两块栅极(FinFETs).     

场引晶体管理论:XI.双极电化电流（薄及厚、纯及不纯基体,单及双MOS栅极）

场引晶体管本质双极,包括电子和空穴表面和体积沟道和电流,一或多个外加横向控制电场．自1952年Shockley发明,55年来它被认为单极场引晶体管,因电子电流理论用多余内部和边界条件,不可避免忽略空穴电流．多余条件,诸如电中性和常空穴电化电势,导致仅用电子电流算内部和终端电学特性的错误解．当忽略的空穴电流与电子电流可比,可在亚阈值区和强反型区,错误解有巨大误差．本文描述普适理论,含有电子和空穴沟道和电流．用z轴宽度方向均匀的直角平行六面体（x,y,z）晶体管,薄或厚、纯或杂基体,一或二块MOS栅极,描述两维效应及电势、电子空穴电化电势的正确内部和边界条件．没用多余条件,导出四种常用MOS晶体管,直流电流电压特性完备解析方程：半无限厚不纯基上一块栅极（传统的Bulk MOSFET）,与体硅以氧化物绝缘的不纯硅薄层上一块栅极（SOI）,在沉积到绝缘玻璃的不纯硅薄层上一块栅极（SOI TFT）,和薄纯基上两块栅极（FinFETs）．     

SOI LDMOSFET的背栅特性

在绝缘体上硅衬底上,制备了栅长为0.5μm的低势垒体接触结构和源体紧密接触结构的横向双扩散功率晶体管.详细研究了器件的背栅特性.背栅偏置电压对横向双扩散功率晶体管的前栅亚阈值特性、导通电阻和关态击穿特性均有明显影响.相比于源体紧密接触结构,低势垒体接触结构横向双扩散功率晶体管的背栅效应更小,这是因为低势垒体接触结构更好地抑制了浮体效应和背栅沟道开启.还介绍了一种绝缘体上硅横向双扩散功率晶体管的电路模型,其包含前栅沟道,背栅沟道和背栅偏置决定的串联电阻.     

Study of the effect of the gate region parameters on static characteristics of microwave field-effect transistors based on pseudomorphic AlGaAs-InGaAs-GaAs heterostructures

The results of numerical simulation and experimental study of the effect of the gate region parameters on static characteristics of microwave field-effect transistors based on pseudomorphic AlGaAs-InGaAs-GaAs heterostructures (p-HEMT) are considered. The possibility of correct simulation of static characteristics of actual device structures of p-HEMT transistors using the TCAD software package (SILVACO Inc.) is demonstrated. The essential necessity of using selective gate-groove etching to achieve controllable and reproducible device parameters is shown.     

基于器件仿真的参数提取方法研究

介绍器件参数提取的意义,并对基于工艺的参数提取和基于器件仿真的参数提取两种方法进行了比较。根据0.35 μm SOI CMOS工艺参数,构造出部分耗尽SOI NMOS结构。基于BSIM SOI模型采用局部优化,单器件提取的策略进行参数提取。最后通过将仿真与实际测试得到的参数比较,验证了该方法的准确性。     

Simulation of Hall Field Elements Based on Nanosized Silicon-on-Insulator Heterostructures

Russian Microelectronics - This article is devoted to the issues of numerical simulation of field Hall sensors (FHSs) based on the silicon-on-insulator (SOI) structure with two control gates. To...     

Design guideline for minimum channel length in silicon-on-insulator (SOI) MOSFET

This brief proposes a preliminary design guideline for the minimum channel length in silicon-on-insulator (SOI) MOSFETs that is based on simulations of device characteristics. The simulations examine a wide variation in many device parameters to comprehensively evaluate device characteristics. A characteristic parameter that can successfully describe the minimum channel length is found. It is suggested that a sub-20-nm-channel single-gate SOI MOSFET with suppressed short-channel effects can be stably realized by optimizing its device parameters.     

Nonlinearity in hall devices and its compensation

Three types of nonlinearity effects can be distinguished in Hall devices: material, geometrical and junction field-effect nonlinearity. Material nonlinearity, a magnetic field dependence of the Hall coefficient, is experimentally characterized for n-type silicon as a function of carrier concentration and temperature. Geometrical nonlinearity, which is due to the short-circuiting effects by the sensor contacts, is related to the geometrical correction factor. It is shown that material and geometrical non-linearity can mutually cancel. Junction field-effect nonlinearity comes about as a modulation of the plate thickness in junction-isolated, integrated Hall devices. The junction field-effect can also be used to compensate nonlinearity.     

Defect transformation study in silicon-on-insulator structures by high-resolution X-Ray diffraction

Silicon-on-insulator (SOI) structures were fabricated by bonding using a new variant of Smart-Cut technology. As-bonded SOI structures are annealed at high temperature (1100°C) for removal of hydrogen, radiation defects and stresses at the bonding interface. The transformation of structural parameters in as-bonded and annealed SOI structures was investigated by high-resolution X-ray diffraction. The large strain observed for as-bonded SOI structures is relaxed during annealing at high temperature and final SOI wafer has strain-free top silicon layer due to defect annealing and viscous flow of SiO₂. FWHM value for SOI film is higher than that for typical silicon single crystal and is caused by mosaic-like structure only.     

基于SOI衬底的射频电感优化设计

比较了SOIRF电感与体硅电感的性能 ,并根据模拟结果分析了电感中空面积 ,电感形状结构 ,金属宽度、间距对SOI电感品质因数Q、自谐振频率、电感量L的影响 ,最后提出了一种基于SOI衬底RF电感的优化设计原则 .以往射频集成电感性能的比较并不固定电感值 ,而文中全部参数的变化都是在电感值相同的情况下进行比较     

Silicon-on-insulator optical rib waveguide loss and modecharacteristics

Optical rib waveguides with rib heights of 3.17 and 7.67 microns with various widths have been formed in separation by implantation of oxygen (SIMOX) based silicon-on-insulator (SOI) structures. The effect of waveguide rib etch depth, width, and interface roughness on loss and mode characteristics have been studied at wavelengths of 1.15 and 1.523 microns. The experimental results support the hypothesis that certain rib dimensions can lead to single mode SOI waveguides even though planar SOI waveguides of similar multimicron dimension are not single mode. Mode loss was found to be strongly dependent on interface roughness and mode confinement