A 3.6-Gb/s 340-mW 16:1 pipe-lined multiplexer using 0.18 μmSOI-CMOS technology

This paper describes a 16:1 multiplexer using 0.18 μm SOI-CMOS technology. To realize ultra-high-speed operations, the multiplexer adapts a pipeline structure and a phase shift technique together with a selector architecture. This architecture takes advantage of the small junction capacitances of the SOI-CMOS devices. The multiplexer achieves 3.6 Gb/s at a supply voltage of 2.0 V, while dissipating only 30 mW at the core circuit and 340 mW for the whole chip which includes the I/O buffers     

50-Gb/s SiGe BiCMOS 4:1 multiplexer and 1:4 demultiplexer for serial communication systems

4:1 multiplexer and 1:4 demultiplexer ICs targeting SONET OC-768 applications are reported. The ICs have been implemented using a 120-GHz-f/sub T/ 0.18-/spl mu/m SiGe BiCMOS process. Both ICs have been packaged to enable bit error rate testing by connecting their serial interfaces. Error-free operation has been achieved for both circuits at data rates beyond 50 Gb/s. At a -3.6-V supply voltage, the multiplexer and demultiplexer dissipate 410 and 430 mA, respectively. Switching behavior of the 4:1 multiplexer has also been checked up to 70 Gb/s.     

100-Gb/s multiplexing and demultiplexing IC operations in InP HEMT technology

This paper describes the 100-Gb/s multiplexing operation of a selector IC and demultiplexing operation of a D-type flip-flop (D-FF) using production-level 0.1-/spl mu/m-gate-length InP HEMT IC technology. To boost the operating speed of the selector IC, a selector core circuit directly drives an external 50-/spl Omega/ load, and is included in the output stage. In addition, a test chip containing the selector and a D-FF to confirm error-free operation of these circuits was designed. The fabricated selector IC exhibited clear eye openings at 100 Gb/s, and its error-free operation was confirmed by using the test chip.     

50-Gb/s 4-b multiplexer/demultiplexer chip set using InP HEMTs

A 50-Gb/s 4:1 multiplexer (MUX) and 1:4 demultiplexer (DEMUX) chip set using InP high electron mobility transistors (HEMTs) is described. In order to achieve wide-range bit-rate operation from several to 50 Gb/s, timing design inside the ICs was precisely executed. The packaged MUX operated from 4 to 50Gb/s with >1-V/sub pp/ output amplitude, and the DEMUX exhibited >180/spl deg/ phase margin from 4 to 50 Gb/s for 2/sup 31/-1 pseudorandom bit sequence (PRBS). Furthermore, 50-Gb/s back-to-back error-free operation for 2/sup 31/-1 PRBS was confirmed with the packaged MUX and DEMUX.     

40-Gb/s 2:1 multiplexer and 1:2 demultiplexer in 120-nm standard CMOS

We present an integrated 2:1 multiplexer and a companion 1:2 demultiplexer in CMOS. Both integrated circuits (ICs) operate up to a bit rate of 40 Gb/s. The 2:1 multiplexer features two in-phase data inputs which are achieved by a master-slave flip-flop and a master-slave-master flip-flop. Current-mode logic is used because of the higher speed compared to static CMOS and the robustness against common-mode disturbances. The multiplexer uses no output buffer and directly drives the 50-/spl Omega/ environment. An inductance connected in series to the output in combination with shunt peaking is used to enhance the bandwidth of the multiplexer. Fully symmetric on-chip inductors are used for peaking. The inductors are mutually coupled to save chip area. Lumped equivalent models of both peaking inductors allow optimization of the circuit. The ICs are fabricated in a 120-nm standard CMOS technology and use 1.5-V supply voltage. Measured eye diagrams of both ICs demonstrate their performance.     

High-gain transimpedance amplifier in InP-based HBT technology forthe receiver in 40-Gb/s optical-fiber TDM links

A monolithic integrated transimpedance amplifier for the receiver in a 40-Gb/s optical-fiber TDM system has been fabricated in an InP-based HBT technology. Despite its high gain (transimpedance of 2 kΩ in the limiting mode, 10 kΩ in the linear mode) the complete amplifier was realized on a single chip. Clear output eye diagrams were measured up to 43 Gb/s under realistic driving conditions. The voltage swing of 0.6 V_pp at the differential 50 Ω output does not change within the demanded input dynamic range of 6 dB. At the upper input current level even 48 Gb/s were achieved. The power consumption is approximately 600 mW at a single supply voltage of -5.5 V     

A 9.6-Gb/s HEMT ATM switch LSI with event-controlled FIFO

An asynchronous-transfer-mode (ATM) switch LSI was designed for the broadband integrated services digital network (B-ISDN) and fabricated using 0.6-μm high-electron-mobility-transistor (HEMT) technology. To enhance the high-speed performance of direct-coupled FET logic (DCFL), event-controlled logic was used instead of conventional static memory for the first-in first-out (FIFO) buffer circuit. The 4.8-mm×4.7-mm chip contains 7100 DCFL gates. The maximum operating frequency was 1.2 GHz at room temperature with a power dissipation of 3.7 W. The single-chip throughput was 9.6 Gb/s. An experimental 4-to-4 ATM switching module using 16 switch LSIs achieved a throughput of 38.4 Gb/s     

A 165-Gb/s 4:1 Multiplexer in InP DHBT Technology

This paper presents a 4:1 multiplexer fabricated in InP double heterojunction bipolar transistor (DHBT) technology. The multiplexer works up to 165 Gb/s at a supply voltage of$-hbox3.2~V$consuming 1.6 W. It is a half-rate multiplexer using a multi-phase clock architecture. The main design challenge was to ensure correct timing between clock and data signals.     

A 20-Gb/s silicon bipolar 1:4-demultiplexer IC

This paper presents a 20-Gb/s 1:4-demultiplexer for future fiber-optic transmission systems. It uses an 0.4-μm emitter double polysilicon 21-GHz f_T Si bipolar foundry process. This is the highest data rate of a 1:4-DEMUX reported so far in any technology. The 1:4-DEMUX features a tree-type architecture with one frequency divider and a channel switch circuit. The circuit design was carefully optimized to achieve high speed and moderate power dissipation. It consumes 1.4 W with a single -4.5-V supply     

A 43-Gb/s full-rate clock transmitter in 0.18-/spl mu/m SiGe BiCMOS technology

A 43-Gb/s full-rate clock transmitter chip for SONET OC-768 transmission systems is reported. The IC is implemented in a 0.18-/spl mu/m SiGe BiCMOS technology featuring 120 GHz f/sub T/ and 100 GHz f/sub max/ HBTs. It consists of a 4:1 multiplexer, a clock multiplier unit, and a frequency lock detector. The IC features clock jitter generation of 260 fs rms and dissipates 2.3 W from a -3.6-V supply voltage. Measurement results are compared to a previously reported half-rate clock transmitter designed using the same technology.     

A 4 Gbits/s GaAs 16:1 multiplexer/1:16 demultiplexer LSI chip

A GaAs 16:1 multiplexer (MUX)/1:16 demultiplexer (DMUX) LSI chip, which operates at data rates from 50 Mb/s up to 4 Gb/s in a multilayer ceramic package, is described. The LSI chip incorporates trees of 2:1 MUX and 1:2 DMUX. The 2:1 MUX is composed of a master-slave D-flip-flop (DFF) joined with a 2-1 selector. The 1:2 DMUX consists of DFFs which are either a master-slave or the tristage type. The package has 76 pins and consists of five layers, including four power layers, and is applicable up to 7.7 GHz operation. The LSI chip is fabricated using a flat-gate self-aligned implantation for n⁺-layer technology (FG-SAINT process)     

A 10-Gb/s 16:1 multiplexer and 10-GHz clock synthesizer in0.25-μm SiGe BiCMOS

A 10-Gb/s 16:1 multiplexer, 10-GHz clock generator phase-locked loop (PLL), and 6 × 16 b input data buffer are integrated in a 0.25-μm SiGe BiCMOS technology. The chip multiplexes 16 parallel input data streams each at 622 Mb/s into a 9.953-Gb/s serial output stream. The device also produces a 9.953-GHz output clock from a 622- or 155-MHz reference frequency. The on-board 10-GHz voltage-controlled oscillator (VCO) has a 10% tuning range allowing the chip to accommodate both the SONET/SDH data rate of 9.953 Gb/s and a forward error correction coding rate of 10.664 Gb/s. The 6 × 16 b input data buffer accommodates ±2.4 ns of parallel input data phase drift at 622 Mb/s. A delay-locked loop (DLL) in the input data buffer allows the support of multiple input clocking modes. Using a clock generator PLL bandwidth of 6 MHz, the 9.953-GHz output clock exhibits a generated jitter of less than 0.05 UI_P-P over a 50-kHz to 80-MHz bandwidth and jitter peaking of less than 0.05 dB     

A 40-43-Gb/s clock and data recovery IC with integrated SFI-5 1:16 demultiplexer in SiGe technology

A fully integrated OC-768 clock and data recovery IC with SFI-5 1:16 demultiplexer is designed in a 120-GHz/100-GHz (f/sub T//f/sub MAX/) SiGe technology. The 16 2.5-Gb/s outputs and additional deskew channel are compliant with the Serdes Framer Implementation Agreement Level 5 specification. The measured bit-error rate is <10/sup -15/. The measured jitter tolerance exceeds the mask specified in G.8251. The IC operates with 1.8-V and -5.2-V supplies and dissipates 7.5 W.     

Fully monolithic integrated 43 Gbit/s clock and data recoverycircuit in InP HEMT technology

A fully monolithic integrated 43 Gbit/s clock and data recovery circuit for optical fibre communication systems is described. The circuit is based on a phase-locked loop technique, and the input data signal is regenerated with the data-rate clock signal. The circuit was fabricated with 0.1 μm gate-length InAlAs/InGaAs/InP HEMTs, and error-free operation was confirmed for 2³¹-1 PRBS data signal at 43 Gbit/s     

具有时钟提取及倍频功能的 5Gb/s全速率复接器设计

采用SMIC 0．18μm CMOS工艺设计了一个具有时钟提取及倍频功能的5Gb／s全速率2：1复接电路。整个电路由两部分构成,即：全速率2：1复接器和时钟提取及倍频环路。其中,后者从一路2．5Gb／S输入数据中提取出时钟信号,并为前者提供所需的2．5GHz及5GHz的时钟。Pottbgcker鉴频鉴相器被运用以提高环路的捕获带宽。设计广泛采用了具有速度高和抗干扰能力强等诸多优点的电流模逻辑。仿真结果表明,本电路无需任何参考时钟,无需外接元件及手动相位调整或辅助捕获,就能可靠地工作在2．4～2．9Gb／s的输入数据速率上。芯片面积为812μm&#215;675μm。电源电压1．8V时,功耗为162mW。     

A fully integrated 40-Gb/s clock and data recovery IC with 1:4DEMUX in SiGe technology

In this paper, a fully integrated 40-Gb/s clock and data recovery (CDR) IC with additional 1:4 demultiplexer (DEMUX) functionality is presented. The IC is implemented in a state-of-the-art production SiGe process. Its phase-locked-loop-based architecture with bang-bang-type phase detector (PD) provides maximum robustness. To the authors' best knowledge, it is the first 40-Gb/s CDR IC fabricated in a SiGe heterojunction bipolar technology (HBT). The measurement results demonstrate an input sensitivity of 42-mV single-ended data input swing at a bit-error rate (BER) of 10^-10. As demonstrated in optical transmission experiments with the IC embedded in a 40-Gb/s link, the CDR/DEMUX shows complete functionality as a single-chip-receiver IC. A BER of 10^-10 requires an optical signal-to-noise ratio of 23.3 dB     

Simulation and design methodology for a 50-Gb/s multiplexer/demultiplexer package

A 50 Gb/s package for SiGe BiCMOS 4:1 multiplexer and 1:4 demultiplexer targeting SONET OC-768 serial communication systems is introduced in this work. The package was designed to facilitate bit-error-rate tests and constructed with high-speed coaxial connectors, transmission lines on ceramic substrate, ribbon bonds for chip-to-package interconnects, and a metal composite housing. Numerical simulations were conducted to guide the package design, and both small signal measurements and operational tests were performed thereafter to verify the design and modeling concepts. To keep the model structure under the existing computing capability, the simulation was segmented into three sections - coaxial connector to transmission line, transmission line alone, and transmission line to ribbon bond, and then the results were assembled to predict the performance of the entire package. The package was operated up to 50 Gb/s with low degradation to input digital waveforms and free of error.     

50 Gbit/s 2:1 multiplexer in 0.13 /spl mu/m CMOS technology

A fully integrated 2:1 multiplexer IC which operates at up to 50 Gbit/s data rate is presented. The MUX uses inductive shunt peaking and an output series inductor for higher bandwidth. The MUX directly drives the 50 /spl Omega/ load. The IC is fabricated in a 0.13 /spl mu/m bulk CMOS technology and draws 65 mA at 1.5 V supply voltage. The output voltage swing is 2/spl times/100 mV.     

100-Gb/s 2/sup 7/-1 and 54-Gb/s 2/sup 11/-1 PRBS generators in SiGe bipolar technology

This paper presents two monolithic pseudorandom bit sequence (PRBS) generators. One circuit uses a seven-stage shift register operating with a half-rate clock and provides output signals up to 100 Gb/s. The second circuit contains an eleven-stage shift register operating with a full-rate clock up to 54 Gb/s. Both PRBS generators provide a wide range of data rates down to below 1 Gb/s simply by changing the frequency of the external clock signal without the need of any further adjustments. The integrated circuits provide a trigger output which can be switched between eye and pattern display. Furthermore, they contain additional circuitry to guarantee automatic start after power-on. The circuits are manufactured in a 200-GHz f/sub T/ SiGe bipolar technology. They each have a chip size of 900/spl times/700 /spl mu/m/sup 2/ and consume 1.5 and 1.9 W, respectively.     

12-Gb/s 0.25-μm CMOS 1:4分接器

介绍光纤传输系统的组成,分析1:4分接器的树型结构,并给出其主要特点.在此基础上,进一步探讨树型结构中所用的1:2分接器,并给出其中的锁存器电路结构.此外,讨论了起重要作用的匹配电路以及驱动电路.电路采用标准的0.25μm CMOS工艺设计并实现.实际测试结果显示该电路能够稳定地在STM-16至STM-64所要求的数据速率下工作,最高工作速率为12.92Gb/s.