A 50-Gbit/s 450-mW Full-Rate 4:1 Multiplexer With Multiphase Clock Architecture in 0.13- μm InP HEMT Technology

A full-rate multiplexer (MUX) with a multiphase clock architecture for over 40 Gbit/s optical communication systems is presented. The 4:1 MUX is comprised of a re-timer based on a D-type flip-flop (DFF) and a clock tree system that uses EXOR-type delay buffers to match its skews well to those of the data. The supply voltage is reduced to -1.5 V by analyzing the voltage allocation. Fabricated in a 0.13-mum InP HEMT technology, a DFF test circuit achieved 75-Gbit/s operation and exhibited performance sufficient to re-time 50-Gbit/s serialized data. The 4:1 MUX measurement results demonstrate successful 50-Gbit/s operation at room temperature, and 40-Gbit/s operation, which has 10^-11 error free for 2³¹ - 1 pseudorandom bit stream (PRBS) data, up to an ambient temperature of 90 degrees or down to - 1.24 V of supply voltage. The circuit consumes 450 mW at a - 1.5-V supply and exhibits an output jitter of 283 fs rms at 50-Gbit/s operation. We also propose a multiphase clock generator for a MUX that has a serialization of more than four channels     

A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os

A 0.622-8-Gb/s clock and data recovery (CDR) circuit using injection locking for jitter suppression and phase interpolation in high-bandwidth system-on-chip solutions is described. A slave injection locked oscillator (SILO) is locked to a tracking aperture-multiplying DLL (TA-MDLL) via a coarse phase selection multiplexer (MUX). For the fine timing vernier, an interpolator DAC controls the injection strength of the MUX output into the SILO. This 1.2-V 0.13-/spl mu/m CMOS CDR consumes 33 mW at 8Gb/s. Die area including voltage regulator is 0.08 mm/sup 2/. Recovered clock jitter is 49 ps pk-pk at a 200-ppm bit-rate offset.     

SiGe-HBT-based 54-gb/s 4:1 multiplexer IC with full-rate clock for serial communication systems

A 4:1 multiplexer (MUX) IC for 40 Gb/s and above operations in optical fiber link systems has been developed. The ICs are based on 122-GHz-f/sub T/ 0.2-/spl mu/m self-aligned selective-epitaxial-growth SiGe HBT technology. To reduce output jitter caused by clock duty distortion, a master-slave delayed flip-flop (MS-DFF) with full-rate clock for data retiming is used at the final stage of the MUX IC. In the timing design of the critical circuit for full-rate clocking, robust timing design that has a wide timing margin between data and clock at the MS-DFF was achieved. Measurements using on-wafer probes showed that the MUX attained 54-Gb/s operation with an output voltage-swing of 400 mVpp. The output rms jitter generated by the MUX was 0.91 ps and tr/tf (10%-90%) was 11.4/11.3 ps at a data rate of 50 Gb/s. Power consumption of the IC was 2.95 W at a power supply of -4.8 V. Error-free operation (<10/sup -12/) in back-to-back configuration of the MUX and a 1:4 DEMUX IC module at a data rate of 45 Gb/s was confirmed. We therefore concluded that the MUX IC can be applied for transmitter functions in optical-fiber-link systems at a data rate of 40 Gb/s and higher for forward error correction.     

5?Gb/s 2:1 fully-integrated full-rate multiplexer with on-chip clock generation circuit in 0.18-μm CMOS

A 5?Gb/s 2:1 full-rate multiplexer (MUX) has been designed and fabricated in SMIC 0.18-??m CMOS process. A clock generation circuit (CGC) is also integrated to provide the MUX with both 2.5 and 5-GHz clock signals. The CGC is realized by a clock and data recovery (CDR) loop with a divide-by-2 frequency divider embedded in, where the two required clocks are obtained after and before the divider, respectively. In addition, the phase relation between data and clock is assured automatically by CDR feedback loop and the precise layout. The whole chip area is 812?×?675???m, including pads. At a single supply voltage of 1.8?V, the total power consumption is 162?mW with an input sensitivity of <25?mV and a single-ended output swing of above 300?mV. And due to the full-rate architecture, the pulse width distortion (PWD) with multiplexed data is removed. The measured results also show that the circuit can work reliably at any input data rate between 2.46 and 2.9?Gb/s without need for external components, reference clock, or manual phase alignment between data and clock.     

A 30-gb/s 70-mW one-stage 4:1 multiplexer in 0.13-/spl mu/m CMOS

A completely integrated 4:1 multiplexer for high-speed operation and low power consumption is presented. The circuit uses a new architecture where four data streams are multiplexed in one stage. Pulses with a duty cycle of 25% switch the inputs to the multiplexer (MUX) output. The pulses are generated from the clock signal and the divided clock signal. Measurement results show the performance of the IQ divider. Current-mode logic is used because of the higher speed compared to static CMOS and the robustness against common-mode disturbances. The multiplexer uses no output buffer and directly drives the 50-/spl Omega/ environment. The lower number of gates compared to the conventional tree topology enables low-power design. Relaxed timing conditions are additional benefits of the one-stage MUX topology. The IC is fabricated in a 0.13-/spl mu/m standard bulk CMOS technology and uses 1.5-V supply voltage. The MUX works up to 30 Gb/s and consumes 70 mW.     

A 2.125-Gb/s BiCMOS fiber channel transmitter for serial datacommunications

A 2.125-Gb/s transmitter meeting the specifications of the emerging ANSI Fiber Channel standard has been developed using BiCMOS technology. This transmitter features (1) a fully bipolar 10:1 multiplexer (MUX) and a 2.125-GHz retimer for high-accuracy transmission of data, (2) an emitter-coupled logic (ECL) CMOS analog phase-locked loop, (3) pure ECL-level output for direct connection to the currently available optical modules, and (4) BiCMOS process technology that includes 0.25-μm CMOS devices and 20-GHz bipolar devices. The LSI serializes 32-bit-wide, 53.125-Mb/s data into 2.125-Gb/s data through a CMOS 8B10B encoder. The chip area is 3×2 mm², and the power dissipation is 860 mW     

STS-768 multiplexer with full-rate output data retimer in InP HBT

A 16:1 STS-768 multiplexer IC has been designed and fabricated using the Vitesse Semiconductor VIP-1 process. This IC is part of a complete chip-set solution for a 40-Gb/s STS-768 optical communication transceiver module. The multiplexer IC features a full-rate clock multiplication unit and a data retimer in the output stage to reduce duty-cycle distortion and jitter in the output data eye. Because of its strict timing requirements, this approach needs fast logic gates with a very low gate delay. The Vitesse VIP-1 process, with 150-GHz f/sub t/ and 150-GHz f/sub max/ heterojunction bipolar transistor, is an obvious choice to implement this IC. The multiplexer IC typically dissipates 3.6 W from -3.6-V and -5.2-V power supplies. This paper discusses the design and development of a 40-Gb/s 16:1 multiplexer IC including current-mode logic gate circuit design, divide-by-two, 40-GHz clock tree, voltage-controlled oscillator, clock multiplication unit, and output driver. Layout design and package design are also discussed due to their significant roles in the IC performance.     

A Tree-Topology Multiplexer for Multiphase Clock System

This paper proposes a tree-topology multiplexer (MUX) that employs a multiphase low-frequency clock rather than a high-frequency clock. Analysis and simulation results show that the proposed design can achieve higher bandwidth and be less sensitive to process variations than the conventional single-stage MUX. In order to verify the feasibility, this proposed design is integrated with a multiphase phase-locked loop and a low-voltage differential signaling driver in a 0.18- ${rm mu}hbox{m}$ CMOS technology. Measured results indicate that the proposed design can operate up to 7 gigabits/s under 0.3-UI jitter limitation.      

A 150 mW 8:1 MUX and a 170 mW 1:8 DEMUX for 2.4 gb/s optical-fibercommunication systems using n-AlGaAs/i-InGaAs HJFET's

An 8:1 multiplexer (MUX) and a 1:8 demultiplexer (DEMUX) for 2.4-Gb/s optical communication systems have been developed using 0.35-μm GaAs heterojunction field-effect transistors (FETs). To ensure timing margins, a new timing generator with latches and new clock buffers with cross-coupled inverters have been developed. These large-scale integrations (LSIs) operate at over 2.4 Gb/s with a power consumption of 150 mW (MUX) and 170 mW (DEMUX) at a supply voltage of 0.7 V, and at over 5 Gb/s with power consumption of 200 mW at a supply voltage of 0.8 V     

50-Gb/s 4-b multiplexer/demultiplexer chip set using InP HEMTs

A 50-Gb/s 4:1 multiplexer (MUX) and 1:4 demultiplexer (DEMUX) chip set using InP high electron mobility transistors (HEMTs) is described. In order to achieve wide-range bit-rate operation from several to 50 Gb/s, timing design inside the ICs was precisely executed. The packaged MUX operated from 4 to 50Gb/s with >1-V/sub pp/ output amplitude, and the DEMUX exhibited >180/spl deg/ phase margin from 4 to 50 Gb/s for 2/sup 31/-1 pseudorandom bit sequence (PRBS). Furthermore, 50-Gb/s back-to-back error-free operation for 2/sup 31/-1 PRBS was confirmed with the packaged MUX and DEMUX.     

BiCMOS circuit technology for a 704 MHz ATM switch LSI

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W     

4-bit multiplexer/demultiplexer chip set for 40-Gbit/s optical communication systems

We have designed and fabricated a low-power 4:1 multiplexer (MUX), 1:4 demultiplexer (DEMUX) and full-clock-rate 1:4 DEMUX with a clock and data recovery (CDR) circuit using undoped-emitter InP-InGaAs HBTs. Our HBTs exhibit an f/sub T/ of approximately 150 GHz and an f/sub max/ of approximately 200 GHz at a collector current density of 50 kA/spl mu/m/sup 2/. In the circuit design, we utilize emitter-coupled logic and current-mode logic series gate flip-flops and optimized the collector current density of each transistor to achieve low-power operation at required high bit rates. Error-free operation at bit rates of up to 50 Gbit/s were confirmed for the 4:1 MUX and 1:4 DEMUX, which dissipates 2.3 and 2.5 W, respectively. In addition, the full-clock-rate 1:4 DEMUX with the CDR achieved 40-Gbit/s error-free operation.     

Ultrahigh-speed heterojunction bipolar transistormultiplexer/demultiplexer ICs

High-speed 2-b monolithic integrated multiplexer (MUX) and demultiplexer (DMUX) circuits have been developed using self-aligned AlGaAs/GaAs heterojunction bipolar transistors (HBTs) with improved high-speed performance. Both ICs were designed using emitter-coupled logic. The 2:1 MUX was composed of a D-type flip-flop (D-FF) merging a selector gate and a T-type flip-flop (T-FF). The 1:2 DMUX consisted of two D-FFs driven at a clock of half the rate of the input data. Error-free operation with a pseudorandom pattern was confirmed up to 10 Gb/s. The rise and fall times of the output signals of both ICs were 40 and 25 ps, respectively. HBT frequency dividers were used as inputs for both ICs in order to find the maximum operation speed. Although only a few test patterns were available, the maximum operation speeds of the MUX and DMUX were found to be around 15 and 19 Gb/s, respectively     

80 Gb/s 2 : 1 multiplexer in 0.13-μm SiGe BiCMOS technology

This work presents an ultra-high speed 2 : 1 multiplexer (MUX) in a SiGe BiCMOS technology with fT = 103 GHz. To boost the operating speed, the system scheme is optimized including a 2 : 1 selector circuit directly driving an external 50 Ω load, and two wide-band data buffers and one clock buffer in the input stage. The chip exhibited an open eye at 80 Gb/s with a 160 mV single-ended voltage swing.     

A 15-gb/s 2:1 multiplexer in 0.18-/spl mu/m CMOS

By employing the inductive peaking technique and the super-dynamic flip-flops, a 2:1 multiplexer (MUX) is presented for high-speed operations. The proposed circuit is realized in a 0.18-/spl mu/m CMOS process. With a power consumption of 110mW from a 2-V supply voltage, the fully integrated MUX can operate at an output rate up to 15Gb/s. From the measured eye-diagrams, the 15-Gb/s half-rate MUX exhibits an output voltage swing of 225mV and a root-mean-square jitter of 2.7ps.     

带有自适应频率校准单元的26~41 GHz锁相环

采用45 nm SOI CMOS工艺,设计了一种带有自适应频率校准单元的26~41 GHz 锁相环。该锁相环包括输入缓冲器、鉴频鉴相器、电荷泵、环路滤波器、压控振荡器、高速时钟选通器、分频器和频率数字校准单元。采用了基于双LC-VCO的整数分频锁相环,使用了自适应频率选择的数字校准算法,使得锁相环能在不同参考时钟下自适应地调整工作频率范围。仿真结果表明,该锁相环的输出频率能够连续覆盖26~41 GHz。输出频率为26 GHz时,相位噪声为-103 dBc/Hz@10 MHz,功耗为34.64 mW。输出频率为41 GHz时,相位噪声为-96 dBc/Hz@10 MHz,功耗为35.44 mW。     

基于0.13微米锗硅BiCMOS工艺的80 Gb/s 2:1 复接器

本文介绍了基于0.13微米锗硅BiCMOS工艺设计的超高速2:1复接器芯片,工艺fT为103 GHz。为了最大限度提高工作速度,系统方案进行了优化,采用了选择器输出直接驱动片外50 Ω负载的形式,并在输入级集成了两个宽带数据放大器和一个时钟放大器。经测试,芯片输出眼图达到了80 Gb/s的速率,单端电压摆幅为160 mV。     

2.5 Gb／s 16：1 MUX IC Design with CMOS

A low--power and high--speed 16.-1 MUX IC designed for optical fiber communication based on TSMC 0.25μm CMOS technology is presented. A tree—type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak—to—peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is 1.8mm^2.     

A CMOS mixed-signal clock and data recovery circuit for OIF CEI-6G+ backplane transceiver

A CMOS low-power mixed-signal clock and data recovery circuit is presented in this paper. It is designed for OIF CEI-6G+ LR backplane transceiver, and consists of a phase detector, loop filter, phase control logic, and phase interpolator. A unique subsampled architecture makes it possible for a low-power mixed-signal clock recovery loop running at a rate of 6 Gb/s. The proposed architecture has data pattern independent loop bandwidth. Fabricated in a 0.13-/spl mu/m CMOS technology in an area of 280/spl times/100 /spl mu/m/sup 2/, the clock and data recovery loop exhibits a frequency tracking range up to 2000 ppm. The bit error rate is less than 10/sup -12/ with a pseudorandom bit sequence of length 2/sup 31/-1. The power dissipation is 24 mW for clock and data recovery circuits from a single 1.2-V supply.