Low temperature Si/Si wafer direct bonding using a plasma activated method

Manufacturing and integration of micro-electro-mechanical systems (MEMS) devices and integrated circuits (ICs) by wafer bonding often generate problems caused by thermal properties of materials. This paper presents a low temperature wafer direct bonding process assisted by O₂ plasma. Silicon wafers were treated with wet chemical cleaning and subsequently activated by O₂ plasma in the etch element of a sputtering system. Then, two wafers were brought into contact in the bonder followed by annealing in N₂ atmosphere for several hours. An infrared imaging system was used to detect bonding defects and a razor blade test was carried out to determine surface energy. The bonding yield reaches 90%–95% and the achieved surface energy is 1.76 J/m² when the bonded wafers are annealed at 350 °C in N₂ atmosphere for 2 h. Void formation was systematically observed and elimination methods were proposed. The size and density of voids greatly depend on the annealing temperature. Short O₂ plasma treatment for 60 s can alleviate void formation and enhance surface energy. A pulling test reveals that the bonding strength is more than 11.0 MPa. This low temperature wafer direct bonding process provides an efficient and reliable method for 3D integration, system on chip, and MEMS packaging.     

Fabrication of silicon and oxide membranes over cavities usingion-cut layer transfer

Silicon and oxide membranes were fabricated using an ion-cut layer transfer process, which is suitable for sub-micron-thick membrane fabrication with good thickness uniformity and surface micro-roughness. After hydrogen ions were implanted into a silicon wafer, the implanted wafer was bonded to another wafer that has patterned cavities of various shapes and sizes. The bonded pair was then heated until hydrogen-induced silicon layer cleavage occurred along the implanted hydrogen peak concentration, resulting in the transfer of the silicon layer from one wafer to the other. Using this technique, we have been able to form sealed cavities and channels of various shapes and sizes up to 50-μm wide, with a 1.6-μm-thick silicon membrane. As a process variation, we have also fabricated silicon dioxide membranes for optically transparent applications     

Glass Blowing on a Wafer Level

A fabrication process for the simultaneous shaping of arrays of glass shells on a wafer level is introduced in this paper. The process is based on etching cavities in silicon, followed by anodic bonding of a thin glass wafer to the etched silicon wafer. The bonded wafers are then heated inside a furnace at a temperature above the softening point of the glass, and due to the expansion of the trapped gas in the silicon cavities the glass is blown into three-dimensional spherical shells. An analytical model which can be used to predict the shape of the glass shells is described and demonstrated to match the experimental data. The ability to blow glass on a wafer level may enable novel capabilities including mass-production of microscopic spherical gas confinement chambers, microlenses, and complex microfluidic networks     

Bonded thick film SOI with pre-etched cavities

We have studied direct bonding and thinning of pre-etched silicon wafers. Silicon-on-insulator (SOI) substrates with pre-etched cavities provide freedom to MEMS design and enable manufacturing of advanced sensor structures (sensor structures that would be difficult or impossible with conventional substrates). Cavities with different shapes and sizes were etched on to the handle wafers. The etched handle wafers were bonded to unpatterned cap wafers in air or in vacuum. The bonding quality was evaluated with scanning acoustic microscopy and with HF-etching test. After bonding, the cap wafers were thinned down with grinding and polishing. The thickness variation of silicon diaphragm over the cavities was evaluated with cross-sectional SEM. The deflection of the Si film was measured with surface profilometry. To decrease the deflection and the thickness variation of the film, different support structures were placed inside the cavities.The bonding experiments carried out with patterned wafers showed that vacuum bonding results in slightly higher bonding energy than bonding in air. With large cavity fraction (80% of total wafer area), the air bonded samples had large void on the bonded interface. With smaller cavity fractions or with vacuum bonded samples, no such voids were found. Thinning studies showed that the thickness variation of the silicon diaphragm increases with increasing cavity dimensions and with decreasing SOI layer thickness. Thickness variation can be reduced with support structures under the Si membrane.     

Low temperature silicon direct bonding for application in micromechanics: bonding energies for different combinations of oxides

Plain or structured hydrophillic silicon wafers covered with native oxide or with thermally grown oxide layers have been directly bonded at room temperature; afterwards, the samples were annealed at 100°C to 400°C. There is a significant difference in the observed bonding energy depending on the wafer pairing chosen. If one or both wafers are covered with a native oxide layer, high bonding strengths are reached even at low temperatures. This can be explained by the different diffusion behaviour of water molecules through a thick thermal oxide layer on one hand, and through a thin native oxide layer on the other hand. Two different methods for the activation of the wafer surfaces just prior to bonding are described.     

Flexible integration of MEMS and IC for low-cost production of wireless sensor nodes

In this paper, we proposed a flexible process for size-free MEMS and IC integration with high efficiency for MEMS ubiquitous applications in wireless sensor network. In this approach, MEMS and IC can be fabricated individually by different wafers. MEMS and IC known-good-dies (KGD) are temporarily bonded onto carrier wafer with rapid and high-accurate self-alignment by using fine pattern of hydrophobic surface assembled monolayer and capillary force of H₂O; and then KGD are de-bonded from carrier wafer and transferred to target wafer by wafer level permanent bonding with plasma surface activation to reduce bonding temperature and load force. By applying above 2-step process, size of both wafer and chip could be flexible selected. Besides, CMOS processed wafer or silicon interposer can be used as the target wafer. This approach offers us excellent process flexibilities for low-cost production of wireless sensor nodes.     

Micro-mixer device with deep channels in silicon using modified RIE process: fabrication,packaging and characterization

In the present work, silicon based micromixer microfluidic devices have been fabricated in silicon substrates of 2-inch diameter. These devices are of 2-input and 1-output port configuration bearing channel depth in the range 80–280 µm. Conventional reactive ion etching (RIE) process used in integrated circuit fabrication was modified to get reasonably high silicon etch rate (~1.2 µm/min). It was anticipated that devices with channel depth in excess of 150 µm would become weak and susceptible to breakage. For such devices, a bonded pair of silicon having a 0.5 µm SiO₂ at the bonded interface was used as the starting substrate. The processed silicon wafer bearing channels was anodically bonded to a Corning^® 7740 glass plate of identical size for fluid confinement. Through-holes for input/output ports were made either in Si substrate or in glass plate before carrying out anodic bonding. Micro-channels were characterized using stylus and optical profiler. Surface roughness of the channel was observed to increase with increasing channel depth. The devices were packaged in a polycarbonate housing and pressure drop versus flow rate measurements were carried out. Reynolds number and friction factor were calculated for devices with 82 µm deep channels. It was observed that up to 25 sccm of gas and 10 ml/min of liquid, the flow was laminar in nature. It is envisaged that using bonded silicon wafer pair and combination of RIE and wet etching, it is possible to get an etch stop at the SiO₂ layer of the bonded silicon interface with much smaller value of surface roughness rendering smooth channel surface.     

Wafer direct bonding with ambient pressure plasma activation

Ambient pressure plasma processes were applied for surface activation of semiconductor (Si, Ge and GaAs) and other wafers (glass) before direct wafer bonding for MEMS and engineered substrates. Surface properties of activated wafers were analysed. Caused by activation high bond energies were obtained for homogeneous (e.g. Si/Si) as well as for heterogeneous material combinations (for instance Si/Ge) after a subsequent low temperature annealing process at 200°C. The resulting bond energies are analogous or higher as obtained for low-pressure plasma activation processes. The advantages of the ambient pressure plasma processes are described; a technical solution is discussed demonstrating the low risk for contamination and radiation damage.     

Non-destructive in situ test for anodic bonding

New test structures have been designed, fabricated and tested to monitor the quality of the anodic bonding between silicon and glass. The main advantage of the described test is that it is not destructive and allows the bond quality to be monitored in processed wafers. This test is very easy to implement in a chip or in a wafer because of its simplicity. Test structures consist of a matrix of circular and rectangular cavities defined by reactive ion etching (RIE) on the silicon wafer, with different sizes and depths. The bonding process and quality can be monitorized by the measurement of the size of the smallest bonded cavity and the distance between the bonded area and the cavity border. These structures give information about the level of electrostatic pressure that has been applied to pull together into intimate contact the surfaces of the two wafers. The higher the electrostatic pressure, the better the bond. We have applied these test structures to study the influence of the voltage and the temperature on the anodic bonding process. Results are in good agreement with finite-element method (FEM) simulations.     

Low temperature wafer direct bonding

A pronounced increase of interface energy of room temperature bonded hydrophilic Si/Si, Si/SiO₂, and SiO₂/SiO ₂ wafers after storage in air at room temperature, 150°C for 10-400 h has been observed. The increased number of OH groups due to a reaction between water and the strained oxide and/or silicon at the interface at temperatures below 110°C and the formation of stronger siloxane bonds above 110°C appear to be the main mechanisms responsible for the increase in the interface energy. After prolonged storage, interface bubbles are detectable by an infrared camera at the Si/Si bonding seam. Desorbed hydrocarbons as well as hydrogen generated by a reaction of water with silicon appear to be the major contents in the bubbles. Design guidelines for low temperature wafer direct bonding technology are proposed     

A new method for fast anodic bonding in microsystem technology

Other than temperature and voltage, load plays a key role in anodic bonding process. In this paper we present a new design of top electrode (cathode) for anodic bonding machine by which the bonding time has been reduced up to 30 % in case of bare silicon wafer at ?400 V and approximate 52 % in case of oxidized silicon wafer with Pyrex glass bonding at ?800 V. Experimentally it has been observed there was no bonding in oxidized silicon wafer with Pyrex glass up to ?600 V by using standard design while it has been successfully bonded at same voltage (?600 V) by using new design.     

碳化硅直接键合机理及其力学性能研究

随着碳化硅(SiC)材料的MEMS器件在恶劣环境测量中的应用前景和迫切需求,进行了碳化硅的直接键合实验.研究了工艺条件对键合样品力学性能的影响,同时借助激光共聚焦扫描显微镜(CLSM)、扫描电子显微镜(SEM)、能谱仪(EDS)和拉曼光谱仪等对碳化硅键合样品界面的微观结构进行了分析.结果表明:退火温度和加载压力是影响键合效果的关键性因素.当退火温度为1 300℃,加载压力为3 MPa和退火时间为3 h时,此时键合样品的气密性非常好,力学性能达到最佳,键合强度2 MPa.最后通过样品微观界面分析表明碳化硅直接键合的机理为界面氧化硅过渡层的形成及粘性流动与碳化硅和碳化硅的熔融直接键合.     

Characterization of wafer-level thermocompression bonds

Thermocompression bonding joins substrates via a bonding layer. In this paper, silicon substrates were bonded using gold thin films. Experimental data on the effects of bonding pressure (30 to 120 MPa), temperature (260 and 300/spl deg/C), and time (2 to 90 min) on the bond toughness, measured using the four-point bend technique, are presented. In general, higher temperature and pressure lead to higher toughness bonds. Considerable variation in toughness was observed across specimens. Possible causes of the nonuniform bond quality were explored using finite element analysis. Simulation results showed that the mask layout contributed to the pressure nonuniformity applied across the wafer. Finally, some process guidelines for successful wafer-level bonding using gold thin films are presented.     

Low-temperature wafer bonding: a study of void formation and influence on bonding strength

The void formation has been systematically observed for low-temperature (120/spl deg/C and 400/spl deg/C) Si-Si and SiO/sub 2/-SiO/sub 2/ wafer bonding techniques in function of the annealing time (from 70 to 595 h), pressure (low vacuum and atmospheric) and surface pretreatments. Mixed solution (H/sub 2/SO/sub 4/ and H/sub 2/O/sub 2/) standard cleaning, warm nitric acid and O/sub 2/-plasma-assisted surface pretreatments have been considered and compared. The void formation is clarified according to the void distribution and the measurement of surface energy. Long annealing time periods are considered in order to reach the saturation of the interface chemical reactions. Our experiments demonstrate that the origin of voids appearing in low temperature O/sub 2/-plasma-enhanced wafer bonding is related to the great quantity of chemical reaction products. It has been shown that optimized O/sub 2/-plasma pretreatment time can lead to void-free, uniform and high surface energy (over 2.0 J/m/sup 2/) wafer bonding. In the case of SiO/sub 2/-SiO/sub 2/ wafer bonding, our experimental results show that below a certain critical silicon dioxide thickness the reaction products cannot be absorbed totally and then voids occur. Presenting a higher surface energy than warm nitric acid O/sub 2/-plasma is an extremely promising surface pretreatment solution for the increasing demand of low-temperature wafer bonding techniques.     

Effect of bonding temperature on hermetic seal and mechanical support of wafer-level Cu-to-Cu thermo-compression bonding for 3D integration

Hermetic seal and mechanical support of wafer-level Cu-to-Cu thermo-compression bonding with different bonding temperature are analyzed in this work. The investigation consists of two parts: hermetic seal study using helium bomb test and mechanical support study using four-point bending method. The wafer pairs are bonded at 250, 300 and 350 °C, respectively, under a bonding force of 5,500 N for a duration of 1 h in vacuum (~2.5 × 10^?4 mbar). The bonding medium consists of Cu (300 nm) bonding layer and Ti (50 nm) barrier layer. Excellent helium leak rate, which is smaller than the reject limit defined by MIL-STD-883E standard (method 1014.10), and outstanding interfacial adhesion energy are detected for all samples. The cavities sealed at 300 °C present an excellent reliability of temperature cycling test up to 500 cycles. Cu-to-Cu thermo-compression bonding at low temperature (≤300 °C) presents an attractive hermetic seal and a robust mechanical support for 3D integration application.     

Steady-state measurement of wafer bonding cracking resistance

A steady-state wedge-opening test has been developed in order to measure the fracture toughness of bonded silicon wafers. Comparison between non-steady-state and steady-state tests is performed. The importance of allowing the rotation of the testing stage is discussed and appears to be essential in order to have the wedge perfectly aligned with the sample. Significant influence of (1) surface treatment; (2) thermal annealing; and (3) crack velocity on the toughness is observed for Si/Si wafer bonding and related to the interface chemistry.     

Adhesive wafer bonding with photosensitive polymers for MEMS fabrication

Adhesive wafer bonding is a technique that uses an intermediate layer (typically a polymer) for bonding two substrates. The main advantages of using this approach are: low temperature processing (maximum temperatures lower than 400°C), surface planarization and tolerance to particles contamination (the intermediate layer can incorporate particles with the diameter in the layer thickness range). The main bonding layers properties required by a large field of applications/designs can be summarized as: isotropic dielectric constants, good thermal stability, low Young’s modulus, and good adhesion to different substrates. This paper reports on wafer-to-wafer adhesive bonding using SINR^TM polymer materials. Substrate coating process as well as wafer bonding process parameters optimization was studied. Statistical analysis methods were used to show repeatability and reliability of coating processes. Features of as low as 15 μm size were successfully resolved by photolithography and bonded. An unique megasonic-enhanced development process of the patterned film using low cost solvent was established and proven to exceed standard development method performance.     

Stamp-and-stick room-temperature bonding technique for microdevices

Multilayer MEMS and microfluidic designs using diverse materials demand separate fabrication of device components followed by assembly to make the final device. Structural and moving components, labile bio-molecules, fluids and temperature-sensitive materials place special restrictions on the bonding processes that can be used for assembly of MEMS devices. We describe a room temperature "stamp and stick (SAS)" transfer bonding technique for silicon, glass and nitride surfaces using a UV curable adhesive. Alternatively, poly(dimethylsiloxane) (PDMS) can also be used as the adhesive; this is particularly useful for bonding PDMS devices. A thin layer of adhesive is first spun on a flat wafer. This adhesive layer is then selectively transferred to the device chip from the wafer using a stamping process. The device chip can then be aligned and bonded to other chips/wafers. This bonding process is conformal and works even on surfaces with uneven topography. This aspect is especially relevant to microfluidics, where good sealing can be difficult to obtain with channels on uneven surfaces. Burst pressure tests suggest that wafer bonds using the UV curable adhesive could withstand pressures of 700 kPa (7 atmospheres); those with PDMS could withstand 200 to 700 kPa (2-7 atmospheres) depending on the geometry and configuration of the device.     

Low-temperature bonding of thick-film polysilicon for microelectromechanical system (MEMS)

Polysilicon thick films have been found to be an irreplaceable option in various sensors and other microelectromechanical system (MEMS)-designs. Polysilicon is also a prospective option for replacing single-crystal silicon in customized silicon-on-insulator-substrates. Due to the nature of polysilicon, bonding for MEMS-purposes has so far concentrated on anodic bonding, which has drawbacks for instance in terms of process duration and thermal load. The objective of this work is to develop low-temperature direct bonding for various polysilicon films. Polysilicon films were grown at varying temperatures and pressures with and without boron doping. The films were polished by chemical–mechanical polishing and cleaned. Surface qualities were studied by atomic-force-microscope before bonding. Wafers were then activated with argon plasma and bonded to oxidized silicon, quartz and glass. Bonding quality was evaluated with scanning-acoustic-microscope, the crack-opening-method and HF-etching. Scanning-electron-microscopy was used to investigate film and interface quality. This development has led to a new kind of polishing process, where several microns of polysilicon are removed still leaving surface direct bondable. This is accomplished by a dedicated and effectively planarizing polishing process. Spontaneous bonding took place and good bonding quality was achieved after annealing at 200°C.