共查询到20条相似文献,搜索用时 15 毫秒
1.
Peter Aronhime KeChang Wang Tongfeng Qian 《Analog Integrated Circuits and Signal Processing》2001,28(1):27-34
A current feedback op-amp (CFOA) has the advantage that feedback structures in current-mode circuits are more easily devised because the voltage buffer at the output of the CFOA does not load the output of the integral positive, second-generation current conveyor (CCII+) that constitutes part of the CFOA. In this paper, the changes on the current mode transfer function of a linear circuit composed of a subnetwork
connected to a CCII+ are determined when the CCII+ is replaced by a CFOA and a feedback component is connected from the output of the CFOA to an independent node of
. Two applications of the results are provided. A new theorem is then presented which generalizes the results. This theorem should be useful for the comparison, synthesis, and improvement of linear current-mode signal processing circuits. 相似文献
2.
Uğur Çam Oğuzhan Çiçekoğlu Ali Toker Hakan Kuntman 《Analog Integrated Circuits and Signal Processing》2001,28(3):299-307
In this study, five current-mode FTFN-based multifunction filters are proposed, which realize the same transfer functions in ideal case. All circuits employ two capacitors and three resistors. For each circuit R-C:C-R transformation increases the number of realization possibilities to ten. The proposed topologies simultaneously realize three basic filtering functions using minimum number of FTFNs and provide high output impedances that enable easy cascading in current mode. Sensitivity analysis of the filters show that they have low passive sensitivities,
and
of the filters are insensitive to current tracking errors, furthermore
of the filters are insensitive to voltage tracking errors of the FTFNs. The proposed circuits do not require component matching condition except for notch and allpass responses and permit independent adjustment of
without disturbing
. Experimental and simulation results are given to verify the theoretical analyses. 相似文献
3.
Yuyu Chang John Choma Jr. Jack Wills 《Analog Integrated Circuits and Signal Processing》2001,28(1):43-52
A CMOS inductorless image-reject filter based on active RLC circuitry is discussed and designed with the emphasis on low-noise, low-power, and gigahertz-range circuits. Two
-enhancement techniques are utilized to circumvent the low
characteristics inherent in the simple feedback circuit. The frequency tuning is almost independent of
tuning, facilitating the design of the automatic tuning circuitry. The stability and the tuning scheme of the filter are also discussed. Simulations using 0.6 m CMOS technology demonstrate the feasibility of the tunable image-reject filter for GSM wireless applications. Simulation results show 4.75 dB voltage gain, 9.5 dB noise figure, and –20 dBm IIP3 at a passband centered at 947 MHz. The image signal suppression is 60 dB at 1089 MHz and the power consumption is 27 mW. 相似文献
4.
The statistical design of the four-MOSFET structure is presented in this paper. The quantitative measure of the effect of mismatch between the four transistors on nonlinearity and offset current is provided through contours. Statistical optimization of the transistor
and
values is demonstrated. The four-MOSFET structure was fabricated through the MOSIS 2 m process using MOS transistor Level-3 model parameters. Experimental results are included in the paper. 相似文献
5.
A 900 MHz low-power CMOS bandpassamplifier suitable for the applications of RFfront-end in wireless communication receiversis proposed and analyzed. In this design, thetemperature compensation circuit is used tostabilize the amplifier gain so that theoverall amplifier has a good temperaturestability. Moreover, the compact tunablepositive-feedback circuit is connected to theintegrated spiral inductor to generate thenegative resistance and enhance its
value. The simple diode varactor circuit isadopted for center-frequency tuning. These twoimproved circuits can reduce the powerdissipation of the amplifier. An experimentalchip fabricated by 0.5 mdouble-poly-double-metal CMOS technologyoccupies a chip area of
; chip area. The measuredresults have verified the performance of thefabricated CMOS bandpass amplifier. Under a2-V supply voltage, the measured quality factoris tunable between 4.5 and 50 and the tunablefrequency range is between 845 MHz and 915 MHz. At
, the measured
is 20 dB whereas thenoise figure is 5.2 dB in the passband. Thegain variation is less than 4 dB in the rangeof 0–80°C. The dc powerdissipation is 35 mW. Suitable amplifier gain,low power dissipation, and good temperaturestability make the proposed bandpass amplifierquite feasible in RF front-endapplications. 相似文献
6.
A 5.8 GHz Low Noise Amplifier for Wireless LAN Applications in Silicon Bipolar Technology 总被引:1,自引:0,他引:1
Gerd Schuppener Mehran Mokhtari Boris Kerzar 《Analog Integrated Circuits and Signal Processing》2001,27(1-2):129-136
A monolithic integrated low-noise amplifier for operation in the 5.8-GHzband is described. Two different versions have been implemented where the biasing wasadapted to allow operation over a different range of supply voltage. At 5-V, theamplifiers gain is about 17-dB, with a noise figure of 4.2-dB and 1-dB compressionpoint at –15-dBm input power. The circuits have been designed utilizing a0.6-micron silicon bipolar production technology, featuring npn transistors with
and
of about20-GHz. 相似文献
7.
Arturo Sarmiento-Reyes Octavio González-Castolo 《Analog Integrated Circuits and Signal Processing》2001,28(1):123-129
A fundamental problem of symbolic analysis of electric networks when using the signal-flow (SFG) graph method is to find the common tree of the current and voltage graph (
and
, respectively). In this paper we introduce a novel method in order to determine a common tree of both graphs, which may be used to obtain the symbolic network transfer function when carrying out the small-signal analysis of linear(ised) circuits. 相似文献
8.
A Fully Integrated, Low Noise and Low Power BiCMOS Front-end Readout System for Capacitive Detectors 总被引:1,自引:0,他引:1
Chaoying-Christine Guo Philippe Schmitt Grzegorz Deptuch Yongcai-Yann Hu 《Analog Integrated Circuits and Signal Processing》2001,28(3):211-223
Bipolar transistors are interesting for low noise front-end readout systems when high speed and low power consumption are required. This paper presents a fully integrated, low noise front-end design for the future Large Hadron Collider (LHC) experiments using the radiation hard SOI BiCMOS process. In the present prototype, the input-referred Equivalent Noise Charge (ENC) of 990 electrons (rms) for 12 pF detector capacitance with a shaping time of 25 ns and power consumption of 1.4 mW/channel has been measured. The gain of this front-end is 90 mV/MIP (Minimum Ionisation Particle: 1
fC) with non-linearity of less than 3% and linear input dynamic range is
MIP. These results are obtained at room temperature and before irradiation. The measurements after irradiations by high intensity pion beam with an integrated flux of
pions/cm2 are also presented in this paper. 相似文献
9.
A novel figure of merit to describe the bandwidth power efficiency of CMOS transconductors—
is proposed and optimized for cross-coupled differential pair transconductor structures. The optimization is done in two different ways: univariable unconstrained and multivariable constrained. It is revealed that not only dc biases but also ac input phases can affect the bandwidth power efficiency of the transconductor. The bias voltages which can lead to best
ratio at different ac phase combinations are obtained and presented in the article. HSPICE simulations are conducted to verify the theoretical predictions. On the basis of the cross-coupled differential pair transconductor, a biquadratic transconductor-C filter configuration is implemented. The frequency vs. power characteristic of the filter is studied for both optimally- and non-optimally-biased transconductor. It is shown that the
optimization of the transconductor structure can result in performance improvement of the transconductor-C filter. The deviation of the optimal bias condition between the transconductor alone and the transconductor-C filter due to the inclusion of peripheray circuitries in the filter is discussed in the article. 相似文献
10.
Charalampos Kapnistis Konstantinos Misiakos Nikos Haralabidis 《Analog Integrated Circuits and Signal Processing》2001,27(1-2):39-49
A charge sensitive readout chain has been designed and fabricated in acommercially available 0.8 m CMOS technology. The readout chain is optimizedfor pixel detectors measuring soft X-ray energies up to 20 KeV. In the first modean analog signal proportional to input charge is generated and processed in realtime. In the second mode a peak-and-hold operation is enabled and therelevant signal is processed in later time. This dual mode of operation iscontrolled by an external digital signal. The readout chain consists of a chargeamplifier, a shaper, an operational amplifier which can either operate as avoltage amplifier or a peak detector and an output buffer. Its area is
. The gain at the shaper output is 378 mv/fC, theENC is 16
rms at 160 nsec shaping time. The overall gainis 557 mV/fC, the ENC is
rms with 240 nsec peaking timeand 1.4 sec recovery time. The overall power dissipation is 1.5 mWatt with aload capacitance of 25 pF. 相似文献
11.
Maria Alessandra Fasoli 《Multidimensional Systems and Signal Processing》1998,9(3):291-306
Let K be a field, k and n positive integers and let
matrices with coefficients in K. For any function
there exists a unique solution
of the system of difference equations
defined by the matrix-k-tuple
such that
. The system
is called finite-memory system iff for every function g with finite support the values
are 0 for sufficiently big
. In the case
, these systems and the corresponding matrix-k-tuples have been studied in bis, fm, fmv, fv1, fv, fz. In this paper I generalize these results to an arbitrary positive integer k and to an arbitrary field K. 相似文献
12.
Tomerlin Andrew T. Edmonson William W. 《Multidimensional Systems and Signal Processing》2002,13(3):333-340
Consider the class of d-dimensional causal filters characterized by a d-variate rational function
analytic on the polydisk
. The BIBO stability of such filters has been the subject of much research over the past two decades. In this paper we analyze the BIBO stability of such functions and prove necessary and sufficient conditions for BIBO stability of a d-dimensional filter. In particular, we prove if a d-variate filter H(z) analytic on
has a Fourier expansion that converges uniformly on the closure of
, then H(z) is BIBO stable. This result proves a long standing conjecture set forth by Bose in [3]. 相似文献
13.
In this paper we investigate -bit serial addition in the context of feed-forward linear threshold gate based networks. We show that twon-bit operands can be added in
overall delay with a feed-forward network constructed with
linear threshold gates and
latches. The maximum weight value is
and the maximum fan-in is
. We also investigate the implications our scheme have to the performance and the cost under small weights and small fan-in requirements. We deduce that if the weight values are to be limited by a constantW, twon-bit operands can be added in
overall delay with a feed-forward network that has the implementation cost [logW]+1, in terms of linear threshold gates,
in terms of latches and a maximum fan-in of 3[logW]+1. We also prove that, if the fan-in values are to be limited by a constantF+1, twon-bit operands can be added in
overall delay with a feed-forward network that has the implementation cost
, in terms of linear threshold gates,
in terms of latches, and a maximum weight value of
. An asymptotic bound of
is derived for the addition overall delay in the case that the weight values have to be linearly bounded, i.e., in the order ofO(n). The implementation cost in this case is in the order ofO(logn), in terms of linear threshold gates, and in the order ofO(log2
n), in terms of latches. The maximum fan-in is in the order ofO(logn). Finally, a partition technique, that substantially reduces the overall cost of the implementation for all the schemes in terms of delay, latches, weights, and fan-in with some few additional threshold gates, is also presented. 相似文献
14.
Celestino A. Corral Claude S. Lindquist 《Analog Integrated Circuits and Signal Processing》2001,28(1):53-62
The problem of determining the band-edge selectivity of elliptic filters and its optimization in filter design is considered. The band-edge selectivity is derived with respect to the
-th order elliptic function. The selectivity formula embodies potential trade-offs in filter requirements for improving filter mangitude or delay response. Design examples are submitted in support of the theory. A simple proof describes the Chebyshev filter as an elliptic filter in the limit of infinite stopband corner frequency. 相似文献
15.
B. Graindourze S. Blieck H. Casier J. P. Bardyn 《Analog Integrated Circuits and Signal Processing》1992,2(1):33-42
This paper describes the design of three high-performance op amps in a 40V BiCMOS technology. The first circuit is a low-noise op amp with MOS inputs. A thermal noise level as low as
with a 1/f noise corner frequency of 100 Hz is achieved. For applications that can tolerate a lower input impedance, a more economical bipolar input low-noise op amp has been designed, yielding an even better noise performance for source impedances up to 20 k. The third circuit is an internally compensated high-gain-bandwidth (GBW=15 MHz) op amp that can drive loads from 0 to 20 pF. A fourth-order low-pass switched-capacitor filter making use of the latter op amp is discussed next. Finally the applications of this 40V BiCMOS process are illustrated. 相似文献
16.
Masakazu Katsuno Noboru Ohtani Tatsuo Fujimoto Hirokatsu Yashiro 《Journal of Electronic Materials》2005,34(1):91-95
The effect of off-orientation growth has been investigated in terms of stacking fault formation during physical vapor transport
(PVT) growth of silicon carbide (SiC) single crystals on the (11
0) seed crystal surface. Occurrence of stacking fault formation is largely dependent on the direction of off-orientation,
and basal plane stacking fault density is significantly reduced by growing the crystals on a (11
0) seed crystal off-oriented toward 〈0001〉. The density of the basal plane stacking faults rapidly decreases from 100–150
cm−1 to ∼10 cm−1 as the degree of off-orientation is increased from 0 to 10 deg. The results are interpreted in the framework of microscopic
facet formation during PVT growth, and the introduction of off-orientation of seed crystal is assumed to prevent (01
0) and (10
0) microfacet formation on the (11
0) growing surface through modification of the surface growth kinetics and to suppress the stacking fault formation.
An erratum to this article is available at . 相似文献
17.
In pacemaker design the mainconcerns are reliability, functionality,operating life and miniaturization. Afundamental role in miniaturization is dueto the increased circuit integration; hencelow power circuit solutions that can beintegrated in sub-micron CMOS technology arehighly desirable. This work proposes avoltage multiplier suitable for pulse outputgeneration in an implantable pacemaker,implemented in a standard, low-cost CMOS 0.8 m technology. The circuit can operatewithin a supply voltage range of 2.8 V to 2V, corresponding to the voltage capabilityprovided by the single lithium iodine cell,ubiquitously used in pacemaker. Fineprogrammability of the output has beenachieved, thus allowing the choice of theoptimum tradeoff between stimulationefficacy and battery longevity. Moreover theproposed solution takes care of minimizingthe parasitic coupling and disturbancesbetween the charge pump and other blocks inthe system. Finally the measured steady statecurrent consumption is smaller than
. 相似文献
18.
This paper considers the problem of constructing feedback stabilizing controllers for the wave operator on
n (more generally AR systems determined by a hyperbolic operator). In order to accomplish this, it must first clarify the notion of an input-output structure on a distributed system, as well as what it means to interconnect two such systems. Both these notions are shown to be consequences of a structure which generalizes the standard causal structure of lumped systems determined by the flow of time. Given this apparatus, the paper then constructs feedback controllers which stabilize the wave equation along directions given by a proper cone in
n. 相似文献
19.
We propose using the TCP decoupling approach to improve a TCP connection's goodput over wireless networks. The performance improvement can be analytically shown to be proportional to
, where MTU is the maximum transmission unit of participating wireless links and HP_Sz is the size of a packet containing only a TCP/IP header. For example, on a WaveLAN [32] wireless network, where MTU is 1500 bytes and HP_Sz is 40 bytes, the achieved goodput improvement is about 350%. We present experimental results demonstrating that TCP decoupling outperforms TCP reno and TCP SACK. These results confirm the analysis of
performance improvement. 相似文献
20.
In this paper several examples of circuits obtained with an automatic synthesis algorithm will be shown. The algorithm, described in a companion paper [1] and outlined here for clarity, has been implemented in the Mathematica
language. We applied the new algorithm to classical problems of inmittance synthesis, obtaining well known topologies and also non-reported structures. When the algorithm is applied to challenging new problems, novel and practically useful inmittances are synthesized. 相似文献