The impact of supercomputers on IC technology development and design

Very large scale integration (VLSI) has evolved at an enormous rate, progressing from hundreds of components on an integrated circuit (IC) in the 1960's to a million components on a chip in the foreseeable future. This paper reviews some of the computer-aided design (CAD) tools that are essential for VLSI technology development and circuit design and that also require large amounts of computer resources. Specifically, we describe programs for process simulation, device simulation, and circuit simulation. This paper also reviews the impact of high-performance computing facilities on the development and use of these programs at AT & T Bell Laboratories.     

Tools for the computer-aided design of multigigahertzsuperconducting digital circuits

The realization of large integrated circuits depends upon the application of computer-aided design (CAD) tools. This paper summarizes the results of a survey of CAD tools targeting superconducting digital electronics. Five categories of tools: circuit simulators, circuit optimizers, layout tools, inductance estimators, and logic simulators are discussed in detail. Within each category, a comparison of several currently available CAD tools is presented, and a tool which has been adapted for use or developed at the University of Rochester is discussed in greater detail. In addition, tools for timing analysis as well as integrated design environments that permit the effective data interchange among various tools and support libraries of design models are discussed. Future tools for timing optimization, automated logic synthesis, and automated layout synthesis are shown to be necessary for the design of superconducting circuits at the very large scale of integration (VLSI) level of integration. Trends regarding changes in the requirements for effective CAD tools are discussed, and expected improvements to existing tools and features of new tools currently under development are presented     

VLSI计算机辅助设计框架──面向对象的DO模型及EOIDE框架的开发

本文叙述了一种新的集成电路计算机辅助设计框架的设计思想：提出了符合集成电路设计需要的新的四维数据模型，并设计了面向对象的工程数据库；提出了便于在框架中集成已开发完成的ＩＣ设计工具的松耦合的集成方式。讨论了用户管理、设计数据的版本管理以及在层次设计、多用户环境下的并发控制等在框架实施中的问题，提出了处理方案。基于上述思想，在ＨＰ／８００工作站ＵＮＩＸ操作系统下开发了集成电路设计框架ＥＯＩＤＥ（Ｅｎｔｉｔｙ－ＯｒｉｅｎｔｅｄＩＣＩｎｔｅｇｒａｔｅｄＤｅｖｅｌｏｐｍｅｎｔＥｎｖｉｒｏｎ－ｍｅｎｔ），并在框架上装入了单层门阵列设计工具（ＥＮＹＡ），设计了单层门阵列电路，结果良好。     

Coupling effects on wire delay. Challenges in deep submicron VLSIdesign

Coupling is a complex phenomenon, especially where the high-gain coupling effect is concerned. To introduce coupling effects on wire delay, including the high-gain coupling effect, this article presents a generalization of a study that evolved from a real VLSI design. Possible solutions to coupling effects such as CAD tools, circuit design methodology, and circuit design techniques are also discussed. The conclusions and results presented in this article are based on current complementary metal oxide semiconductor (CMOS) technologies     

Computer-aided design in VLSI device development

Computer-aided design (CAD) has been used extensively in the development of VLSI MOS technology at Hewlett-Packard Laboratory. The CAD system for MOS device design is described. The development of the p-channel transistor with submicrometer channel length, trench isolation in CMOS, and side-wall-masked isolation (SWAMI) for VLSI technology are then presented, followed by a discussion of the techniques used in the simulation of parasitic capacitances in multilayer interconnects for circuit performance evaluations.     

Custom design of a VLSI PCM-FDM transmultiplexer from system specifications to circuit layout using a computer-aided design system

The computer-aided design of a VLSI PCM-FDM transmultiplexer is presented. The entire design process, from system specifications to integrated circuit layout, is carried out with the aid of specialized computer programs for the analysis, synthesis, and optimization at each design level: the filter network, the architecture, and the circuit layout. These CAD tools support a top-down custom design methodology based on bit-serial architectures and standard cells. A customized architecture is constructed which is integrated using a 5-/spl mu/m CMOS cell library. The results are compared with a fully manual design and demonstrate the power of architecture based computer-aided design methodologies for VLSI filtering. By combining both synthesis and optimization aids at each design level it is possible to achieve a high degree of automation while retaining an efficient use of silicon area, high throughput, and moderate power consumption.     

Computer-aided design of VLSI circuits

With the rapid evolution of integrated circuit (IC) technology to larger and more complex circuits, new approaches are needed for the design and verification of these very-large-scale integrated (VLSI) circuits. A large number of design methods are currently in use. However, the evolution of these computer aids has occurred in an ad hoc manner. In most cases, computer programs have been written to solve specific problems as they have exist and no truly integrated computer-aided desisn (CAD) systems exist for the design of IC's. A structured approach both to circuit desisn and to circuit verification, as well as the development of integrated design systems, is necessary to produce cost-effective error-free VLSI circuits. This paper presents a review of the CAD techniques which have been used in the design of IC's, as well as a number of design methods to which the application of computer aids has proven most successful. The successful application of design-aids to VLSI circuits requites an evolution from these techniques and design methods.     

Technology transfer between VLSI design and software engineering: CAD tools and design methodologies

Recent research on the explicit transfer of technology used in computer-aided design (CAD) tools and design methodologies is reported. First, several examples are given of applications of these technologies to software engineering. Then, three research projects are described which focused on applying software engineering principles to the VLSI design process. They are: a methodology, language, and assessment tool for multilevel mixed-mode VLSI designs; a research project that explored the potential for transfer of software design methodologies for managing VLSI design complexity; and a specification technique for "modules" in a VLSI design that localizes the impact of changes to the design. Next, a CAD tool and design methodology are described which consider the design of software and hardware together, and apply common techniques to both. Finally, some observations are made on the appropriateness of technology transfer between VLSI design and software engineering.     

Design of a low-power, high performance, 8×8 bit multiplier using a Shannon-based adder cell

In this paper, we have developed a new full-adder cell using multiplexing control input techniques (MCIT) for the sum operation and the Shannon-based technique to implement the carry. The proposed adder cell is applied to the design of several 8-bit array multipliers, namely a Braun array multiplier, a CSA multiplier, and Baugh–Wooley multipliers. The multiplier circuits are designed using DSCH2 VLSI CAD tools and their layouts are generated by Microwind 3 VLSI CAD tools. The output parameters such as propagation delay, total chip area, and power dissipation are calculated from the simulated results. We have also calculated energy per instruction (EPI), throughput, latency, signal-to-noise ratio (SNR), and the effect of temperature on the drain current by using the generated layout output parameter of a BSIM 4 advanced analyzer. The simulated results of the proposed adder-based multiplier circuit are compared with a cell multiplier that utilizes a MCIT-based adder, a cell multiplier composed of complementary pass transistor logic-based (CPL) adders and those of other published multipliers circuits. From the analysis of these simulated results, it was found that the proposed multiplier circuit gives better performance in terms of power, propagation delay, latency and throughput than other published results.     

可用于微机上的VLSI设计软件-Alliance

本篇文章介绍了一种超大规模集成电路设计软件-Auiance VLSI CAD System通常设计超大规模集成电路必须有昂贵的软件诸如Cadence，Synopsys，Mentor Graphics，而且要在高性能的工作站上才能完成。然而Alliance不仅能成功的运用于微机上而且可以从互连网上免费下载因此Alliance这套软件给高等院校的学生学习集成电路的设计提供了许多低廉、有效的工具。我们将告诉读者如何在微机上安装Alliance，如何用Alliance来设计超大规模集成电路。     

硬件描述语言VHDL及其应用

ＶＨＤＬ是一种超高速ＶＬＳＩ硬件描述语言，能对集成电路的功能和结构进行描述，用ＣＡＤ软件将其编译和转换，并自动形成线路，概要地介绍了ＶＨＤＬ的设计组织和数据类型，并对ＶＨＤＬ的特点及其在ＶＬＳＩ设计中的应用要点做了一些探讨。     

A 300-MHz 115-W 32-b bipolar ECL microprocessor

A full-custom single-chip bipolar ECL RISC microprocessor was implemented in a 1.0-μm single-poly bipolar technology. This research prototype contains a CPU and on-chip 2-KB instruction and 2-KB data caches. Worst-case power dissipation with a nominal -5.2 V supply is 115 W. The chip has been designed for a worst-case clock frequency of 275 MHz at a nominal supply. The chip verifies a new style of CAD tools developed during the design process, advanced packaging techniques for high-power microprocessors, and VLSI ECL circuit techniques     

A general-purpose framework for CAD algorithms

The demands imposed by large circuits on computer-aided design (CAD) systems are discussed, showing how each can be met. In particular, it is shown how a CAD system can handle many tools, accommodation different design environments, provide a flexible interface, provide user-specified constraints, and be platform independent. A complete system, called the Electric VLSI Design System which exhibits all of these features is described     

微波电路原理图编辑工具及网表提取程序的实现方法

介绍了基于用于ＶＬＳＩＣＡＤ的熊猫系统，针对微波电路的特点进行修改和扩充，形成微波电路原理图编辑工具的方法。     

Computer-aided design for VLSI circuit manufacturability

It is noted that the nominal design created by CAD tools must often be modified to maximize manufacturing yield. Such maximization must be performed during the design to achieve an acceptable level of initial manufacturing yield and during fabrication to achieve the maximum rate of yield improvement in the entire product development cycle. The manufacturing-oriented component of the CAD of VLSI circuits is discussed. The concept of design for manufacturability is explained, and a number of issues and design problems relevant to achieving a high level of IC manufacturability are examined. An overview of needed and existing CAD tools that can be used to solve previously listed problems is presented     

Computer-Aided Design for Low-Power Robust Computing in Nanoscale CMOS

This work argues that the foremost challenges to the continued rapid improvements in CMOS integrated circuit (IC) performance are power consumption and design robustness. Furthermore, these two goals are often contradictory in nature, which indicates that joint optimization approaches must be adopted to properly handle both. To highlight needs in computer-aided design (CAD), we review a sampling of state-of-the-art work in power reduction techniques, and also in the newly emerging area of statistical optimization applied to very large scale integration (VLSI) ICs. The lack of CAD techniques to perform multiobjective function optimization (specifically parametric yield under correlated performance metrics) is a major limitation of current CAD research. In addition, with design trends pushing towards architectures based on aggressive adaptivity and voltage scaling, CAD researchers and engineers will need to refocus efforts on enabling this type of complex design     

Modified asynchronous wave-pipelining

A modified asynchronous wave-pipelining design method for optimising circuit performance is presented. Using this method, the number of latches in the circuit can be decreased compared with the asynchronous wave-pipelined circuit that uses latches at every gate level. As a result, the latency of the circuit can be reduced drastically and the number of delay elements used in the wave-pipelined circuit can be decreased. To verify the proposed method, the authors have designed and 8×8 multiplier and performed simulations using HSPICE. The latency of the multiplier decreased by 40% when compared with the asynchronous wave-pipelined circuit and a delay latch replaced two delay elements that were used in the wave-pipelined circuit. The designed multiplier works well at 1 GHz     

The DTI-industry sponsored Silicon Architectures ResearchInitiative

A significant national programme on the development of advanced software for VLSI system design is reported. The Silicon Architectures Research Initiative (SARI) is supported by selected UK electronics companies as well as the UK Department of Trade & Industry (DTI). It has resulted in the design and development of an interactive software suite for optimising a system implementation in VLSI circuit form. The new software permits a specific system design to be optimised in terms of chip speed or area prior to interfacing with one of the available commercial silicon layout tools