A method for numerical modelling of convection–reaction–diffusion using electrical analogues

In this paper, a new method, called the lumped‐component circuit method (LCM), is developed for one‐dimensioal and two‐dimensional convection–reaction–diffusion with low to moderate Peclet numbers, tested for modelling both steady‐state and transient problems, and compared with standard finite volume method (FVM) schemes. The method has been developed principally for solving equations with piecewise‐constant coefficients using nodes that are not positioned to correspond to the coefficient discontinuities. In such situations, the FVM solutions do not converge consistently as the node spacing is decreased, but LCM solutions do. In general, the LCM method is more accurate than the FVM schemes tested, and, while the computational cost of LCM is higher, results suggest that it can be more efficient. Like the transmission line method (TLM), it is an indirect scheme in which the problem to be solved is first represented by an analogous transmission line (TL). Unlike with TLM, however, the TL is then modelled using a lumped‐component circuit, the voltages at nodes within that circuit being calculated. Copyright © 2015 John Wiley & Sons, Ltd.     

On frequency response and stability of an optical front–end with variable‐gain current amplifier using a bipolar junction transistor translinear loop

A comparative analysis of implementations of an optical front–end with variable transimpedance intended for optical storage systems in two different BiCMOS technologies is given in this article. The variable‐gain current amplifier within the optical front–end is designed by using a modified balanced type of the bipolar junction transistors translinear loop. The predictions of the optical front–end mathematical models are confirmed by the measured results. They show that a 0.6‐µm BiCMOS silicon technology implementation with worse bipolar junction transistor parameters (unity‐gain frequency, current gain β, and the Early voltage) gives much better stability than a 0.35‐µm BiCMOS silicon‐germanium technology implementation. As a consequence, the useful measured transimpedance dynamic range of the proposed optical front–end is 17.5 times larger in the 0.6‐µm BiCMOS silicon technology than that in the 0.35‐µm BiCMOS silicon‐germanium technology. Copyright © 2012 John Wiley & Sons, Ltd.     

Analysis and implementation of a power management unit with a multiratio switched capacitor DC–DC converter for a supercapacitor power supply

An energy‐harvesting system requires an energy‐storing device to store the energy retrieved from the surrounding environment. Rechargeable batteries are commonly used to store this energy; however, because of the limited number of charge/discharge cycles, they need to be periodically replaced. A supercapacitor, which has, ideally, a limitless number of charge/discharge cycles, avoids this problem. In this case, it is required for the power management unit to produce a constant output voltage as the supercapacitor discharges. This paper presents a system with a multiratio switched capacitor DC–DC converter, in a 130‐nm technology, with a maximum output power of 2 mW, a maximum efficiency of 79.63% and a maximum output ripple, in the steady state, of 23 mV for an input voltage range of 2.3–0.87 V. The proposed converter has four operation states, to maximize its efficiency, that correspond to the conversion ratios of 1/2, 2/3, 1/1 and 3/2. Its clock frequency is automatically adjusted to produce a stable output voltage of 1 V. These features are implemented through two distinct controller circuits that use two asynchronous time machines to dynamically adjust the clock frequency and to select the active state of the converter. All the theoretical expressions as well as the behaviour of the whole system were verified by using electrical simulations. Copyright © 2016 John Wiley & Sons, Ltd.     

Fault detection for a class of network‐based nonlinear systems with communication constraints and random packet dropouts

This paper is dealt with the fault detection (FD) problem for a class of network‐based nonlinear systems with communication constraints and random packet dropouts. The plant is described by a Takagi–Sugeno fuzzy time‐delay model, it has multiple sensors and only one of them is actually communicated with the FD filter at each transmission instant, and the packet dropouts occur randomly. The goal is to design a FD filter such that, for all unknown inputs, control inputs, time delays and incomplete data conditions, the estimation error between the residual and ‘fault’ (or, more generally, the weighted fault) is minimized. By casting the addressed FD problem into an auxiliary H_∞ filtering problem of a stochastic switched fuzzy time‐delay system, a sufficient condition for the existence of the desired FD filter is established in terms of linear matrix inequalities. A numerical example is provided to illustrate the effectiveness and applicability of the proposed technique. Copyright © 2011 John Wiley & Sons, Ltd.     

Design and analysis of power‐CMOS‐gate‐based switched‐capacitor DC–DC converter with step‐down and step‐up modes

A unified multi‐stage power‐CMOS‐transmission‐gate‐based quasi‐switched‐capacitor (QSC) DC–DC converter is proposed to integrate both step‐down and step‐up modes all in one circuit configuration for low‐power applications. In this paper, by using power‐CMOS‐transmission‐gate as a bi‐directional switch, the various topologies for step‐down and step‐up modes can be integrated in the same circuit configuration, and the configuration does not require any inductive elements, so the IC fabrication is promising for realization. In addition, both large‐signal state‐space equation and small‐signal transfer function are derived by state‐space averaging technique, and expressed all in one unified formulation for both modes. Based on the unified model, it is all presented for control design and theoretical analysis, including steady‐state output and power, power efficiency, maximum voltage conversion ratio, maximum power efficiency, maximum output power, output voltage ripple percentage, capacitance selection, closed‐loop control and stability, etc. Finally, a multi‐stage QSC DC–DC converter with step‐down and step‐up modes is made in circuit layout by PSPICE tool, and some topics are discussed, including (1) voltage conversion, output ripple percentage, and power efficiency, (2) output robustness against source noises and (3) regulation capability of converter with loading variation. The simulated results are illustrated to show the efficacy of the unified configuration proposed. Copyright © 2003 John Wiley & Sons, Ltd.