Capacitance extraction for electrostatic multiconductor problems byon-surface MEI

In this paper, on-surface measured equation of invariance (OSMEI) method is implemented for capacitance extraction of electrostatic multiconductor interconnect problems. OSMEI uses the same mesh as that in method of moments (MoM), but generates highly sparse matrices rather than a full matrix. In comparison with “standard” MEI which contains a few finite difference (FD) or finite element (FE) mesh layers, the number of unknowns and the computation memory can be saved. For each OSMEI equation in the multiconductor interconnects, a given node on a given conductor is forced into coupling with the few adjacent nodes on conductor itself and the few sampled nodes on other conductors. Thus, the system sparse matrices can be generated. The convergent behavior of the capacitance with the number of the nodes in the OSMEI equations has been widely investigated, Numerical examples of the capacitance extraction for two-dimensional (2-D) and three-dimensional (3-D) multiconductor interconnects show that the computing errors are within 24%. The OSMEI method may become a powerful technique for the more complex interconnect problems     

Simple determination of all capacitances for a set of parallelmicrostrip lines

A fast and moderately accurate method to describe the complicated dependence on design and process parameters of coupling capacitances between a set of parallel lines is presented in this paper. It involves only one circuit-dependent parameter at a time. This is accomplished by calculating the capacitance coefficient matrix through inversion of a potential coefficient matrix with much simpler dependence on geometry. Self elements are approximately independent of the presence of other lines, and mutual elements do not depend on linewidths or interfering lines as long as the ground is sufficiently far away. The potential coefficients are derived by inverting one- or two-line capacitance matrices that are either theoretically calculated or determined by measurements on integrated circuit (IC) test structures. Look-up tables for a specific IC process can then be constructed with only linewidth as the parameter for self potential elements and distance between line centers as parameter for mutual potential elements. General algorithms have been derived for microstrip on one or two layers of dielectric     

一种快速的三维VLSI互连电容提取方法:虚拟多介质方法

本文提出一种基于直接边界元方法的虚拟多介质(Quasi-Multiple Medium,QMM)加速方法,并将它应用于三维VLSI多介质互连电容的计算中.QMM方法将三维互连电容器中的单层介质看成由多个虚拟介质组成,从而大大减少了系数矩阵中的非零元数目,最终使计算时间和存储空间显著减少.通过比较QMM算法与非QMM算法,以及商业软件Raphael对实际三维互连结构的计算,结果表明QMM算法在保持计算准确性的同时,可使电容提取的效率得到显著提高.     

Performance Modeling of Low-$k$/Cu Interconnects for 32-nm-Node and Beyond

Challenges and issues with the scaling of low-$k$/Cu interconnects in ultra-large-scale integration (ULSI) devices are reviewed, and the performance of interconnects is featured by considering the effect of the resistance and capacitance per unit interconnect length or the minimum grid length. The grid-scaled resistance–capacitance (GSRC) model is proposed to compare the interconnect performance at various technology nodes. Introduction of low-$k$ films to reduce the line capacitance improves the per-grid value of the resistance–capacitance product, however, the abrupt increment of the line resistivity due to the small-size effect consumes the benefit of the capacitance beyond 32-nm-node. We also discuss power consumption in interconnects with different low- $k$ structures based on experimental works. Continuous reduction of effective $k$-value $(K_{ rm eff})$ is needed to reduce the active power consumption. The way to reduce the interconnect resistance while keeping the interconnect reliability high is a key challenge, particularly for deeply scaled-down ULSIs.      

随机间距稀疏三元循环相位掩膜矩阵可压缩成像

可压缩成像是一种新兴的基于压缩感知理论的新成像技术,其核心思想是如果空间场景是稀疏或可压缩,那么它可以用远少于经典的Nyquist采样数目的测量值捕获的足够信息重构原场景;构建合适的测量矩阵并易于使用物理实现压缩感知理论中对于图像的随机线性测量是可压缩成像理论实用化的关键之一。该文在研究Bernoulli和Circulant矩阵的基础上,提出一种新的随机间距稀疏三元循环相位掩膜矩阵。模拟实验结果表明,在可压缩双透镜成像系统单次曝光下,与Bernoulli和Bernoulli-Circulant相位掩膜矩阵相比,新相位掩膜矩阵的成像信噪比与之相当;但是该文提出的矩阵随机独立变元个数和非零元个数显著减少,易于数据存储与传输;更重要的是物理上更容易实现,重构时间是只有原来的约20%~50%。新的相位掩膜矩阵的研究对于可压缩成像理论的实际应用具有重要的意义。     

A comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesis

Although three-dimensional (3-D) partial inductance modeling costs have decreased with stable, sparse approximations of the inductance matrix and its inverse, 3-D models are still intractable when applied to full chip timing or crosstalk analysis. The 3-D partial inductance matrix (or its inverse) is too large to be extracted or simulated when power-grid cross-sections are made wide to capture proximity effect and wires are discretized finely to capture skin effect. Fortunately, 3-D inductance models are unnecessary in VLSI interconnect analysis. Because return currents follow interconnect wires, long interconnect wires can be accurately modeled as two-dimensional (2-D) transmission lines and frequency-dependent loop impedances extracted using 2-D methods . Furthermore, this frequency dependence can be approximated with compact circuit models for both uncoupled and coupled lines. Three-dimensional inductance models are only necessary to handle worst case effects such as simultaneous switching in the end regions. This paper begins by explaining and defending the 2-D modeling approach. It then extends the extraction algorithm to efficiently include distant return paths. Finally, a novel synthesis technique is described that approximates the frequency-dependent series impedance of VLSI interconnects with compact circuit models suitable for timing and noise analysis.     

一种用于提取超大规模集成电路电容的新型库查找法

提出了八种节点电容典型结构用以建立电容模型库,并阐明了这八种结构可以提取大多数VLSI互连线的电容参数,给出了这些结构的拟合公式.采用该库查找法计算的互连线电容结果与FastCap所得结果非常吻合.由于电容是直接代入拟合公式计算得到的,所以计算速度非常快.     

Asymptotic Behavior of Random Vandermonde Matrices With Entries on the Unit Circle

Analytical methods for finding moments of random Vandermonde matrices with entries on the unit circle are developed. Vandermonde matrices play an important role in signal processing and wireless applications such as direction of arrival estimation, precoding, and sparse sampling theory, just to name a few. Within this framework, we extend classical freeness results on random matrices with independent and identically distributed (i.i.d.) entries and show that Vandermonde structured matrices can be treated in the same vein with different tools. We focus on various types of matrices, such as Vandermonde matrices with and without uniform phase distributions, as well as generalized Vandermonde matrices. In each case, we provide explicit expressions of the moments of the associated Gram matrix, as well as more advanced models involving the Vandermonde matrix. Comparisons with classical i.i.d. random matrix theory are provided, and deconvolution results are discussed. We review some applications of the results to the fields of signal processing and wireless communications.     

On the Elementwise Convergence of Continuous Functions of Hermitian Banded Toeplitz Matrices

Toeplitz matrices and functions of Toeplitz matrices (such as the inverse of a Toeplitz matrix, powers of a Toeplitz matrix or the exponential of a Toeplitz matrix) arise in many different theoretical and applied fields. They can be found in the mathematical modeling of problems where some kind of shift invariance occurs in terms of space or time. R. M. Gray's excellent tutorial monograph on Toeplitz and circulant matrices has been, and remains, the best elementary introduction to the Szegouml distribution theory on the asymptotic behavior of continuous functions of Toeplitz matrices. His asymptotic results, widely used in engineering due to the simplicity of its mathematical proofs, do not concern individual entries of these matrices but rather, they describe an "average" behavior. However, there are important applications where the asymptotic expressions of interest are directly related to the convergence of a single entry of a continuous function of a Toeplitz matrix. Using similar mathematical tools and to gain insight into the solutions of this sort of problems, the present correspondence derives new theoretical results regarding the convergence of these entries     

Impact of line-edge roughness on resistance and capacitance of scaled interconnects

The impact of line-edge roughness (LER) on resistance R and capacitance C of on-chip interconnects is for the first time evaluated by a simulation methodology based on a realistic modeling of LER. The model can be calibrated with measured LER parameters. A geometrical approximations of LER is generated and superimposed to an interconnect architecture model with no roughness; resistance and capacitance are extracted from the model by a 3D static solver to estimate the impact of LER on them. By applying this methodology to the interconnect scaling scenario of the 2005 ITRS Roadmap, a small but increasing detrimental effect of LER on both R and C is predicted.     

动态随机存储器中堆叠电容器结构的互连寄生电容模拟

在高密度比特位动态随机存储器(DRAM)芯片的发展中,随着多层布线与复杂存储单元结构的日渐普遍使用,互连寄生电容对存储器件性能如时延、功耗、噪声等的影响日渐突出,已成为不可忽视的重要因素,对互连寄生电容提取软件提出了紧迫的要求.本文介绍一个基于直接边界元素法的精度高,速度快,并可适应复杂堆叠(stacked)电容器结构的互连寄生电容模拟软件,并通过实例计算,分析DRAM中互连线寄生电容对电路性能的影响.     

Computation of the Transmission Line Inductance and Capacitance Matrices from the Generalized Capacitance Matrix

In a recent paper [1], a method for computing the per-unitlength generalized capacitance matrix of a system of dielectric-insulated wires was given. In this-paper, a method for computing the per-unitlength inductance and capacitance matrices used in multiconductor transmission-line models in terms of the elements of the generalized capacitance matrix is given. Certain approximate formulas for large wire separations are also given. Rome Air Development Center.     

Modeling and Analysis of On-Chip Single and H-tree Distributed RLC Interconnects

This paper presents novel methods for modeling and analysis of on-chip Single and H-tree distributed resistance inductance capacitance interconnects. The matrix pade-type approximation and scaling and squaring methods are employed for the numerical estimation of delay in single interconnect, and H-tree interconnects. The proposed models, which are based on these methods, provide rational function approximation for obtaining a passive interconnect model. Multiple single input single output model approximated transfer functions are developed for H-tree interconnects structure. With the equivalent reduced order lossy interconnect transfer functions, finite ramp responses are obtained, and line delay is estimated for various line lengths, input ramp rise times, source resistances, parasitic capacitances and load capacitances. In order to demonstrate the accuracy of proposed models, the estimated 50 % delay values are compared with the standard HSPICE W-element model and are found to be in good agreement. The proposed models worst case 50 % delay errors of single interconnect are 0.27 and 0.24 % respectively, while the worst case 50 % delay errors of H-tree structure are 5.73 and 3.94 % respectively.     

A new on-chip interconnect crosstalk model and experimentalverification for CMOS VLSI circuit design

A new, simple closed-form crosstalk model is proposed. The model is based on a lumped configuration but effectively includes the distributed properties of interconnect capacitance and resistance. CMOS device nonlinearity is simply approximated as a linear device. That is, the CMOS gate is modeled as a resistance at the driving port and a capacitance at a driven port. Interconnects are modeled as effective resistances and capacitances to match the distributed transmission behavior. The new model shows excellent agreement with SPICE simulations. Further, while existing models do not support the multiple line crosstalk behaviors, our model can be generalized to multiple lines. That is, unlike previously published work, even if the geometrical structures are not identical, it can accurately predict crosstalk. The model is experimentally verified with 0.35-μm CMOS process-based interconnect test structures. The new model can be readily implemented in CAD analysis tools. This model can be used to predict the signal integrity for high-speed and high-density VLSI circuit design     

Inductance model and analysis methodology for high-speed on-chip interconnect

With operating frequencies entering the multi-gigahertz range, inductance has become an important consideration in the design and analysis of on-chip interconnects. In this paper, we present an accurate and efficient inductance modeling and analysis methodology for high-performance interconnect. We determine the critical elements for a PEEC based model by analyzing the current flow in the power grid and signal interconnect. The proposed model includes distributed interconnect resistance, inductance and capacitance, device decoupling capacitances, quiescent switching currents in the grid, pad connections, and pad/package inductance. We propose an efficient methodology for extracting these elements, using statistical models for on-chip decoupling capacitance and switching currents. Simulation results show the importance of various elements for accurate inductance analysis. We also demonstrate the accuracy of the proposed model compared to the traditional loop-based inductance approach. Since the proposed model can consist of hundreds of thousands of RLC elements, and a fully dense mutual inductance matrix, we propose a number of acceleration techniques that enable efficient analysis of large interconnect structures.     

Tropospheric radio propagation assessment

The status of tropospheric radio propagation assessment is reviewed and recent advances in this area are described. Special emphasis is given to anomalous propagation in a marine environment. Modeling and measurements of ducting phenomena caused by the oceanic evaporation duct and by elevated refractive layers are discussed. The modeling involves extensive numerical calculations of waveguide propagation, ray-tracing techniques, and empirical relationships. Effects such as sea-surface roughness and horizontal inhomogeneity are also addressed. The models have been compared with extensive measurements in a variety of geographic locations. Worldwide radio refractivity climatologies have been compiled. A propagation assessment system, called the "Integrated Refractive Effects Prediction System" (IREPS), has been developed and successfully tested. It uses a small computer with interactive graphic displays and provides the user with performance assessment of communications and radar equipment based on prevailing atmospheric conditions. Environmental inputs into the system consist of surface measurements and profiles of atmospheric refractivity either calculated from radiosonde balloon data or measured by microwave refractometers. Status and shortcomings of direct and remote sensing techniques for measurement of atmospheric refractivity are also discussed.     

Field-Based Capacitance Modeling for Sub-65-nm On-Chip Interconnect

Back-end-of-the-line (BEOL) interconnect becomes a limiting factor to circuit performance in scaled complementary metal–oxide–semiconductor design. To accurately extract its paratactic capacitance for circuit simulation, compact models should be scalable with wire geometries and should capture the latest technology advances, such as the air gap and Cu diffusion barrier. This paper achieves these goals based on the distribution of the electric field in on-chip BEOL structures. By decomposing the electric field into various regions, the proposed method physically solves each basic capacitance component into a closed-form solution; the total ground and coupling capacitances are then the sum of all related components. Such a component-based approach is convenient in incorporating new interconnect structures. Its physics basis minimizes the complexity and the error in a traditional model fitting process. Compared with Raphael simulations at the 45-nm node, the new compact model accurately predicts the capacitance value, even in the presence of the air gap and diffusion barrier, covering a wide range of BEOL dimensions. The complete set of equations will be implemented at http://www.eas.asu.edu/~ptm.      

Analysis of interconnect capacitance for sub nano CMOS technology using the low dielectric material

A vital parameter interconnect capacitance in the ULSI has been investigated in this paper. The potential and static capacitance under the metal line strip has been determined by solving the Poisson’s equation by finite difference method. It has been observed that, the lowering of interconnect width and spacing between the two metal lines affect significantly on coupling capacitance. The total capacitance (C_T) is dominantly being contributed by coupling capacitance (C_c). The calculations of C_T have been made by using the low dielectric constant (k = 2.97) of the deposited hybrid thin film.     

A simple and efficient measurement method for characterizingcapacitance matrix of multilayer interconnection in VLSI

A compact new test structure for direct extraction of components of the capacitance matrix for multilayer interconnections is presented. In this new method, each capacitive component in integrated structures is separately and directly obtained from measurement, and the total pads are kept to eight, independent of the size of the target matrix. As a result of evaluation of measurement errors caused by the asymmetry of structures, this new method can measure components of capacitance matrix with a precision of femto-farad order     

Interconnection of Subsystem Reduced-Order Models in the Electrothermal Analysis of Large Systems

Heat conduction in an electronic device is commonly modeled as a discretized thermal system (e.g., finite element or finite difference models) that typically uses large matrices for solving complex problems. The large size of electronic-system heat transfer models can be reduced using model reduction methods and the resulting reduced-order models can yield accurate results with far less computational costs. Electronic devices are typically composed of components, like chips, printed circuit boards, and heat sinks that are coupled together. There are two ways of creating reduced-order models for devices that have many coupled components. The first way is to create a single reduced-order model of the entire device. The second way is to interconnect reduced-order models of the components that constitute the device. The second choice (which we call the "reduce then interconnect" approach) allows the heat transfer specialist to perform quick simulations of different architectures of the device by using a library of reduced-order models of the different components that make up the device. However, interconnecting reduced-order models in a straightforward manner can result in unstable behavior. The purpose of this paper is two-fold: creating reduced-order models of the components using a Krylov subspace algorithm and interconnecting the reduced-order models in a stable manner using concepts from control theory. In this paper, we explain the logic behind the "reduce then interconnect" approach, formulate a control-theoretic method for it, and finally exhibit the whole process numerically, by applying it to an example heat conduction problem