General purpose rail-to-rail input circuit with constant behaviour for VLSI cell libraries

A general purpose rail-to-rail input stage suitable for analogue and mixed signal applications and compatible with modern submicron CMOS technologies, is introduced. The circuit provides, simultaneously, a constant small- and large-signal behaviour over the entire input common-mode voltage range, whilst imposing no appreciable constraint for high-frequency operation. Experimental results are given.     

Calculating mean system-failure frequency with prescribed accuracy

To calculate mean system-failure frequency (MSFF) for good engineering designs, an approximation with prescribed accuracy is possible, starting from mincuts, viz, from a sum-of-products form of the fault-tree Boolean-function. Bonferroni-type inequalities, for which a new proof is included, are used. There is a far-reaching similarity between certain kinds of bounds for MSFF (of coherent systems) and for system unavailability. However, this similarity Is not complete. For most real systems, omitting the less-important mincuts yields lower bounds not only for unavailability but also for MSFF. Because an equivalent of the first Bonferroni inequality also holds with MSFF, it is possible to determine an upper bound of the contribution of the deleted mincuts or, the other way around: given a maximum error, determine a set of less-important mincuts, which can be deleted prior to a standard (exact) analysis of the rest. Since 1977 there is a valuable insight that Bonferroni-type inequalities hold also for MSFF (and since 1995 for mean electronic-system life). However, if the difference between the first upper and lower bounds is not small enough, then the investigation of further bounds might be rather cumbersome. However, there is a straight-forward mincut-based approximation to MSFF. As for approximate values of system mean time to failure (MTTF) and mean time to repair (MTTR), upper and lower bounds can be readily found via MSFF=unavailability/MTTR=availability/MTTF using upper and lower bounds for unavailability and MSFF in an obvious way. Of course, these bounds might not be sufficiently tight initially     

Fast and accurate statistical characterization of standard cell libraries

With devices entering the nanometer scale process-induced variations, intrinsic variations and reliability issues impose new challenges for the electronic design automation industry. Design automation tools must keep the pace of technology and keep predicting accurately and efficiently the high-level design metrics such as delay and power. Although it is the most time consuming, Monte Carlo is still the simplest and most employed technique for simulating the impact of process variability at circuit level. This work addresses the problem of efficient alternatives for Monte Carlo for modeling circuit characteristics under statistical variability. This work employs the error propagation technique and Response Surface Methodology for substituting Monte Carlo simulations for library characterization.The techniques are validated and compared using a production level cell library using a state-of-the-art 32 nm technology node and statistical device compact model. They require electrical simulation effort linear to the number of devices, thus from one to two orders of magnitude speed-up is obtained compared to Monte Carlo analysis with the error on standard deviation and mean being smaller than 2% for the Response Surface Methodology, as compared to errors of 7% when using linear sensitivity analysis.     

Constant-g/sub m/ constant-slew-rate high-bandwidth low-voltage rail-to-rail CMOS input stage for VLSI cell libraries

This paper introduces a general-purpose low-voltage rail-to-rail input stage suitable for analog and mixed-signal applications. The proposed circuit provides, simultaneously, constant small-signal and large-signal behaviors over the entire input common-mode voltage range, while imposing no appreciable constraint for high-frequency operation. In addition, the accuracy of the circuit does not rely on any strict matching of the devices, unlike most of the traditional approaches based on complementary input pairs, which need to compensate for the difference in mobility between electrons and holes with the transistor aspect ratios. Also, the technique is compatible with deep submicrometer CMOS devices, where the familiar voltage-to-current square law in saturation is not completely satisfied. Based on the proposed input stage, a transconductor with rail-to-rail input common-mode range and an input/output rail-to-rail operational amplifier were developed. Both cells were designed to operate with a 3-V single supply and fabricated in standard 0.8-/spl mu/m CMOS technology. Experimental results are provided.     

Evaluation of capacitance with prescribed accuracy adaptive methodbased on exact error estimation

This paper presented an adaptive method for a two-dimensional electrostatic analysis of air-filled two-conductor lines. The method is based on exact error estimates, and thus enables the evaluation of capacitance within prescribed accuracy limits. For the example of a transmission line consisting of square conductors considered, the characteristic impedance was estimated to be Z=75 ohms with a predefined relative error of less than δ_max=10^-6. The method can be generalized to two-dimensional and three-dimensional electrostatic analysis of arbitrary systems of conducting bodies in free space     

An effective timing characterization method for an accuracy-proved VLSI standard cell library

This paper presents a method of tailoring the characterization and modeling timing of a VLSI standard cell library. The paper also presents a method to validate the reasonability of the value through accuracy analysis. In the process of designing a standard cell library, this method is applied to characterize the cell library. In addition, the error calculations of some simple circuit path delays are compared between using the characterization file and an Hspice simulation. The comparison results demonstrate the accuracy of the generated timing library file.     

Statistical control of VLSI fabrication processes

Random fluctuations in very large scale integrated circuit (VLSIC) fabrication processes cause the parametric production yield to fall below acceptable levels, resulting in a loss of competitive edge. To address this problem, a framework for an integrated computer-aided-design-computer-aided-manufacturing (CAD-CAM) system that will enable the design, fabrication, control, and diagnosis of present and future VLSICs to be carried out profitably is proposed. It is argued that the inefficiencies of present-day CAM systems are due to the lack of appropriate methodologies for process monitoring and statistical techniques to analyze the in-process and end-of-process data. Methodologies for monitoring lots in fabrication lines, using in situ measurements, and for controlling lots, using the multivariate distribution of observable in-process parameters, are discussed. These methodologies attempt to eliminate the pitfalls of the previous statistical process control algorithms. The software system that implements the algorithms has shown encouraging results when applied to industrial fabrication lines     

The accuracy and validity of the simulation of VLSI MOS transistors

Corrections of the concepts of the accuracy and validity of compact models of deep submicron MOS transistors are suggested for the circuit design of VLSIs.     

Optimization of SIMOX for VLSI by electrical characterization

A comprehensive electrical characterization study which was conducted to optimize the fabrication of SIMOX substrates for VLSI is discussed. The oxygen implantation was carried out using medium-current and high-current implanters. The wafers were annealed at 1275°C and 1300°C to produce high-quality, precipitate-free material. The effect of dose, the effect of multiple implantation (by sequentially implanting and annealing), and the effect of the anneal ambient gas and the capping layer during annealing were studied. MOSFETs of various geometries with a gate oxide of ~20 nm were fabricated by a CMOS process incorporating the addition of a thin epitaxial Si layer. A general evaluation of each transistor was conducted by studying its static characteristics. The interface states, bulk traps, and carrier generation phenomena were studied. Good-quality interfaces were obtained. Better implantation control reduced contamination and suppressed deep traps below the detection limit. Multiple implantation resulted in superior material quality. as evidenced by very long generation lifetime values (> 100 μs)     

Design and characterization of analog VLSI neural network modules

A systematic method for testing large arrays of analog, digital, or mixed-signal circuit components that constitute VLSI neural networks is described. This detailed testing procedure consists of a parametric test and a behavioral test. Characteristics of the input neuron, synapse, and output neuron circuits are used to distinguish between faulty and useful chips. Stochastic analysis of the parametric test results can be used to predict chip yield information. Several measurement results from two analog neural network processor designs that are fabricated in 2 μm double-polysilicon CMOS technologies are presented to demonstrate the testing procedure     

"VLSI物理设计"科教融合教学方法探索

"VLSI物理设计"是关于集成电路设计方法与流程的研究生课程,本文在教学中引入芯片设计项目,把科研成果转化为教学内容,采用制作PPT、比对设计流程、扩展课程内容、展示芯片实物、播放样机视频和分享项目经验等多种方式探索科教融合新途径,这些方式提高了课程教学质量.     

VLSI电源/地网设计方法

对芯片有效供电的电源/地网设计在VLSI设计中非常重要。电源/地网布线设计方法可分成建立电源/地网拓扑结构、在已有拓扑结构及约束条件的基础上进行线宽优化等两步。本文简要介绍了电源/地网拓扑生成、线宽优化算法的研究进展,并指出了这些算法存在的一些问题。     

Measurement and characterization of multilayered interconnectcapacitance for deep-submicron VLSI technology

This paper presents the measurement and characterization of multilayered interconnect capacitances for a 0.35-μm CMOS logic technology, which become a critical circuit limitation to high performance VLSI design. To measure multilayered capacitances of nonstacked, stacked, and orthogonally crossing interconnect lines, new test structures and measurement methods are presented. The measured interconnect capacitances were employed to evaluate and calibrate TCAD tools for the simulation of high-speed interconnect technologies. This study shows that the calibration method considerably improves the accuracy of simulation results compared with measured results     

Distributed control of performance management traffic with accuracy objectives

One of the important functions of a network management system (NMS) is performance management (PM). PM deals with collecting statistical information to track the effectiveness and utilization of the network and network elements (NE). While this may be done offline, it is often necessary to monitor the network statistics online in real time. The aim of real‐time monitoring is to achieve high accuracy of the statistics while minimizing the use of scarce network bandwidth. The accuracy objective can vary depending on the priority and dynamic severity state of the NE. We define cost, which needs to be optimized, as a function of network traffic and achieved accuracy. Based on the cost, a comparison of push and pull data collection alternatives is done. We have developed a push‐based distributed data collection system that tunes the accuracy objectives, based on the network traffic and the dynamic severity state of the NE. Copyright © 2009 John Wiley & Sons, Ltd.     

Interconnect characterization of X architecture diagonal lines for VLSI design

This paper addresses the manufacturability, yield, and reliability aspects of X Architecture interconnects (diagonal lines) in a very large scale integrated (VLSI) design that enables integrated circuit (IC) chips to become faster and smaller (area) compared to the same design in Manhattan routing. Test chips that consist of comb/serpentine, maze, via chain, as well as resistance and capacitance structures are designed and fabricated using both 130- and 90-nm copper processes. A new technique to characterize interconnect physical parameters (top and bottom line widths, metal line, and dielectric thickness) is developed that requires capacitance measurement on sets of special test structures. An excellent agreement is found between the extracted process parameters, for both diagonal and Manhattan lines, using this technique and those of SEM/FIB data. Measurements of the line resistance, capacitance, and SEM/FIB data on different types of test structures show that 1:1 design rule ratio (Manhattan versus X Architecture) is manufacturable, and the uniformity and fidelity of the diagonal lines are as good as Manhattan lines. The current generation of mask, lithography, wafer processing techniques are applicable to X Architecture designs.     

TD-LTE信令数据准确性核查方法

随着TD-LTE网络的建设和大数据技术的逐渐成熟,基于TD-LTE信令数据进行网络质量分析已然成为当前趋势.通过采集海量XDR话单进行用户感知和网络性能分析,正在成为一种越来越重要的分析手段.数据源的完整性和准确性是分析的基石,文章分析数据采集的关键字段,制定核查算法,应用于当前信令分析系统.     

Full-wave modelling and broadband characterization of coupled interconnects in high-speed VLSI

A time-domain full-wave method for the extraction of broadband equivalent circuit parameters of symmetrical coupled interconnection lines on chips is presented. This method is based on the two-dimensional finite-difference time-domain method. After determination of the even and odd mode propagation constant γ and characteristic impedance Z _c of the lines, the RLGC matrices per unit length can be obtained. Many techniques are proposed and used during the time-domain analysis to improve the efficiency. The circuit parameters extracted can be inserted into circuit simulation software to investigate the time-domain responses of high-speed integrated circuits on chips. The reliability of this method is verified by its applications to typical problems.     

Statistical control of VLSI fabrication processes. II. A softwaresystem

For pt.I see ibid., vol.1, no.2, p.62-71, 1988. The algorithms used to implement the CMU-CAM statistical control system for VLSI integrated circuit fabrication are presented. The CMU-CAM system performs three major operations: modeling; quality control; and feed-forward control. In order to increase the efficiency of modeling and control, the problem is decomposed using statistical factorization techniques. Algorithms for process modeling and algorithms used in quality control and feed-forward control are described. The CMU-CAM system performs profit maximization through statistical process control. Its capabilities are illustrated by a number of computational examples