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1.
Standard micropipelines use simple two-phase control circuits. The latches employed on AMULET1 are level sensitive, so two- to four-phase converters are required in each latch controller. To avoid this overhead an investigation has been carried out into four-phase micropipeline control circuits; this has thrown up several design issues relating to cost, performance and safety, and forms a useful illustration of asynchronous design techniques  相似文献   

2.
异步系统的信号传送研究   总被引:3,自引:0,他引:3  
异步电路在低功耗、低噪声、抗干扰、无时钟偏移和模块化设计等方面有较高的性能。在SOC芯片设计中,异步设计技术逐渐成为研究的热点。文中比较了同步系统和异步系统信号传递基础,介绍了多个基于异步系统的信号传递模型,讨论了专用于异步电路的数据传送方式。从应用的角度对现有的异步电路信号传递模型的结构、特点、数据信号、应用背景等方面进行了比较研究,最后总结了在实际问题中选择模型的原则。  相似文献   

3.
姜小波  叶德盛 《电子学报》2012,40(8):1650-1654
本文利用输入数据的统计特性,设计了两种低功耗异步比较器——异步行波比较器和提前终止异步比较器.异步行波比较器从第一个不相等的数位开始停止运算,但要把结果传到最低位,消耗部分功耗.提前终止异步比较器通过修改真值表,基于新的比较单元电路和终止判断电路,在第一个不相等的数位停止运算并立即输出比较结果,节省不必要的功耗.新设计的异步比较器和用于对比的同步比较器(BCL比较器和门控时钟比较器)均用SMIC0.18μm工艺实现.仿真结果表明,提前终止异步比较器功耗最低,与同步BCL比较器和门控时钟比较器相比,在随机数据和来自LDPC解码器的数据下,分别节省了87.1%、84.5%和37.5%、28.6%的功耗.  相似文献   

4.
Providing quality mobile video applications in hand-held mobile devices requires increased computational capability. Using Single Instruction Multiple Data (SIMD) techniques to expose and accelerate the data parallelism inherent in video processing increases performance in handheld and wireless systems. The paper introduces a new 64-bit SIMD coprocessor of the Intel® XScale® microarchitecture which is optimized for low-power handheld applications. The architecture blends the SIMD media processing style with the capabilities of the XScale microarchitecture. This paper provides an overview of the architecture, its instruction set, programming model, the pipeline organization and functional units. The paper also describes how key features of architecture improve the performance of video applications as compared to a scalar implementation. The performance and power improvements based upon measured results are analyzed to show how the opportunities of power savings by reducing the frequency and voltage can be realized.Nigel C. Paver has 13 years experience with the ARM architecture, and in the Intel PCA Components group in Austin, Texas, he is responsible for the architecture and implementation of multimedia coprocessors for the Intel XScale micro-architecture. He is also involved in product architecture and definition of Intel PCA processors. Before Intel, Nigel was one of the lead designers of the early AMULET asynchronous ARM microprocessors at the University of Manchester. He was also vice president in a startup company which used asynchronous design techniques to produce a low-power asynchronous DSP core. Nigel holds a Master of Science degree and Ph.D. in computer science from the University of Manchester and a Bachelor of Science degree in electronics from UMIST.Moinul Khan is a multimedia product architect at Intel Corporation PCA Components group. He is responsible PCA graphics and security architecture. His research interests are virtual prototyping, signal processing algorithms and architecture and communications networking. Before joining Intel he was a technology specialist and founding member of a startup at ATDC, Georgia. He worked on his doctoral research at Georgia Center for Advanced Telecommunications Technology at Georgia Institute of Technology. He received his B.Tech form Indian Insti-ture of Technology and MSEE from Georgia Tech. He also worked as a research member for Canadian Institute for Telecommunications Research and Bell Communications Laboratories.Bradley C. Aldrich joined Intel in 1997 where he is currently an architect within the PCA Components Group. His current work includes the development of coprocessor instruction support in addition to image capture and display technologies for XScale based application processors. He was previously a member of the Intel/Analog Devices joint development architecture team responsible for video enhancements for the Micro Signal Architecture. Prior to that he was a video system architect in Intel’s Digital Imaging and Video Division working on CMOS sensors, still cameras, and tethered PC based video peripherals. He has also worked as a device engineer for Motorola and as a test engineer for Tektronix. He received a BSEE in 1988 and MSEE in 1994 from the University of Texas at San Antonio.Christopher D. Emmons received a Bachelor of Science degree in Computer Science from the University of Texas at Austin in 2003. He joined Intel in 2001 and is currently a multimedia architect responsible for algorithm development and performance optimization for handheld products within the PCA Components Group. Prior to this he worked as an applications engineer providing performance and power analysis in support of product marketing groups. His research interests include video compression, operating system design, and dynamic resource management.  相似文献   

5.
This paper presents a new approach to an on-chip asynchronous transmission system suitable for next generation asynchronous on-chip networks. It implements multivalued logic to reduce the number of wires and a low-voltage swing for lower dynamic power dissipation. Furthermore, the transmission system described here enjoys fully static design and has zero static power consumption. Two versions of the transmitter circuit and the receiver are described. The proposed signaling scheme is compared to a classical dual-rail signaling system with regard to speed, power consumption, and reliability. The simulation results show that the asynchronous ternary logic signaling (ATLS) system delivers over 70% higher bandwidth per wire and consumes over 50% less power than the dual-rail signaling system on 10-mm-long on-chip interconnection.  相似文献   

6.
LCD控制器中异步电路的设计   总被引:1,自引:0,他引:1  
异步电路的设计能够解决功耗、系统速度、时钟偏移等问题,成为当前VLSI研究的热点.文章提出了4级灰度LCD控制器异步电路的设计方案,通过异步控制以消除无效操作从而降低功耗,经验证平均功耗仅为同步电路的23.7%:异步电路还实现了部分显示和滚屏等功能,加快了系统响应速度.  相似文献   

7.
Two types of low-power asynchronous comparators featured with input data statistical characteristic are proposed in this article. The asynchronous ripple comparator stops comparing at the first unequal bit but delivers the result to the least significant bit. The pre-stop asynchronous comparator can completely stop comparing and obtain results immediately. The proposed and contrastive comparators were implemented in SMIC 0.18 μm process with different bit widths. Simulation shows that the proposed pre-stop asynchronous comparator features the lowest power consumption, shortest average propagation delay and highest area efficiency among the comparators. Data path of low-density parity check decoder using the proposed pre-stop asynchronous comparators are most power efficient compared with other data paths with synthesised, clock gating and bitwise competition logic comparators.  相似文献   

8.
Asynchronous interconnection paradigm in NoCs has attracted many system designers in the recent years, through its different possible implementation strategies. In this paper, we present a new insight on how to categorize asynchronous protocols and explore a suitable protocol for the NoC asynchronous links. The new categorization criterion is based on the type of dependency between data transferring and handshaking tasks in a protocol. Furthermore, a new protocol called modified bundled-data (MBD) is introduced. MBD is a bundled-data-like protocol with two pairs of two-phase dual-rail encoded parity lines on the lateral sides of data lines, besides one two-phase acknowledgement line. The new protocol is evaluated by comparing its simulation results with those of bundled-data (BD) and dual-rail (DR) protocols on a 32-bit flit NoC asynchronous link. For this purpose, a new comprehensive interconnect model has been developed. The simulation results show that the new protocol's features such as power consumption, throughput, and latency are comparable with BD protocol's, while its signal integrity features are close to DR's.  相似文献   

9.
针对单个电流型逆变器供电质量不足,提出双重电流型逆变器供电异步电动机的控制。分析了电流型逆变器结构及工作过程,建立异步电动机数学模型,构建了双重电流型逆变器供电三相异步电动机系统,并进行了仿真。仿真结果表明,双重电流型逆变器优于单个电流型逆变器供三相电异步电动机的性能,而且该系统起动快,运行稳定,动态性能优良。  相似文献   

10.
在二维异步光码分多址(OCDMA)系统中,考虑光接收机存在多种噪声源干扰和用户之间存在的多址干扰(MAI),使用了具有双硬限幅器(OHL)的光接收机来优化系统传输性能.文章数值分析了阈值、用户数和入射光功率等对系统误码率的影响.结果表明:双OHL二维异步OCDMA系统的误码率相对于单OHL系统和无OHL系统明显下降,基本消除了MAI.  相似文献   

11.
In applications where issues like power efficiency, high performance, and more noise tolerance are important, asynchronous design methodology can play a significant role. However, as a result of technology shrinkage, combinational asynchronous circuits have become vulnerable in presence of particle strikes. In this paper, we design robust quasi-delay insensitive (QDI) asynchronous circuits against soft errors. Null Convention Logic (NCL) gates used as one of the basic techniques in asynchronous circuits, are redesigned to increase their robustness against Single Event Upset (SEU). We analyze our design for various NCL structures and compare them with another design in Kuang et al. (2007) [4], and show that our proposed approach is more robust against SEU. The effect of some parameters such as power consumption, delay, and the influence of transistor sizing on soft error tolerance are discussed.  相似文献   

12.
An ISFET-based integrate and fire neuron, forming the front-end of a chemical pixel sensor, is introduced. With the sense data being encoded in the spike domain, i.e. asynchronous/continuous time and discrete value, it is directly compatible with asynchronous communication hardware, e.g. address event representation. The circuit is shown to be tunable to yield a linear relation with both pH and actual hydrogen ion concentration, with a peak power consumption of 35 muW. Furthermore, its compact pixel footprint of under 6500 mum2, makes it ideal for use in arrayed architectures with application in biochemical imaging  相似文献   

13.
介绍了一种适用于Viterbi解码器的异步ACS(加法器-比较器-选择器)的设计.它采用异步握手信号取代了同步电路中的整体时钟.给出了一种异步实现结构的异步加法单元、异步比较单元和异步选择单元电路.采用全定制设计方法设计了一个异步4-bit ACS,并通过0.6μm CMOS工艺进行投片验证.经过测试,芯片在工作电压5V,工作频率20MHz时的功耗为75.5mW.由于采用异步控制,芯片在"睡眠"状态待机时不消耗动态功耗.芯片的平均响应时间为19.18ns,仅为最差响应时间23.37ns的82%.通过与相同工艺下的同步4-bit ACS在功耗和性能方面仿真结果的比较,可见异步ACS较同步ACS具有优势.  相似文献   

14.
As system-level interconnect incurs increasing penalties in latency, round-trip cycle time and power, and as timing-variability becomes an increasing design challenge, there is renewed interest in using two-phase delay-insensitive asynchronous protocols for robust system-level communication. However, in practice, it is extremely inefficient to build local asynchronous computation nodes with two-phase logic, hence four-phase (i.e., return-to-zero) computation blocks are typically used. This paper proposes two new architecture for a family of asynchronous protocol converters that translate between two- and four-phase protocols, thus facilitating robust system design using efficient global two-phase communication and local four-phase computation. A converter circuit is implemented and evaluated a 0.18 micron TSMC process through post-layout simulation, assuming both a small computation block (8 $,times,$8 combinational multiplier) and an empty computation block (FIFO stage).   相似文献   

15.
介绍一种异步可重构结构,研究了异步可重构单元的设计。通过提前产生求值完成信号,使用DSDCVS逻辑实现可重构单元的运算电路,改进了异步可重构单元的控制电路。用三输入的C元件实现异步可重构单元的控制电路。仿真结果表明,异步可重构结构具有低功耗、高性能的优点,适合作为IP集成到系统芯片上,组成低功耗、高性能的可重构计算平台。  相似文献   

16.
肖蕙蕙  王志强  李山 《现代电子技术》2011,34(10):136-138,148
三相异步电动机直接启动,存在较大的电流冲击,会引起电网电压下降,影响同一电网其他设备的正常运行。针对电动机的这一特性,介绍了一种基于模糊控制原理的三相异步电动机的软起动控制系统,通过在Simulink下建模、仿真,其结果证明了采用模糊控制的方法可以使三相异步电动机的启动电流减小,从而达到平稳起动的目的。  相似文献   

17.
Wideband DS-CDMA for next-generation mobile communications systems   总被引:5,自引:0,他引:5  
Wideband wireless access based on direct sequence code division multiple access aimed at third-generation mobile communications systems is reviewed. W-CDMA is designed to flexibly offer wideband services which cannot be provided by present cellular systems, with various data rates as high as 2 Mb/s. The important concept of W-CDMA is the introduction of intercell asynchronous operation and the pilot channel associated with individual data channels. Intercell asynchronous operation facilitates continuous system deployment from outdoors to indoors. Other technical features of W-CDMA include fast cell search under intercell asynchronous operation, fast transmit power control, coherent spreading code tracking, a coherent RAKE receiver, orthogonal multispreading factor forward link, and variable-rate transmission with blind rate detection. The introduction of the data-channel-associated pilot channel allows W-CDMA to support interference cancellation and adaptive antenna array techniques that can significantly increase the link capacity and coverage. This article presents the radio link performance evaluated by computer simulation. Field experiment radio link performance results are also presented  相似文献   

18.
Demosthenous  A. Taylor  J. 《Electronics letters》1998,34(18):1714-1715
A low voltage, low power current-mode comparator is described. The circuit features a wide dynamic range and very high-speed asynchronous operation and is intended for use in maximum likelihood sequence detection (MLSD) applications  相似文献   

19.
The matrix turbine features an arrangement of identical units of turbines and asynchronous generators. When installed in the stop log slot of a fill and discharge channel of a ship lock, power is generated both during fill and discharge operations. The locks of seven power plants at the Danube allow retrofit with marginal civil construction effort.  相似文献   

20.
A cellular asynchronous code-division multiple access (A-CDMA) system operating in the 63-64-GHz band for short-range communications is analyzed. A simple propagation model for the 63-64-GHz band is first introduced and discussed. The system capacity, expressed as the maximum number of users per cell, is then analytically derived and favorably compared with other CDMA schemes operating in conventional frequency bands (i.e., below 2 GHz). Also, simple expressions for the system bit error rate (BER) are analytically derived for different cases and validated through computer simulations. Finally, power requirements are derived and the impact of atmospheric conditions is evaluated. It turns out that the use of the 63-64-GHz band significantly increases the capacity of A-CDMA, and proves to be suitable for cellular systems and personal communication networks (PCNs) provided that adequate power margins are taken into account in the design of the system  相似文献   

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