Organic bistable memory device using MoO3 nanocrystal as a charge trapping center

Organic bistable memory devices (OBDs) with MoO₃ as a nanocrystal inside organic layer were developed and bistability of MoO₃ based OBDs was investigated. High on/off ratio over 200 was obtained at a low reading voltage of 1 V. MoO₃ OBDs could be electrically switched between high conductance state and low conductance state over more than 100 cycles and space charge limited conduction mechanism dominated switching behavior in MoO₃ OBDs.     

A novel quad source/drain metal nanocrystal memory device for multibit-per-cell storage

Based on the 2-bit-per-cell metal nanocrystal memories, a novel quad source/drain device capable of 4 bits per cell data storage is demonstrated. Along with the new device structure, a reliable parallel read scheme with low V/sub DS/ is also proposed and verified for 4-bit-per-cell operations. The proposed read scheme requires 1.125 read operations on average to read out the 4 bits stored in a cell, while minimizing the read disturb and interference between the different storage bits.     

1.2V NOR flash memory in system-in-package

A NOR Flash memory system, the supply voltage of which can be as low as 1.2 V, is described. The internal memory chip supply voltage (1.8 V) is obtained by means of a DC-DC converter totally included in the same package of the memory. This system represents a way to overcome technology limitations to generate a Flash device supplied at a voltage close to 1 V and below. The NOR Flash memory system is assembled in a ball grid array 88 balls 14times8times1.6 mm, with the same ballout of the standard Flash memory working at 1.8 V     

Statistical constraints in nanocrystal memory scaling

This paper presents a detailed investigation of the statistical constraints that may limit nanocrystal memory scaling to the deca-nanometer scale-size. We adopted a Monte Carlo simulation approach to evaluate the probability distribution of the threshold voltage shift after program and of the retention time in presence of stress-induced leakage current. These distributions were used to extract a program and a retention fail probability. Both of them increase with cell dimensions scaling, strongly reducing the benefits offered by the nanocrystal technology in future microelectronics nodes.     

Silicon nanocrystal non-volatile memory for embedded memory scaling

In this paper, we present key features of silicon nanocrystal memory technology. This technology is an attractive candidate for scaling of embedded non-volatile memory (NVM). By replacing a continuous floating gate by electrically isolated silicon nanocrystals embedded in an oxide, this technology mitigates the vulnerability of charge loss through tunnel oxide defects and hence permits tunnel oxide and operating voltage scaling along with accompanied process simplifications. However, going to discrete nanocrystals brings new physical attributes that include the impact of Coulomb blockade or charge confinement, science of formation of nanocrystals of correct size and density and the role of fluctuations, all of which are addressed in this paper using single memory cell and memory array data.     

快闪器件研究

快闪存储器由于其所具有的非挥发电可编程和片擦除特性,在嵌入式应用中有望取代SRAM、DRAM以及磁性存储器,并愈来愈受到重视,产品的市场占有率稳步上升,近10年来发展迅速。随着嵌入式系统和移动设备的发展以及集成电路特征尺寸的进一步缩小,在现有基础上对嵌入式存储器又提出了新的要求,主要有两条:更低的工作电压和更快的擦写速度。为满足这些要求,国际上在快闪存储器单元结构和相应的工艺实现方法上开展了大量的工作。对快闪存储器结构方面的研究进行了综述,以利于国内同行对该领域及快闪存储器的机理和研究方向有一个较全面的了解。     

一种适用于NOR结构快闪存储器的快速页编程算法

为了降低NOR结构快闪存储器的编程时间,本文提出一种能够根据编程数据的特点改变编程脉冲时序的快速页编程算法.它通过一个简单的判断电路对输入的编程数据中"1"的个数进行判断,并在状态机的控制下产生具有最小编程时间的页编程脉冲时序,从而达到缩短页编程时间的目的.统计结果表明,本算法的页编程时间不到传统方法的70%.     

Nonvolatile memory with a metal nanocrystal/nitride heterogeneous floating-gate

Heterogeneous floating-gates consisting of metal nanocrystals and silicon nitride (Si/sub 3/N/sub 4/) for nonvolatile memory applications have been fabricated and characterized. By combining the self-assembled Au nanocrystals and plasma-enhanced chemical vapor deposition (PECVD) nitride layer, the heterogeneous-stack devices can achieve enhanced retention, endurance, and low-voltage program/erase characteristics over single-layer nanocrystals or nitride floating-gate memories. The metal nanocrystals at the lower stack enable the direct tunneling mechanism during program/erase to achieve low-voltage operation and good endurance, while the nitride layer at the upper stack works as an additional charge trap layer to enlarge the memory window and significantly improve the retention time. The write/erase time of the heterogeneous stack is almost the same as that of the single-layer metal nanocrystals. In addition, we could further enhance the memory window by stacking more nanocrystal/nitride heterogeneous layers, as long as the effective oxide thickness from the control gate is still within reasonable ranges to control the short channel effects.     

Hafnium silicate nanocrystal memory using sol-gel-spin-coating method

The authors fabricate the hafnium silicate nanocrystal memory for the first time using a very simple sol-gel-spin-coating method and 900 /spl deg/C 1-min rapid thermal annealing (RTA). From the TEM identification, the nanocrystals are formed as the charge trapping layer after 900 /spl deg/C 1-min RTA and the size is about 5 nm. They demonstrate the composition of nanocrystal is hafnium silicate from the X-ray-photoelectron-spectroscopy analysis. They verify the electric properties in terms of program/erase (P/E) speed, charge retention, and endurance. The sol-gel device exhibits the long charge retention time of 10/sup 4/ s with only 6% charge loss, and good endurance performance for P/E cycles up to 10/sup 5/.     

Integration of CVD silicon nanocrystals in a 32 Mb NOR flash memory

In this paper, silicon nanocrystals (Si-NCs) fabricated by Chemical Vapor Deposition (CVD) are successfully integrated in a 32 Mb ATMEL NOR Flash memory product, processed in a 130 nm technology platform. Different Si-NC deposition conditions are explored and the threshold voltage distributions of the arrays are correlated to the Si-NC size/dispersion. Main reliability characteristics, as endurance and data-retention after cycling, are studied. Results obtained on large arrays are related to single cell characteristics. The large set of data measured on arrays clearly demonstrates the robustness of our process and integration scheme.     

Theoretical and experimental investigation of Si nanocrystal memory device with HfO/sub 2/ high-k tunneling dielectric

In this paper, silicon (Si) nanocrystal memory using chemical vapor deposition (CVD) HfO/sub 2/ high-k dielectrics to replace the traditional SiO/sub 2/ tunneling/control dielectrics has been fabricated and characterized for the first time. The advantages of this approach for improved nanocrystal memory operation have also been studied theoretically. Results show that due to its unique band asymmetry in programming and retention mode, the use of high-k dielectric on Si offers lower electron barrier height at dielectric/Si interface and larger physical thickness, resulting in a much higher J/sub g,programming//J/sub g,retention/ ratio than that in SiO/sub 2/ and therefore faster programming and longer retention. The fabricated device with CVD HfO/sub 2/ shows excellent programming efficiency and data-retention characteristics, thanks to the combination of a lower electron barrier height and a larger physical thickness of HfO/sub 2/ as compared with SiO/sub 2/ of the same electrical oxide thickness (EOT). It also shows clear single-electron charging effect at room temperature and superior data endurance up to 10/sup 6/ write/erase cycles.     

1V NOR Flash memory employing inductor merged within package

A NOR Flash memory fully functional at 1 V is demonstrated, based on an inductor built directly into the package. A ferromagnetic nucleus is wound by means of the bonding wires and the first package substrate metal layer. The magnetic field does not affect the system since it is strictly confined into the toroidal nucleus. The whole system is enclosed into a standard BGA package 8times14times1.4 mm with 88 balls     

High-performance nonvolatile HfO/sub 2/ nanocrystal memory

In this letter, we demonstrate high-performance nonvolatile HfO/sub 2/ nanocrystal memory utilizing spinodal phase separation of Hf-silicate thin film by 900/spl deg/C rapid thermal annealing. With this technique, a remarkably high nanocrystal density of as high as 0.9 /spl sim/ 1.9 /spl times/ 10/sup 12/ cm/sup -2/ with an average size <10 nm can be easily achieved. Because HfO/sub 2/ nanocrystals are well embedded inside an SiO/sub 2/-rich matrix and due to their sufficiently deep energy level, we, for the first time, have demonstrated superior characteristics of the nanocrystal memories in terms of a considerably large memory window, high-speed program/erase (P/E) (1 /spl mu/s/0.1 ms), long retention time greater than 10/sup 8/ s for 10% charge loss, and excellent endurance after 10/sup 6/ P/E cycles.     

Impact of floating gate dry etching on erase characteristics in NOR flash memory

We report the effects of plasma process-induced damage during floating gate (FG) dry-etching process on the erase characteristics of NOR flash cells. As compared to flash cells processed in a stable plasma condition, it is found that flash cells processed in the nonoptimized ambient show significantly degraded erase characteristics under a negative gate Fowler-Nordheim (FN) bias, exhibiting a fast-erasing bit in the distribution of erased bits. However, little differences are found in their tunneling characteristics under a positive gate biasing. The gate bias polarity dependence of FN tunneling indicates that positive charges are created near the poly-Si/SiO/sub 2/ interface during the FG dry-etching, prior to the backend processes such as metal- or via-etch.     

A novel sourceline voltage compensation circuit for embedded NOR flash memory

A novel sourceline voltage compensation circuit for program operation in embedded flash memory is presented. With the sourceline voltage compensation circuit, the charge pump can modulate the output voltage according to the number of cells to be programmed with data ＂0＂. So the IR drop on the sourceline decoding path is compensated, and a stable sourceline voltage can be obtained. In order to reduce the power dissipation in program operation, a bit-inversion program circuit is adopted. By using the bit-inversion program circuit, the cells programmed to data ＂0＂ are limited to half of the bits of a write data word, thus power dissipation in program operation is greatly reduced. A 1.8-V 8 × 64-kbits embedded NOR flash memory employing the two circuits has been integrated using a GSMC 0.18-μm 4-poly 4-metal CMOS process.     

Ionising radiation and electrical stress on nanocrystal memory cell array

In this work, we have investigated the effects of irradiation and electrical stress of nanocrystal memory cell arrays. Heavy ion irradiation has no or negligible immediate effects on the nanocrystal MOSFET characteristics, and on the programming window of the cells. By electrically stressing irradiated device, we see accelerated oxide breakdown similar to that previously observed on conventional thin gate oxide MOS capacitors, but no appreciable change of the degradation kinetics in terms of programming window closure and shift. The accelerated breakdown is ascribed to the degradation of the oxide–nitride–oxide (ONO) layer used as control oxide after exposure to ionising irradiation.     

A semiconductor-ferroelectric memory device

The development of monolithic, optically written, and electrically read memory elements employing single-crystal barium titanate is described. Both single and multiple-unit structures have been made. These structures can be fabricated using techniques similar to those employed in integrated circuits.     

基于RST的SiGe/Si"或非"逻辑器件研究

文中通过利用耗尽层阻断沟道的方法,讨论了一种基于RST结构原理实现"或非"逻辑功能的器件结构.     

The effect of dimensional scaling on the erase characteristics of NOR flash memory

In this letter, new limitations on the NOR flash cell scaling have been presented. As cell scaling is continued, a parasitic capacitance between floating gate and bitline contact induces a large disturbance to the Fowler-Nordheim tunneling characteristics due to a coupling ratio variation, resulting in a much broader erase threshold distribution. Theoretical analysis including MEDICI simulations confirms the effects of parasitic capacitance on the erase threshold of NOR flash cells.     

Design of a 16384-bit serial charge-coupled memory device

This paper describes a 16384-bit serial charge-coupled memory device designed primarily for low cost and compatibility with existing high-volume manufacturing techniques. To obtain low access time, the device was organized as 64 recirculating shift registers each 256 bits long. Any one register can be selected at random for reading or writing, by means of a 6-bit address input. The alternatives considered in choosing the charge-coupled device (CCD) structure and chip organization are discussed. Data regeneration circuits are described in detail. The device was fabricated on a silicon chip, with an area of 2.07 mil/SUP 2//bit (including all peripheral circuitry). It operates at data rates exceeding 2 MHz, and has a minimum average access time of under 100 /spl mu/s.