500 GHz cutoff frequency SiGe HBTs

A current gain cutoff frequency f_T of 508 GHz is reported for a SiGe heterojunction bipolar transistor (HBT) operating at 40 K. This 63% increase over the 311 GHz value measured at room temperature results from the overall decrease of the transit and charging times. Two HBTs are compared to highlight the importance of the topology of the HBT to reach maximum performances.     

5 GHz, 12 mW NMOS frequency divider

Reports on the development of an NMOS 2:1 frequency divider circuit that operates to over 5 GHz. It is powered from a 2.5 V supply and dissipates only 0.012 W. These results indicate that the use of silicon MOS technology may be extended to very-high-speed low-power applications     

18 GHz low-power CMOS static frequency divider

A pseudo-differential latch circuit is investigated. By removing the current source from the conventional source-coupled field-effect-transistor logic (SCFL) structure, the speed of the circuit can be improved. The pseudo-differential D-type flip-flop-based 2:1 static frequency divider, which can operate up to 18 GHz and consumes less than 4 mA from a 1.8 V supply, has been realised in 0.18 /spl mu/m standard digital CMOS technology.     

75 GHz ECL static frequency divider using InAlAs/InGaAs HBTs

A 75 GHz static frequency divider in InAlAs/InGaAs transferred-substrate heterojunction bipolar transistor (HBT) technology is reported. This is the highest reported frequency of operation for a static frequency divider. The circuit has 60 transistors and dissipates 800 mW. The divider was operated at a clock frequency of 5.0 to 75 GHz     

22 GHz 1/4 frequency divider using AlGaAs/GaAs HBTs

A divide-by-four frequency divider using AIGaAs/GaAs HBTs with GalnAs/GaAs emitter cap layers was designed and fabricated. A maximum toggle frequency of 22.15 GHz was obtained at a power supply voltage of 9 V and a total power dissipation of 712 mW. The minimum input signal power was under 0dBm and the free-running frequency was as high as 20 GHz.     

80 GHz 4:1 frequency divider IC using nonself-aligned InP/InGaAsheterostructure bipolar transistors

80 GHz operation has been attained for a divide-by-four frequency divider IC fabricated with non-self-aligned InP/InGaAs heterostructure bipolar transistors. To the authors' knowledge, this is the fastest digital frequency divider IC reported to date. The measured maximum toggle frequency of 80 GHz was the upper limit of the measurement setup     

40GHz InGaAs/InP CML 结构静态分频器

Static frequency dividers are widely used as a circuit performance benchmark or figure-of-merit indicator to gauge a particular device technology's ability to implement high speed digital and integrated high performance mixed-signal circuits.We report a 2:1 static frequency divider in InGaAs/InP heterojunction bipolar transistor technology.This is the first InP based digital integrated circuit ever reported on the mainland of China. The divider is implemented in differential current mode logic(CML) with ...     

An InGaAs/InP 40 GHz CML static frequency divider

Static frequency dividers are widely used as a circuit performance benchmark or figure-of-merit indicator to gauge a particular device technology’s ability to implement high speed digital and integrated high performance mixed-signal circuits.We report a 2:1 static frequency divider in InGaAs/InP heterojunction bipolar transistor technology.This is the first InP based digital integrated circuit ever reported on the mainland of China. The divider is implemented in differential current mode logic(CML) with 30 transistors.The circuit operated at a peak clock frequency of 40 GHz and dissipated 650 mW from a single -5 V supply.     

中科院微电子研究所研制成功40GHz静态分频器

近日,中科院微电子研究所四室InP HBT小组研制成功基于InP/InGaAs DHBT工艺的静态分频器,测试结果表明此分频器可在大于40GHz频率下正常工作,在电源供电为-5V的情况下,功耗为650mW,芯片尺寸为1.2mm×0.6mm.这是国内第一款基于InP/InGaAs DHBT工艺的可在毫米波段工作的超高速数字电路.     

50 GHz frequency divider using resonant tunnelling chaos circuit

An ultra-high-speed frequency divider using a resonant tunnelling chaos circuit is fabricated, which monolithically integrates a resonant tunnelling diode and a high electron mobility transistor. This frequency divider is based on the long-period behaviour of the nonlinear circuits generating chaos. The various frequency dividing operations are observed at the input frequency of 50 GHz. Chaotic operation is also observed     

2.4GHz动态CMOS分频器的设计

对现阶段的主流高速CMOS分频器进行分析和比较,在此基础上设计一种采用TSPC(truesingle phase clock)和E-TSPC(extended TSPC)技术的前置双模分频器电路.该分频器大大提高了工作频率,采用0.6μm CMOS工艺参数进行仿真的结果表明,在5V电源电压下,最高频率达到3GHz,功耗仅为8mW.     

10.7 GHz frequency divider using double layer silicon bipolarprocess technology

A high-speed bipolar process is described which offers high performance, low capacitances and high packing densities. The performance of the process is demonstrated by a 1/8 frequency divider operating at a room temperature frequency of 10.7 GHz. This is considered to be the fastest for any silicon bipolar circuit     

Static 7 GHz frequency divider IC based on a 2 ?m Si bipolar technology

A static 8:1 frequency divider IC operating at up to 7 GHz has been realised using a preproduction silicon bipolar technology with 2 ?m lithography. This technology is characterised by a self-aligned double polysilicon emitter-base structure and oxide wall isolation. The high upper frequency limit, not yet achieved with comparable 2 ?m technologies, was attained by careful circuit design and optimisation.     

应用于26 GHz-41 GHz频率综合器的高速可编程分频器的设计

毫米波频率综合器中的重要模块之一高速可编程多模分频器,它主要用于对VCO的输出信号进行分频从而获得稳定的本振信号,它的性能影响整个毫米波频率综合器性能。本文设计的一种高速、低功耗、分频比可变的分频器具有非常重要的意义[1]。根据26 GHz-41 GHz硅基锁相环频率综合器的系统指标,本文基于TSMC 45nm CMOS工艺,设计实现了一种高速可编程分频器。本文采用注入锁定结构分频结构实现高速预分频,该结构可以实现在0 d Bm的输入功率下实现25 GHz-48 GHz的分频范围、最低功耗为:2.6 m W。基于脉冲吞咽计数器的可编程分频器由8/9双模分频器和可编程脉冲吞咽计数器组成。其中8/9双模分频器由同步4/5分频器和异步二分频构成,工作频率范围10 GHz-27 GHz,最低输入幅度为:300 m V,最低功耗为:1.6 m V。可编程吞咽计数器采用改进型带置数功能的TSPC D触发器,该可编程分频器的最大工作范围:25 GHz;最小功耗为:363μW。本文设计的高速可编程多模分频器,可以实现32-2 062的分频比;当工作于28 GHz时,相位噪声小于-159 dBc/Hz。动态功耗为5.2 m W。     

1 V 2 GHz CMOS frequency divider

A new frequency divider, called differential injection locking, is proposed. The proposed divider has no transistor stacking to suppress the performance degradation due to supply voltage reduction. It is shown that the proposed frequency divider achieves 2 GHz with 1 V supply voltage and 540 /spl mu/W power consumption.     

Substrate current based avalanche multiplication measurement in 120 GHz SiGe HBTs

A new substrate current-based technique for measuring the avalanche multiplication factor (M - 1) in high-speed SiGe heterojunction bipolar transistors (HBTs) is proposed. The technique enables M - 1 measurement at high operating current densities required for high-speed operation, where conventional techniques fail because of self-heating. Using the proposed technique, M - 1 was measured up to 10 mA//spl mu/m/sup 2/ on SiGe HBTs featuring 120 GHz peak f/sub T/ which occurs at J/sub C/ about 7 mA//spl mu/m/sup 2/. Implications for circuit applications are also discussed.     

Ultra-compact 350 GHz gain-bandwidth product 40 Gbit/s predriver IC in SiGe bipolar technology

An ultra-compact 0.36 mm/sup 2/ differential wideband amplifier fabricated using SiGe technology is presented. Measurements show an on-wafer gain of 20.8 dB and a 3 dB cutoff frequency of 32.0 GHz. The mounted amplifier's gain is 19.5 dB. The circuit is intended to operate as a predriver in a 40 Gbit/s fibre-optic communication system.     

83GHz InP DHBT静态分频器

A static frequency divider is presented using 0.7μm lnP DHBTs with 280 GHz ft/fmax. The divider is based on ECL master-slave D-flip-flop topology with 30 HBTs and 20 resistors with a chip size 0.62 ×0.65 mm^2. The circuits use peaking inductance as a part of the loads to maximize the highest clock rate. Momentum simulation is used to accurately characterize the effect of the clock feedback lines at the W band. Test results show that the divider can operate from 1 GHz up to 83 GHz. Its phase noise is 139 dBc/Hz with 100 kHz offset. The power dissipation of divider core is 350 mW.     

96-GHz static frequency divider in SiGe bipolar technology

A static frequency divider designed in a 210-GHz f/sub T/, 0.13-/spl mu/m SiGe bipolar technology is reported. At a -5.5-V power supply, the circuit consumes 44 mA per latch (140 mA total for the chip, with input-output stages). With single-ended sine wave clock input, the divider is operational from 7.5 to 91.6 GHz. Differential clocking under the same conditions extends the frequency range to 96.6 GHz. At -5.0 V and 100 mA total current (28 mA per latch), the divider operates from 2 to 85.2 GHz (single-ended sine wave input).     

2-46.5 GHz quasi-static 2:1 frequency divider IC usingInAlAs/InGaAs/InP HEMTs

The authors report a 2-46.5 GHz quasi-static frequency divider IC using InAlAs/InGaAs/InP HEMTs. Wideband clock/data buffers and an HLO (high-speed latching operation)-type T-FF were incorporated to enhance the operating range. The IC was mounted on a dedicated IC package and operated up to 45.2 GHz