湿N2退火HfTiO和HfO2栅介质 Ge MOS电特性研究

采用反应磁控溅射方法在Ge衬底上分别制备了HfTiO和HfO2高κ栅介质薄膜,并研究了湿N2和干N2退火对介质性能的影响。由于GeOx在水气氛中的水解特性,湿N2退火能分解淀积过程中生长的锗氧化物,降低界面态和氧化物电荷密度,有效提高栅介质质量。测量结果表明,湿N2退火Al/HfTiO/n-GeMOS和Al/HfO2/n-GeMOS电容的栅介质等效厚度分别为3.2nm和3.7nm,-1V栅偏压下的栅极漏电流分别为1.08×10-5A/cm2和7.79×10-6A/cm2。实验结果还表明,HfTiO样品由于Ti元素的引入提高了介电性能,但是Ti的扩散也使得界面态密度升高。     

Low-temperature conductance measurements of surface states in HfO2–Si structures with different gate materials

Metal-oxide-semiconductor capacitors based on HfO₂ gate stack with different metal and metal compound gates (Al, TiN, NiSi and NiAlN) are compared to study the effect of the gate electrode material on the trap density at the insulator–semiconductor interface.C–V and G–ω measurements were made in the frequency range from 1 kHz to 1 MHz in the temperature range 180–300 K. From the maximum of the plot G/ω vs. ln(ω) the density of interface states was calculated, and from its position on the frequency axis the trap cross-section was found. Reducing temperature makes it possible to decrease leakage current through the dielectric and to investigate the states located closer to the band edge.The structures under study were shown to contain significant interface trap densities located near the valence band edge (around 2×10¹¹ cm⁻²eV⁻¹ for Al and up to (3.5–5.5)×10¹² cm⁻² eV⁻¹ for other gate materials). The peak in the surface state distribution is situated at 0.18 eV above the valence band edge for Al electrode. The capture cross-section is 5.8×10⁻¹⁷ cm² at 200 K for Al–HfO₂–Si structure.     

Optimization of electric properties of high-k zirconium dioxide by varying deposition and annealing conditions

ZrO₂ thin films with a smooth surface were synthesized on silicon by atomic vapor deposition™ using Zr[OC(CH₃)₃]₄ as precursor. The maximum growth rate (7 nm min⁻¹) and strongest crystalline phase were obtained at 400 °C. The increase of the deposition temperature reduced the deposition rate to 0.5 nm min⁻¹ and changed the crystalline ZrO₂ phase from cubic/tetragonal to monoclinic. These films showed no enhancement of the dominating monoclinic phase by annealing. The values of the dielectric constant (up to 32) and leakage current density (down to 1.2×10⁻⁶ A cm⁻² at 1×10⁶ V cm⁻¹) varied depending on the deposition temperature and film thickness. The midgap density of interface states was N_it=5×10¹¹ eV⁻¹ cm⁻². The leakage current and the density of interface states were lowered by the annealing to 10⁻⁷ A cm⁻² at 1×10⁶ V cm⁻¹ and to 10¹⁰ eV⁻¹ cm⁻², respectively. However, this also led to a decrease of the dielectric constant.     

Charge trapping and interface states in hydrogen annealed HfO2–Si structures

Metal–oxide–semiconductor (MOS) capacitors based on HfO₂ gate stacks with Al and TiN gates are compared to study the effect of the gate electrode material to the properties of insulator–semiconductor interface. The structures under study were shown to contain interface trap densities of around 2 × 10¹¹ cm⁻² eV⁻¹ for Al gate and up to 5.5 × 10¹² cm⁻² eV⁻¹ for TiN gate. The peak in the surface state distribution was found at 0.19 eV above the valence band edge for Al electrode. The respective capture cross-section is 6 × 10⁻¹⁷ cm² at 200 K.The charge injection experiments have revealed the presence of hole traps inside the dielectric layer. The Al-gate structure contains traps with effective capture cross-section of 1 × 10⁻²⁰ cm², and there are two types of traps in the TiN-gate structure with cross-sections of 3.5 × 10⁻¹⁹ and 1 × 10⁻²⁰ cm². Trap concentration in the structure with Al electrode was considerably lower than in the structure with TiN electrode.     

Electrical properties of oxidized polycrystalline silicon as a gate insulator for n-type 4H-SiC MOS devices

MOS capacitors were produced on n-type 4H-SiC using oxidized polycrystalline silicon (polyoxide). The polyoxide samples grown by dry oxidation without an anneal had a high interface state density (D_it) of 1.8 × 10¹² cm⁻² eV⁻¹ and the polyoxide samples grown by wet oxidation had a lower D_it of 1.2 × 10¹² cm⁻² eV⁻¹ (both at 0.5 eV below the conduction band). After 1 h Ar annealing, the D_it of wet polyoxide was reduced significantly to 2.6 × 10¹¹ cm⁻² eV⁻¹ (at 0.5 eV below the conduction band). Dry polyoxide exhibits higher breakdown electric fields than wet polyoxide. The interface quality and breakdown characteristics of polyoxide are comparable to published results of low-temperature CVD deposited oxides.     

Examination and evaluation of La2O3 as gate dielectric for sub-100 nm CMOS and DRAM technology

High-k gate dielectric La₂O₃ thin films have been deposited on Si(1 0 0) substrates by molecular beam epitaxy (MBE). Al/La₂O₃/Si metal-oxide–semiconductor capacitor structures were fabricated and measured. A leakage current of 3 × 10⁻⁹ A/cm² and dielectric constant between 20 and 25 has been measured for samples having an equivalent oxide thickness (EOT) 2.2 nm. The estimated interface state density D_it is around 1 × 10¹¹ eV⁻¹ cm⁻². EOT and flat-band voltage were calculated using the NCSU CVC program. The chemical composition of the La₂O₃ films was measured using X-ray photoelectron spectrometry and Rutherford backscattering. Current density vs. voltage curves show that the La₂O₃ films have a leakage current several orders of magnitude lower than SiO₂ at the same EOT. Thin La₂O₃ layers survive anneals of up to 900 °C for 30 s with no degradation in electrical properties.     

An investigation of surface state capture cross-sections for metal–oxide–semiconductor field-effect transistors using HfO2 gate dielectrics

MOSFETs and MOSCs incorporating HfO₂ gate dielectrics were fabricated. The I_DS–V_DS, I_DS–V_GS, gated-diode and C–V characteristics were investigated. The subthreshold swing and the interface trap density were obtained. The surface recombination velocity and the minority carrier lifetime in the field-induced depletion region measured from the gated diodes were about 2.73 × 10³ cm/s and 1.63 × 10⁻⁶ s, respectively. The effective capture cross section of surface state was determined to be 1.6 × 10⁻¹⁵ cm² using the gated-diode technique in comparison with the subthreshold swing measurement. A comparison with conventional MOSFETs using SiO₂ gate oxide was also made.     

Low temperature processed hafnium oxide: Structural and electrical properties

In this work hafnium oxide (HfO₂) was deposited by r.f. magnetron sputtering at room temperature and then annealed at 200 °C in forming gas (N₂+H₂) and oxygen atmospheres, respectively for 2, 5 and 10 h. After 2 h annealing in forming gas an improvement in the interface properties occurs with the associated flat band voltage changing from −2.23 to −1.28 V. This means a reduction in the oxide charge density from 1.33×10¹² to 7.62×10¹¹ cm⁻². After 5 h annealing only the dielectric constant improves due to densification of the film. Finally, after 10 h annealing we notice a degradation of the electrical film's properties, with the flat band voltage and fixed charge density being −2.96 V and 1.64×10¹² cm⁻², respectively. Besides that, the leakage current also increases due to crystallization. On the other hand, by depositing the films at 200 °C or annealing it in an oxidizing atmosphere no improvements are observed when comparing these data to the ones obtained by annealing the films in forming gas. Here the flat band voltage is more negative and the hysteresis on the C–V plot is larger than the one recorded on films annealed in forming gas, meaning a degradation of the interfacial properties.     

Investigation on interfacial and electrical properties of Ge MOS capacitor with different NH3-plasma treatment procedure

The effects of different NH₃-plasma treatment procedures on interfacial and electrical properties of Ge MOS capacitors with stacked gate dielectric of HfTiON/TaON were investigated. The NH₃-plasma treatment was performed at different steps during fabrication of the stacked gate dielectric, i.e. before or after interlayer (TaON) deposition, or after deposition of high-k dielectric (HfTiON). It was found that the excellent interface quality with an interface-state density of 4.79×10¹¹ eV^-1cm^-2 and low gate leakage current (3.43×10^-5A/cm² at V_g=1 V) could be achieved for the sample with NH₃-plasma treatment directly on the Ge surface before TaON deposition. The involved mechanisms are attributed to the fact that the NH₃-plasma can directly react with the Ge surface to form more Ge-N bonds, i.e. more GeO_xN_y, which effectively blocks the inter-diffusion of elements and suppresses the formation of unstable GeO_x interfacial layer, and also passivates oxygen vacancies and dangling bonds near/at the interface due to more N incorporation and decomposed H atoms from the NH₃-plasma.     

Radiation damage of Ge-on-Si devices

The radiation damage induced by 2-MeV electrons and 70-MeV protons in p⁺n diodes and p-channel MOS transistors, fabricated in epitaxial Ge-on-Si substrates is reported for the first time. For irradiation above 5×10¹⁵ e/cm², it is noted that both the reverse and forward current increase, and that the forward current is lower after irradiation for a forward voltage larger than about 0.5 V. The reason for this might be an increased resistivity of the Ge-on-Si substrate. For p-MOSFETs, for a 1×10¹⁶ e/cm² dose, a slight negative shift of the threshold voltage and a decrease of the drain current for input and output characteristics have been observed. In addition, g_m decreases after irradiation. The degradation of the transistor performance is thought to be due to irradiation-induced positive charges in the high-κ gate dielectric. The induced lattice defects are also mainly responsible for the leakage current increase of the irradiated diodes.     

Physical and electrical properties of low dielectric constant self-assembled mesoporous silica thin films

The physical and electrical properties of self-assembled mesoporous silica thin films with defined 2D hexagonal porous architectures have been evaluated in the following study. Self-assembled mesoporous silica thin (MPS) films have been prepared by evaporation-induced self-assembly (EISA) methods using the triblock copolymer (C₂H₂)₁₀₆(C₃H₃)₇₀(C₂H₂)₁₀₆ (Pluronic F127^®). The MPS films exhibit remarkably low level leakage currents (1 × 10⁻⁸–1 × 10⁻⁷ A/cm² at 1 MV/cm¹) and high breakdown voltages (>3 MV/cm¹). The films have dielectric constants of approximately 2.3, low dielectric loss factors of 0.01–0.03 and exhibit negligible frequency dispersion of dielectric constant between 100 kHz and 1 MHz. The effect of physisorbed water (humidity) upon the electrical properties of the films is also investigated using capacitance–voltage techniques.     

Effects of oxygen partial pressure on structural and electrical characteristics of HfAlO high-k gate dielectric grown on strained SiGe by pulsed-laser deposition

Dependence of oxygen partial pressures on structural and electrical characteristics of HfAlO (Hf:Al=1:1) high-k gate dielectric ultra-thin films grown on the compressively strained Si₈₃Ge₁₇ by pulsed-laser deposition were investigated. The microstructure and the interfacial structure of the HfAlO thin films grown under different oxygen partial pressures were studied by transmission electron microscopy, and the their electrical properties were characterized by capacitance–voltage (C−V) and conductance–voltage measurements. Dependence of interfacial layer thickness and C–V characteristics of the HfAlO films on the growth of oxygen pressure was revealed. With an optimized oxygen partial pressure, an HfAlO film with an effective dielectric constant of 16 and a low interface state density of 2.1×10¹⁰ cm⁻² eV⁻¹ was obtained.     

ZrON/GeON 双钝化层改善Ge MOS器件的界面特性和电特性

本文研究了利用等离子体氮化形成ZrON/GeON双钝化层制备Ge MOS器件的界面特性和电特性。结果发现,相比于N2等离子处理,NH3等离子处理制备的双钝化层显著改善了器件的界面和电特性,获得了低的界面态密度 (Dit = 1.64×1011 cm-2 eV-1)和栅极漏电流(Jg = 9.32×10-5 A cm-2@Vfb +1 V),小的电容等效厚度 (CET = 1.11 nm)以及高的k值 (32). XPS分析表明,由NH3等离子体分解出的H原子和NH基团可以有效促进Ge表面不稳定低k GeOx的挥发,从而形成了高质量的GeON钝化层;且NH3等离子体氮化导致更多氮在ZrON/GeON中结合,能更有效阻止O、Ti、Ge等元素间的相互扩散,从而获得好的界面质量和电特性。     

High air stability of threshold voltage on gate bias stress in pentacene TFTs with a hydroxyl-free and amorphous fluoropolymer as gate insulators

We investigated the air stabilities of threshold voltages (V_th) on gate bias stress in pentacene thin-film transistors (TFTs) with a hydroxyl-free and amorphous fluoropolymer as gate insulators. The 40-nm-thick thin films of spin-coated fluoropolymer had excellent electrical insulating properties, and the pentacene TFTs exhibited negligible current hysteresis, low leakage current, a field-effect mobility of 0.45 cm²/Vs and an on/off current ratio of 3 × 10⁷ when it was operated at −20 V in ambient air. After a gate bias stress of 10⁴ s, a small V_th shift below 1.1 V was obtained despite non-passivation of the pentacene layer. We have discussed that the excellent air stability of V_th was attributed to the insulator surface without hydroxyl groups.     

Investigation of high-K gate stacks with epitaxial Gd2O3 and FUSI NiSi metal gates down to CET=0.86 nm

Novel gate stacks with epitaxial gadolinium oxide (Gd₂O₃) high-k dielectrics and fully silicided (FUSI) nickel silicide (NiSi) gate electrodes are investigated. Ultra-low leakage current densities down to 10^–7 A cm^–2 are observed at a capacitance equivalent oxide thickness of CET=1.8 nm. The influence of a titanium nitride (TiN) capping layer during silicidation is studied. Furthermore, films with an ultra-thin CET of 0.86 nm at a Gd₂O₃ thickness of 3.1 nm yield current densities down to 0.5 A cm⁻² at V_g=+1 V. The extracted dielectric constant for these gate stacks ranges from k=13 to 14. These results emphasize the potential of NiSi/Gd₂O₃ gate stacks for future material-based scaling of CMOS technology.     

Investigation of strontium tantalate thin films for high-k gate dielectric applications

Strontium tantalate (STO) films were grown by liquid-delivery (LD) metalorganic chemical vapor deposition (MOCVD) using Sr[Ta(OEt)₅(OC₂H₄OMe)]₂ as precursor. The deposition of the films was investigated in dependence on process conditions, such as substrate temperature, pressure, and concentration of the precursor. The growth rate varied from 4 to 300 nm/h and the highest rates were observed at the higher process temperature, pressure, and concentration of the precursor. The films were annealed at temperatures ranging from 600 to 1000 °C. Transmission electron microscopy (TEM), X-ray diffraction (XRD), and ellipsometry indicated that the as-deposited and the annealed films were uniform and amorphous and a thin (>2 nm) SiO₂ interlayer was found. Crystallization took place at temperatures of about 1000 °C. Annealing at moderate temperatures was found to improve the electrical characteristics despite different film thickness (effective dielectric constant up to 40, the leakage current up to 6×10⁻⁸ A/cm², and lowest midgap density value of 8×10¹⁰ eV⁻¹ cm⁻²) and did not change the uniformity of the STO films, while annealing at higher temperatures (1000 °C) created voids in the film and enhanced the SiO₂ interlayer thickness, which made the electrical properties worse. Thus, annealing temperatures of about 800 °C resulted in an optimum of the electrical properties of the STO films for gate dielectric applications.     

A study on the improved programming characteristics of flash memory with Si3N4/SiO2 stacked tunneling dielectric

The programming characteristics of memories with different tunneling-layer structures (Si₃N₄, SiO₂ and Si₃N₄/SiO₂ stack) dielectrics are investigated using 2-D device simulator of MEDICI. It is theoretically confirmed that the memory with the SiO₂/Si₃N₄ stacked tunneling layer exhibits better programming characteristics than ones with single tunneling layer of SiO₂ or Si₃N₄ for programming by channel hot electron (CHE) injection. A 10-μs programming time with a threshold-voltage shift of 5 V can be obtained for the memory with SiO₂/Si₃N₄ stacked tunneling layer at V_cg = 10 V and V_ds = 3.3 V. This is attributed to the fact that the floating-gate voltage is close to drain voltage for the stacked tunneling dielectric (TD), and thus the CHE injection current is the largest. Furthermore, optimal substrate concentration is determined to be 5 × 10¹⁶–2 × 10¹⁷ cm⁻³, by considering a trade-off between the programming characteristics and power dissipation/lifetime of the devices. Lastly, the effects of interface states on the programming characteristics are investigated. Low interface-state density gives short programming time and small post-programming control-gate current.     

Study of electrically active defects in n-GaN layer

Deep level defects in both p⁺/n junctions and n-type Schottky GaN diodes are studied using the Fourier transform deep level transient spectroscopy. An electron trap level was detected in the range of energies at E_c−E_t=0.23–0.27 eV with a capture cross-section of the order of 10⁻¹⁹–10⁻¹⁶ cm² for both the p⁺/n and n-type Schottky GaN diodes. For one set of p⁺/n diodes with a structure of Au/Pt/p⁺–GaN/n–GaN/n⁺–GaN/Ti/Al/Pd/Au and the n-type Schottky diodes, two other common electron traps are found at energy positions, E_c−E_t=0.53–0.56 eV and 0.79–0.82 eV. In addition, an electron trap level with energy position at E_c−E_t=1.07 eV and a capture cross-section of σ_n=1.6×10⁻¹³ cm² are detected for the n-type Schottky diodes. This trap level has not been previously reported in the literature. For the other set of p⁺/n diodes with a structure of Au/Ni/p⁺–GaN/n–GaN/n⁺–GaN/Ti/Al/Pd/Au, a prominent minority carrier (hole) trap level was also identified with an energy position at E_t−E_v=0.85 eV and a capture cross-section of σ_n=8.1×10⁻¹⁴ cm². The 0.56 eV electron trap level observed in n-type Schottky diode and the 0.23 eV electron trap level detected in the p⁺/n diode with Ni/Au contact are attributed to the extended defects based on the observation of logarithmic capture kinetics.     

Effect of annealing on the properties of low-k nanoporous SiO2 films prepared by sol–gel method with catalyst HF

Using hydrofluoric acid (HF) as catalyst, nanoporous SiO₂ thin film was synthesized by sol–gel method. By scanning electron microscopy, Fourier transform infrared spectra, thermo gravimetric and differential thermal analysis, ellipsometry, capacitance–voltage and current–voltage measurements, the effects of annealing on film properties were discussed in detail. The introduction of HF results in the less polarizability, the preferable microstructures and the improved thermal stability of the nanoporous silica films. After thermal annealing at 450 °C, the crack-free films with strong hydrophobicity, ultra-low dielectric constant of 1.65, porosity of 78%, and leakage current density of 1.3 × 10⁻⁸ A cm⁻² were obtained.     

Optical and electrical characterization of the electron beam gun evaporated TiO2 film

We report measured evolutions of the optical band gap, refractive index and relative dielectric constant of TiO₂ films obtained by electron beam gun evaporation and annealed in an oxygen environment. A negative shift of the flat band voltage with increasing annealing temperatures, for any film thickness, is observed. A dramatic reduction of the leakage current by about four orders of magnitude to 5×10⁻⁶ A cm⁻² (at 1 MV cm⁻¹) after 700°C and 60 min annealing is found for films thinner than 15 nm. The basic carrier transport mechanisms at different ranges of applied voltage such as hopping, space charge limited current and Fowler–Nordheim is established. An equivalent SiO₂ thickness in order of 3.5 nm is demonstrated.