InGaAs/InP double-heterostructure bipolar transistors with near-ideal β versus ICcharacteristic

InGaAs/InP double-heterostructure bipolar transistors (DHBT's) with current gain β ∼ 630 have been realized using gas-source molecular beam epitaxy (GSMBE). These devices exhibit near-ideal β versus ICcharacteristic (i.e., β independent of IC) with a small-signal gainh_{fe} sim 180atI_{C} sim 2nA. In comparison, we findbeta sim I_{C}^{0.5}for a high-quality AlGaAs/GaAs HBT grown by OMCVD. The higher emitter injection efficiency at low collector current levels found in the InGaAs/InP DHBT is due to at least a factor 100 smaller surface recombination current.     

Verification of the integral charge-control relation for high-speed bipolar transistors at high current densities

Gummel's integral charge-control relation (ICCR) IC= (const/Qp).exp (VBE/VT) is an important basis for developing self-consistent compact transistor models for the high-current region (including quasi-saturation). Such models are required for the simulation of future high-speed IC's with a high integration level. Unfortunately, the simplifying assumptions on which the ICCR is based seem to be doubtful especially for very fast transistors. Therefore, in this paper, the ICCR and its assumptions are checked via numerical simulation of such transistors (fT≈ 7-8 GHz). It is found that the one-dimensional ICCR is a fairly good approximation far into the high-current region. This satisfactory result is mainly due to the partial compensation of the influences of the spatially dependent doping concentration on both the electron mobility µnand the effective intrinsic density niewithin the product µnn²ie. Only in the emitter and in the emitter-base space-charge region there is a strong increase of this product which, in conjunction with the increasing contribution of the hole charge in these regions, was proved to be responsible for the errors observed at high current levels. The ICCR can also be applied to a two-dimensional transistor by additionally taking into account the excess hole charge stored outside the internal transistor for the determination of Qp. Thus the contribution of the minority charges can still be determined experimentally by measuring τf(IC).     

Threshold voltage scattering of GaAs MESFET's fabricated on LEC-grown semi-insulating substrates

Threshold voltage standard deviation (sigma V_{th}) for MESFET's on a liquid encapsulated Czochralski (LEC) grown GaAs wafer was investigated, in connection with dislocation distribution. Threshold voltage (Vth) scattering was found to be strongly correlated to the dislocation cell network structure in the substrate. This dislocation cell network is characteristic of the LEC-grown crystal. At largesigma V_{th}region, strongly networked dislocation cell structure was observed. In the area where dislocations distributed randomly without network structure,sigma V_{th}was small in spite of high dislocation density. For FET's located in the dislocation-free region inside the network cell, low drain current Idsand high Vthwere recognized directly by a curve tracer. The experimental results regarding the dislocation network effect on Vthscattering are discussed along with cathodoluminescence study results.     

The temperature dependence of the DC base and collector currents in silicon bipolar transistors

Detailed measurements have been made of the base and collector-current characteristics of both n-p-n and p-n-p silicon transistors as a function of temperature. The collector current shows ideal behavior over the temperature range -60 to 150°C in thatI_{C} infin exp (eV_{BE}/kT). On the other hand, the base current is nonideal:I_{B} infin exp (eV_{BE}/nkT), wheren > 1.0. The nonideality of IBis the main source of the temperature dependence ofh_{FE} = I_{C}/I_{B}. There is no evidence for bandgap narrowing in the devices we have investigated. The temperature dependence of the collector current is given byI_{C} infin T_{m} exp (-e E_{g0}/kT) exp (eV_{BE}/kT), wherem = 1.4or 1.7 for n-p-n or p-n-p devices, respectively.E_{g0} = 1.19 pm 0.01eV. This result is consistent with the findings of others. The base current is a complicated function of temperature due to the presence of nonideal components.     

The area of safe operation of transistors for switching operation

A thermal feedback model is presented for the analytical definition of the ASO (Area of Safe Operation) for transistors in switching operations. This area is narrowed by the "second breakdown in p-n junction," and the approximate representation of the breakdown threshold is presented. This model consists of a forward and feedback energy flow with gains A and B, respectively.A = V_{CE} times M, B = K times theta times alpha_{R} times I_{e}. Therefore, the condition of the breakdown can be introduced as1 - AB = 0, whereMis the current multiplication factor, θ is transient thermal resistance,Kis a newly introduced current concentration factor, and αRis the temperature coefficient of Ie. Experimental results are also reported for a germanium alloy type transistor.     

Three terminal measurements of current amplification factors of controlled rectifiers

By treating the Silicon Controlled Rectifier as a hook transistor and measuring its current amplification factor as a function of frequency, the small-signal low-frequency alphasalpha_{n0}andalpha_{p0}of the n-p-n and p-n-p transistor sections constituting the Controlled Rectifier can be separately determined, together with fnand fp, their respective cutoff frequencies. Repeating these measurements at a number of bias currents, coupled with a numerical integration, enables one to separate the component dc currents of the two transistor sections as well as their dc alphas αnand αP. Measurements indicate that switching from high to low impedance is controlled byalpha_{n0} + alpha_{p0} = 1and notalpha_{n} + alpha_{p} = 1as has hitherto been implied. There are good theoretical reasons for this which have led to a redefinition of the breakover conditions. These are shown to be given by infinite output admittance and not infinite current as has so far been thought to be the case.alpha_{n0}andalpha_{p0}were also measured and plotted as a function of voltage bias.     

Tunneling currents in the copper sulfide/cadmium sulfide heterojunction

The parameters controlling the photovoltaic properties of the Cu2S/CdS heterojunction have been investigated. It is found that the behavior of the short-circuit current and the open-circuit voltage are describable in terms of a deep, donor-like level in the CdS region adjacent to the metallurgical interface. When tunneling from this level into the Cu2S is the mechanism controlling the current flow, theJ_{SC}-V_{OC}characteristics of the device are described by the equationJ_{SC} = J_{00} exp (a_{i}(E_{I} - Phi_{T}_{0})) {exp (a_{i}q V_{OC})-1}where JSCis the short-circuit current, J00is the current preexponential factor,Phi _{T}_{0}is the zero-bias barrier height in the CdS, EIis the ionization energy of the deep donor, VOCis the open-circuit voltage, and aiis a tunneling factor dependent on the net positive charge density in the CdS near the interface. The relative probability of tunneling from this level to the Cu2S is derived, as is the probability of tunneling from the level to the CdS conduction band. The photocapacitance effects observed in this junction are attributed to the joint action of this level and an acceptor state due to copper in the CdS. Combining the results from the tunneling calculation, theJ_{SC}-V_{OC}data, and the quenching spectra of the photocapacitance, the ionization energy of the donor level is determined to be 0.45 eV and the density of these levels exceeds 10¹⁹cm^-3near the interface. The donor level acts as a recombination center, reducing JSC, and as a tunneling center, reducing VOC. Since these levels exist in junctions produced by the dipping method or by the dry method, they set fundamental limits to the efficiency of devices fabricated using these methods.     

Kinetic model of photolytic O2(1Δ) generation

Kinetic analysis of photolysis of O3:O2:He mixtures by UV light has been studied. Dependence of O2(¹Δ) yield on partial pressures, flashlamp intensity, and duration was investigated. Results indicate sufficient O2(¹Δ) yield for operation of a high-power atomic iodine laser on the I*(²P_{1/2})underrightarrow{1.31 mu}m I(²p_{3/2}) transition.     

1/f noise in n-channel silicon-gate MOS transistors

It is found that equivalent gate noise power for l/f noise in n-channel silicon-gate MOS transistors at near zero drain voltage at room temperature is empirically described by two noise terms, which vary asK_{1}(q/C_{ox}) (V_{G} -V_{T})/f and K_{2}(q/C_{ox})^{2}/f, where V_{G}is gate voltage, VTis threshold Voltage, and Coxis gate-oxide capacitance per unit area. Unification of carrier-density fluctuation (McWhorter's model)and mobility fluctuation (Hooge's model) can account for the experimental data. The comparison between the theory and experiment shows that the carrier fluctuation term K2is proportional to oxide-trap density at Fermi-level. The mobility fluctuation term K1is correlated to K2, being proportional toradic K_{2}. The origin of this correlation is yet to be clarified.     

A model of write-inhibition in dynamic injection MNOS

Dynamic Injection MNOS (DIMNOS) memory devices feature high-speed writing, 5-V drain voltage, and MNOS backup one-transistor-type dynamic RAM's. They are written on MNOS, like conventional one-transistor-type dynamic RAM's, when high writing voltage is applied to the MNOS gate. In experiments with DIMNOS, the threshold-voltage shift (Delta V_{th}) of MNOS in the writing mode does not depend very much on temperature;Delta V_{th}in the write-inhibited mode depends hardly at all on temperature; andDelta V_{th}in the write-inhibited mode decreases under the condition that the product of the number of attempts and pulsewidth is constant when he pulsewidth is longer than 10^-4s. The proposed model in the write-inhibited mode means that weak avalanche occurs due to field concentration between the control transistor and MNOS memory region. As a result, hot electrons are injected between the ultrathin SiO2and Si3N4films of MNOS. This model is supported by the above mentioned experimental results in the write-inhibited mode.     

一种高精度带隙基准源和过温保护电路

设计了一种适用于P阱CMOS工艺的高精度带隙基准源及过温保护电路。基准源信号输出由两路电流相加实现：一路是正比于双极晶体管的发射极一基极电压的电流(IVBE)，另一路是基准源内产生的正比于绝对温度的电流(IPTAT)；同时，利用这两路电流的不同温度特性，通过直接电流比较的方法，简单地实现了高精度的过温保护电路。     

Trapped-electron and generated interface-trap effects in hot-electron-induced MOSFET degradation

A new experimental method is proposed to distinguish the electron-trapping effect in the gate oxide from the interface-trap generation effect in hot-electron-induced nMOSFET degradation. In this method, by selecting the appropriate bias conditions, hot electrons and/ or hot holes are intentionally injected into the oxide region above the channel outside the drain layer, which affects MOSFET characteristics such as threshold voltage and transconductance. The negative charges of electrons trapped in the oxide during hot-electron injection are completely compensated for by the positive charges of subsequently injected and trapped holes, and the trapped electron effect in the degradation is eliminated. Using this method, the causes for hot-electron-induced transconductance degradation (Δgm/gm) are analyzed. As the degradation increases, the trapped-electron effect decreases, and the generated interface-trap effect increases. The relationship of (Δgm/gm)_{it}, =A(Δgm/gm) --Bis obtained, where (Δgm/gm)_{it} is gmdegradation due to generated interface-traps, andAandBare fixed numbers. Furthermore φ_{it}/λ (the ratio of the critical value in hot-electron energy for interface-trap generation to the mean free path of hot electrons in Si) is experimentally obtained to be 5.7 × 10⁶eV/cm. Using λ = 9.2 nm [1], a value of φ_{it} = 5.2 eV is derived.     

Low-frequency noise in permeable base transistors

The predominant noise is1/fnoise and consists of two parts: a) Noise varying asImin{C}max{2}, generated mostly with conducting channel and predominating for normal values of the collector voltage VCE. b) Noise at low VCEand practically independent of VCE; it is generated chiefly in the space charge region around the base grating and gives collector1/fnoise atV_{CE} = 0. The turnover frequency of the first noise source lies at about 20 MHz forV_{CE} = 0.30V,V_{BE} = 0.20V. At sufficiently high frequencies the PBT shows thermal noise of the output conductanceg_{c0}at zero bias. Generation-recombination noise is observed at large VBEand low VCEand comes mostly from the space charge region around the base grating.     

Static V-I relationships in transistors at high injection levels

At high injection levels the static V-I characteristics of p-n junction devices must be modified to account for nonlinear transport mechanisms and for relationships between the injected carrier concentrations and the applied voltages which differ from the familiar low-injection relationships. These carrier-concentration-voltage relationships differ in part because of ohmic voltage drops and in part because of conductivity-modulation effects. It is difficult to explore experimentally the high-level extensions of p-n junction theory in diodes because ohmic drops usually dominate the VI characteristics at high levels. However, these effects can be studied experimentally in a transistor which operates in the avalanche mode, with zero base current, because the ohmic drops can be suppressed. Experimental results are presented which support an analysis of the high-level V-I characteristics of the emitter junction of a transistor. This analysis does not predict ane^{qV/2kT}dependence of the junction current at high levels, but yields instead ane^{qV/(1 pm m)kT}dependence, where m is a parameter having a value of about 0.3 in germanium, and V is the applied voltage less the ohmic drops. The plus sign applies for a p⁺-n junction while the minus sign holds for an n⁺-p junction. In accordance with this theory, complementary n-p-n and p-n-p transistors exhibit markedly different behavior at high injection levels.     

Hot-electron-induced MOSFET degradation at low temperatures

The n-channel LDD MOSFET lifetime is observed to followtau=(A/I_{d})(I_{sub}/I_{d})^{-n}from 77 to 295 K when the device is stressed near the maximum Isub. Here Idis the drain current andAis the proportionality constant. The experimental result indicates thatnis approximately 2.7 and is independent of temperature. However, the proportionality constantAfollowsA = A_{0} exp (-E_{a}/kT), withE_{a} = 39meV. The smaller proportionality constant at low temperatures suggests that hot-electron injection (HEI) degradation is caused by the electron trapping in the oxide.     

Investigation of AlGaAs/GaAs superlattice-emitter resonanttunneling bipolar transistor (SE-RTBT)

A bipolar transistor with an i-Al_0.5Ga_0.5As/n⁺-GaAs superlattice emitter as both hole reflection barriers and electron tunneling barriers has been fabricated successfully. The AlGaAs/GaAs potential spike is eliminated by moving the heterointerface away from the emitter-base junction. Both the turn-on voltage of emitter-base and base-collector junctions are almost identical for the same current level. The room-temperature common-emitter current gain is over 60, and a collector-emitter offset voltage of 55 mV has been obtained with a base-to-emitter doping ratio of 10. Multiple differential negative resistance phenomena and different transistor operating regimes have been observed due to the tunneling effects in the AlGaAs/GaAs superlattice at 77 K. Calculated results are in agreement with experimental ones. Because of the existence of high peak-to-valley current ratios as well as current gain over 65, the SE-RTBT is suitable for multivalued logic circuit applications with relatively reduced complexity     

The NEGIT: A surface-controlled negative impedance transistor

A Negative impedance transistor (NEGIT) is realized by controlling base surface recombination in a bipolar transistor by biasing a gate on the oxide over the emitter-base junction. This gate is attached to the collector by conventional metallization. As VCEincreases, the active region is robbed of base current causing ICto decrease. It is shown theoretically, and confirmed experimentally, that both the magnitude of the effect and the voltage range over which the negative resistance occurs, depend strongly on base oxide thickness and base surface doping, and are dominated by the base surface immediately adjacent to the emitter-base junction. Thus very small area devices are possible in both discrete and IC versions, for either high or low voltage operation, with only minor changes in existing technology. Although only sample applications are shown, and frequencies employed only up to 11 MHz, a wide variety of applications are possible.     

Dependence of channel electric field on device scaling

It has been shown previously that the maximum channel electric field Emin a MOSFET is the most important parameter relating to all hot-electron effects and that Emcan be represented as (V_{DS} - V_{DSAT})/l, wherelmay be regarded as the effective length of the velocity-saturation region. The dependence of l on device geometries and process parameters is investigated in this letter. From both experiment and two-dimensional (2-D) simulation, it is found that Emhas a form of (V_{DS} - V_{DSAT})/ 0.22Tmin{ox}max{1/3}Xmin{j}max{1/2}. Channel length affects the saturation voltage, thus influencing the maximum channel electric field. The scaling of oxide thickness and junction depth, however, often has even greater effects on channel field. This semiempirical model of Emagrees with Emdeduced from ISUBwithin about 5 percent; it can predict ISUB, which has been empirically correlated with hot-electron degradations.     

Model for the channel-implanted enhancement-mode IGFET

A simple dc four-terminal "channel-implanted model" is developed for the enhancement-mode IGFET. The model accurately predicts the dependence of transistor threshold voltage and current gain on substrate bias. Modeled and measured threshold voltages are shown to agree to within 25 mV across a 15-V range of VSB. Modeled and measured transistor currents agree to within 5 percent across a 10-V range of VSBfor medium- to long-channel length transistors (L_{drawn} ge 2.5µm). The channel impurity profile is approximated as a constant effective impurity concentration NAEextending from the semiconductor surface through the implanted region to an effective implant depth XDE("box" profile approximation). At depths greater than XDE, the bulk substrate impurity concentration is approximated as a constant, NA. The model is composed of two threshold voltage equations, three drain current equations, two saturation voltage equations, and two boundary equations. All first-order model equations and all of their first derivatives are continuous at all boundaries. The model's continuity and its accuracy make it useful for circuit simulation. Extrapolation of channel concentration profile parameters NAE, XDE, and NAfrom measured threshold voltages yields information on implant profile and on field-implant impurity encroachment into the transistor channel.     

Geometrical factors in avalanche punchthrough erase

It is known that the surface potential of an IGFET can be raised to high levels by reverse-bias pulsing its source and drain. This high surface potential is contingent upon both punchthrough and avalanche injection of majority carriers into the surface region. Erase of some multilayer charge storage memory cells is accomplished using such an avalanche punchthrough erase (APTE) operation. In this paper the maximum surface potential achievable in this manner is assessed for a variety of geometries. The calculation is based upon a Fourier sine transform solution of Poisson's equation, coupled with the sampling theorem for spatially localized functions. The depletion width is determined self-consistently and is found to vary from a minimum value at mid-channel to a maximum value at the channel ends. It is found that the maximum surface potential is achieved for devices whose junction depth is comparable to or greater than the channel length. Under these conditions the surface potential can be as large as the reverse bias less the punchthrough voltage. To avoid serious short-channel behavior during normal read operations, it is suggested that the conditionNl^{2} > 2V_{D}kisin_{0}/ebe observed, whereN= doping level/cm³,l= half channel length, VD= drain voltage during read, K = dielectric constant of semiconductor, ∈0= permittivity of free space,e= electronic charge. Thus for a 2-µm channel length we recommend a junction depth ≥2 µm, and a doping level ≈6.5 × 10¹⁵/cm³for a memory cell which is to use APTE and a read voltageV_{D} simeq 5V.