A ΣΔ micro accelerometer with 6 µg/√Hz resolution and 130 dB dynamic range

This paper reports the implementation of a low noise, high dynamic-range ΣΔ readout for low cost capacitive Micro-Electro-Mechanical Systems (MEMS) accelerometers. The readout circuit sets the bandwidth of the ΣΔ loop through an extra feedback path, and hence allows the closed loop system to operate with the low noise characteristics similar to a second-order ΣΔ analog-to-digital converter. A thorough noise analysis of the proposed accelerometer shows that the mechanical noise is the most significant source and quantization noise is mostly eliminated. Dynamic range (DR) of the system is improved by minimizing the circuit noise and increasing the full scale range (FSR) by high-voltage pulse feedback. Utilization of these techniques allows the implementation of low cost, low noise, and high DR navigation-grade accelerometers, by eliminating the need for large proof mass, large area MEMS sensors. The proposed system can achieve a minimum of 6.0 µg/√Hz noise floor, 3.2 µg bias instability, and a maximum of 130 dB DR at 1 Hz. A FSR of ±20 g is reported for 6.2 µg/√Hz noise floor. This range can be increased up to ±40 g at the cost of noise performance and DR.     

Correction to: A subthreshold low-power CMOS LC-VCO with high immunity to PVT variations

This paper presents a capacitor-free low dropout (LDO) linear regulator based on a dual loop topology. The regulator utilizes two feedback loops to satisfy the challenges of hearing aid devices, which include fast transient performance and small voltage spikes under rapid load-current changes. The proposed design works without the need of a decoupling capacitor connected at the output and operates with a 0–100 pF capacitive load. The design has been taped out in a \(0.18\,\upmu \hbox {m}\) CMOS process. The proposed regulator has a low component count, area of \(0.012\, \hbox {mm}^2\) and is suitable for system-on-chip integration. It regulates the output voltage at 0.9 V from a 1.0–1.4 V supply. The measured results for a current step load from 250 to 500 \(\upmu \hbox {A}\) with a rise and fall time of \(1.5\,\upmu \hbox {s}\) are an overshoot of 26 mV and undershoot of 26 mV with a settling time of \(3.5\,\upmu \hbox {s}\) when \({C_L}\) between 0 and 100 pF. The proposed LDO regulator consumes a quiescent current of only \(10.5\,\upmu \hbox {A}\). The design is suitable for application with a current step edge time of 1 ns while maintaining \(\Delta V_{out}\) of 64 mV.     

Design and implementation of all MOS micro-power voltage reference circuit

In this work we are proposing the all MOST based reference voltage generating circuit, which utilizes the classical principle of addition of two voltages with opposite temperature coefficients. The targeted application of the proposed circuit is a low-dropout regulator which is used in a RF energy harvesting system. The proposed voltage reference circuit is implemented using a standard 0.18 μm CMOS technology. It generates the average reference voltage of 543.658 mV with an average temperature coefficient of 17.43 ppm/°C in the temperature range of ?40 to +85 °C, for the operating supply voltage ranging from 1.25 to 2 V. The maximum power consumption of the proposed architecture is ≈1.5 μW, including power dissipation in bias circuitry and the reference voltage generating core at 2 V supply voltage. The averaged measured line regulation is 1.642 mV/V. The measured power-supply rejection ratio without any filtering capacitor at 100 Hz and 1 MHz are ?62.24 and ?18.94 dB, respectively. Additionally, the measured noise density without any filtering capacitor at 10 Hz and 100 KHz is 20.54 and \(0.30\,\upmu \hbox {V}/\sqrt{\hbox{Hz}}\) , respectively. The proposed circuit has silicon area of ≈0.007 mm².     

On YASS’s Non-monotonic Security Performance

Recently, researchers have discovered unexpected bumps in the detection rate curve of yet another steganographic scheme (YASS). We refer to this abnormal phenomenon as non-monotonic security performance. This paper first analyzes this abnormality and points out that it is caused by the non-uniformity in probability of coincidence of \(8\,\times \,8\) embedding blocks and \(8\,\times \,8\) JPEG blocks. Based on this observation, we propose that further randomizing data embedding positions can overcome the non-monotonic security performance. Experimental results have demonstrated a complete removal of bumps in the detection rate curve of YASS after further randomization.     

Design of 0.5 V voltage-combiner based OTA with 60 dB gain 250 kHz UGB in CMOS

A gain enhancement technique for a pseudo differential OTA based on voltage combiner, suitable for sub-1 V supply is presented in this letter. The proposed technique uses a G _m boosted voltage combiner. Unlike the typical voltage combiner which has an approximated gain of \(2\,\frac{{\text{V}}}{{\text{V}}}\), this voltage combiner can produce gain more than \(5\,\frac{{\text{V}}}{{\text{V}}}\). So it help us achieve nearly 60 dB DC gain with 250 kHz UGB for the pseudo differential OTA at a capacitive load of 10 pF. Power dissipation is very low i.e. 716 nW at supply of 0.5 V. So as to facilitate maximum swing at 0.5 V supply and lower the power consumption, MOS transistors are biased in weak/moderate inversion. The OTA is designed in standard 45 nm CMOS process. Phase margin of is more than \(55^{\circ }\) for a typical load of 10 pF. The input referred noise is \(150\,\upmu {\text{V}}{/}\sqrt{{\text{Hz}}}\) at 10 Hz and slew rate \(0.02\,{\text{V}}{/}\upmu{\text{s}}\) for 10 pF load.     

A High Gain and Low Flicker Noise CMOS Mixer with Low Flicker Noise Corner Frequency Using Tunable Differential Active Inductor

This paper presents the design of a high conversion gain and low flicker noise down conversion CMOS double balanced Gilbert cell mixer using \(0.18\,\upmu \hbox {m}\) CMOS technology. The high conversion gain and low flicker noise mixer is implemented by using a differential active inductor (DAI) circuit and cross-coupled current injection technique within the conventional double-balanced Gilbert cell mixer. A cross-coupled current bleeding circuit is used to inject the current to the switching stage to decrease the flicker noise. Instead of spiral inductor, a DAI with high tunability of the inductor and quality factor is used to tune out the parasitic capacitance effect and decrease the leakage current that has a harmonic component and produce the flicker noise. By tuning the DAI, the flicker noise corner frequency is reduced to 150 Hz. The proposed circuit is simulated with Cadence Spectra and the simulation results shows the NF of 11.2 dB, conversion gain of 23.7 dB and IIP3 of \(-6\)  dB for an RF frequency of 2.4 GHz. The excellent LO-RF, LO-IF, RF-LO and RF-IF isolations of \(-60, -110, -52\) and \(-64\)  dB are achieved respectively. The total power consumption is 10.5 mW from a 1.8 V DC power supply.     

Electronically scanned RF-to-bits beam aperture arrays using 2-D IIR spatially bandpass digital filters

A beamforming system based on two-dimensional (2-D) spatially bandpass infinite impulse response (IIR) plane wave filtering is presented in a multi-dimensional signal processing perspective and the implementation details are discussed. Real-time implementation of such beamforming systems requires modeling of computational electromagnetics for the antennas, radio frequency (RF) analog design aspects for low-noise amplifiers (LNAs), mixed-signal aspects for signal quantization and sampling and finally, digital architectures for the spatially bandpass plane wave filters proposed in Joshi et al. (IEEE Trans Very Large Scale Integr Syst 20(12):2241–2254, 2012). Multi-dimensional spatio-temporal spectral properties of down-converted RF plane wave signals are reviewed and derivation of the spatially bandpass filter transfer function is presented. An example of a wideband antipodal Vivaldi antenna is simulated at 1 GHz. Potential RF receiver chains are identified including a design of a tunable combline microstrip bandpass filter with tuning range 0.8–1.1 GHz. The 1st-order sensitivity analysis of the beam filter 2-D $\mathbf z $ -domain transfer function shows that for a 12-bits of fixed-point precision, the maximum percentage error in the 2-D magnitude frequency response due to quantization is as low as $0.3\,\%$ . Monte-Carlo simulations are used to study the effect of quantization on the bit error rate (BER) performance of the beamforming system. 5-bit analog to digital converter (ADC) precision with 8-bit internal arithmetic precision provides a gain of approximately 16 dB for a BER of $10^{-3}$ with respect to the no beamforming case. ASIC Synthesis results of the beam filter in 45 nm CMOS verifies a real time operating frequency of 429 MHz.     

An Ultra-Low-Power Integrated RF Energy Harvesting System in 65-nm CMOS Process

In recent years, radio frequency (RF) energy harvesting systems have gained significant interest as inexhaustible replacements for traditional batteries in RF identification and wireless sensor network nodes. This paper presents an ultra-low-power integrated RF energy harvesting circuit in a SMIC 65-nm standard CMOS process. The presented circuit mainly consists of an impedance-matching network, a 10-stage rectifier with order-2 threshold compensation and an ultra-low-power power manager unit (PMU). The PMU consists of a voltage sensor, a voltage limiter and a capacitor-less low-dropout regulator. In the charge mode, the power consumption of the proposed energy harvesting circuit is only 97 nA, and the RF input power can be as low as \(-\)21.4 dBm \((7.24\,\upmu \hbox {W})\). In the burst mode, the device can supply a 1.0-V DC output voltage with a maximum 10-mA load current. The simulated results demonstrate that the modified RF rectifier can obtain a maximum efficiency of 12 % with a 915-MHz RF input. The circuit can operate over a temperature range from \(-40\hbox { to }125\,^{\circ }\hbox {C}\) which exceeds the achievable temperature performance of previous RF energy harvesters in standard CMOS process.     

A 470 μA direct readout circuit for electret and MEMS digital microphones

A direct readout circuit configurable for electret or MEMS digital microphones is presented. The circuit includes a transducer buffer, a programmable preamplifier, a ΣΔ modulator, a bandgap reference, a clock detection circuit, and a stability recovery system. The prototype achieves a signal-to-noise-and distortion of 63 dB A-weighted at 1 Pa sound level with a consumption of 470 μA at 1.8 V supply voltage. The active area is 0.72 mm² in a 0.25 μm CMOS process with MIM capacitor option.     

Ultra-Low Power Read-Decoupled SRAMs with Ultra-Low Write-Bitline Voltage Swing

We propose an ultra-low power memory design method based on the ultra-low ( \(\sim \) 0.2 V) write-bitline voltage swing to reduce the write power dissipation for read-decoupled SRAM (RD-SRAM) cells. By keeping the write bitlines at ground level (0 V) during standby and charging them to a low voltage \(V_\mathrm{L}\) ( \(\sim \) 0.2 V) during write operations, the power dissipation for the write bitlines is greatly reduced (0.2 V/ \(V_\mathrm{DD})^{ 2 }\,\times \) 100 %) due to reduced voltage swing (from \(V_\mathrm{DD }\)  = 1.2 to 0.2 V) on the write bitlines. The proposed method is applicable to both dual-voltage and single-voltage operations. We analyze the proposed ultra-low write-bitline voltage swing method and investigate its reliability based on 10K Monte-Carlo simulations. We further verify the functionality and performance of our proposed design through measurements on the fabricated prototypes based on the 65 nm CMOS process. By means of a \(256 \times 64\) bit RD-SRAM memory implementation, we show that our proposed method reduces 87 % write power dissipation when compared to a conventional design.     

A Low-Voltage Fully Differential Pure Current Mode Current Operational Amplifier

In this paper a novel high-frequency fully differential pure current mode current operational amplifier (COA) is proposed that is, to the authors’ knowledge, the first pure MOSFET Current Mode Logic (MCML) COA in the world, so far. Doing fully current mode signal processing and avoiding high impedance nodes in the signal path grant the proposed COA such outstanding properties as high current gain, broad bandwidth, and low voltage and low-power consumption. The principle operation of the block is discussed and its outstanding properties are verified by HSPICE simulations using TSMC \(0.18\,\upmu \hbox {m}\) CMOS technology parameters. Pre-layout and Post-layout both plus Monte Carlo simulations are performed under supply voltages of \(\pm 0.75\,\hbox {V}\) to investigate its robust performance at the presence of fabrication non-idealities. The pre-layout plus Monte Carlo results are as; 93 dB current gain, \(8.2\,\hbox {MHz}\,\, f_{-3\,\text {dB}}, 89^{\circ }\) phase margin, 137 dB CMRR, 13 \(\Omega \) input impedance, \(89\,\hbox {M}\Omega \) output impedance and 1.37 mW consumed power. Also post-layout plus Monte Carlo simulation results (that are generally believed to be as reliable and practical as are measuring ones) are extracted that favorably show(in abovementioned order of pre-layout) 88 dB current gain, \(6.9\,\hbox {MHz} f_{-3\text {db}} , 131^{\circ }\) phase margin and 96 dB CMRR, \(22\,\Omega \) input impedance, \(33\,\hbox {M}\Omega \) output impedance and only 1.43 mW consumed power. These results altogether prove both excellent quality and well resistance of the proposed COA against technology and fabrication non-idealities.     

E-TCAM: An Efficient SRAM-Based Architecture for TCAM

Ternary content addressable memories (TCAMs) perform high-speed search operation in a deterministic time. However, when compared with static random access memories (SRAMs), TCAMs suffer from certain limitations such as low-storage density, relatively slow access time, low scalability, complex circuitry, and higher cost. One fundamental question is that can we utilize SRAM to combine it with additional logic to achieve the TCAM functionality? This paper proposes an efficient memory architecture, called E-TCAM, which emulates the TCAM functionality with SRAM. E-TCAM logically divides the classical TCAM table along columns and rows into hybrid TCAM subtables and then maps them to their corresponding memory blocks. During search operation, the memory blocks are accessed by their corresponding subwords of the input word and a match address is produced. An example design of \(512\times 36\) of E-TCAM has been successfully implemented on Xilinx Virtex- \(5\) , Virtex- \(6\) , and Virtex- \(7\) field-programmable gate arrays (FPGAs). FPGA implementation results show that E-TCAM obtains \(33.33\)  % reduction in block-RAMs, \(71.07\)  % in slice registers, \(77.16\)  % in lookup tables, \(53.54\)  % in energy/bit/search, and offers \(63.03\)  % improvement in speed, compared with the best available SRAM-based TCAM designs.     

A remotely-powered, 20 Mb/s, 5.35 pJ/bit impulse-UWB WSN tag for cm-accurate-localization sensor networks

This paper presents an ultra-low-power, low-voltage sensor node for wireless sensor networks. The node scavenges RF energy out of the environment, resulting in a limited available power budget and causing an unstable supply voltage. Hence, accurate and extensive power management is needed to achieve proper functionality. The fully integrated, autonomous system is described, including the scavenging circuitry with integrated antenna, the power detection and power control circuits, the on-chip clock reference, the UWB transmitter and the digital control circuitry. The wireless sensor node is implemented in \(0.13 \,\upmu \hbox {m}\) CMOS technology. The only external components are a storage capacitor and a UWB transmit antenna. The system consumes only \(113\, \upmu \hbox {W}\) during burst mode, while only 8 nW is consumed during the scavenging operation, enabling an efficiency of 5.35 pJ/bit which is significantly better than current state-of-the-art UWB tags. Due to the use of impulse-radio UWB, also cm-accurate localization of the tag can be achieved.     

9.9 V ASK Demodulator Using Differential Shaper for High-Impedance Electrode

This paper proposes a 9.9 V ASK demodulator for the high-impedance micro-stimulating electrode. In order to receive the 9.9 V ASK modulated signal, a cascoded HV rectifier is utilized to rectify the HV (high voltage) ASK modulated signal and generates a miniature rectified signal with voltage \(<\) 3.3 V, such that the reliability problem can be avoided. Besides, a differential generator and a differential shaper are employed to amplify the miniature rectified signal. The theoretical analysis and the condition are given to guarantee the proposed ASK demodulator functionally working in all process and temperature corners. Besides, the aspect ratios of the MOS transistors can be easily found according to the analysis results. The simulation and measurement results are also given to verify the analysis results. Thus, the HV modulated signal could be demodulated easily without any off-chip step-down circuit, boost circuit and HV process required. The proposed design is carried out using TSMC 0.35  \(\upmu \) m CMOS process. The core area is \(109.515 \times 56.925\,\upmu {\text {m}}^2\) . The maximum data rate is measured to be 1.25 Mbps with the carrier frequency of 12.5 MHz.     

A 97 dB 400 MHz rail to rail fully differential opamp based on split length FGMOS-MOS cell

Recently introduced MOS-FGMOS split length cell has been used to increase the DC gain of a fully differential op amp. Resultant proposed opamp structure exhibits gain of 97 dB and unity gain bandwidth of 400 MHz with power consumption of 1.2 mW. An opamp design has been verified with Cadence Spectre using a 130 nm technology at 1.2 V and has a slew rate of \(53\,\hbox {V}/\mu \hbox {s}\) with a phase margin of \(78^{\circ }\) .     

A Wide Tuning Range Voltage Controlled Oscillator with a High Tunable Active Inductor

This paper presents a wide tuning range CMOS voltage controlled oscillator (VCO) with a high-tunable active inductor circuit. In this VCO circuit, the coarse frequency is achieved by tuning the integrated active inductor circuit. The VCO circuit is designed in 0.18  \(\upmu \hbox {m}\) CMOS process and simulated with Cadence Spectra. The simulation results show the frequency tuning range from 120 MHz to 2 GHz resulting in a tuning range of 94 %. The phase noise variation is from \(-\) 80 to \(-\) 90 dBc/Hz at a 1 MHz frequency offset, and output power variation is from \(-\) 4.7 to \(+\) 11.5 dBm. The active inductor power consumption is 2.2 mW and the total power dissipation is 7 mW from a 1.8 V DC power supply. By comparing the proposed VCO circuit with the general VCO topology, the results show that this VCO architecture by using the novel, high-tunable and low power active inductor circuit, presents a better performance regarding low chip size, low power consumption, high tuning range and high output power.     

A 5 GHZ CMOS Power VCO with Novel Frequency-Modulation for RF Transmitter

A 5 GHz transformer-feedback power oscillator with novel frequency modulation (FM) up to 10 MHz is presented in this paper. The novel FM is achieved by a CMOS transistor between transformer and ground, which is designed for varying the equivalent inductance and mutual inductance of the transformer and shows no DC connection with the oscillation circuit. The major frequency tuning is realized by the variable capacitor which is controlled by a phase lock loop. The RF VCO with 210 MHz tuning range operates in class-E mode to achieve a cost-effective transmitter, which demonstrates a high DC-to-RF conversion efficiency of 39 %. A RF power of 15.1 dBm and phase noise better than \(-\) 109 dBc/Hz @ 100 kHz from the central frequency of 5.5 GHz is obtained with the biasing conditions V \(_\mathrm{ds}\) = 1.8 V and V \(_\mathrm{gs}\) = 0.65 V. The VCO also demonstrates an ultra-low voltage operation capability: with V \(_\mathrm{ds}\) = V \(_\mathrm{gs}\) = 0.6 V and DC power consumption of 9 mW, the output power is 4.5 dBm and the phase noise better than \(-\) 93 dBc/Hz @ 100 kHz. The die size of the transformer-feedback power oscillator is only \(0.4\times 0.6\) mm \(^{2}\) .     

A Low-Voltage and Low-Power 3-GHz CMOS LC VCO for S-Band Wireless Applications

A fully integrated 0.18- \(\upmu \hbox {m}\) CMOS LC-tank voltage-controlled oscillator (VCO) suitable for low-voltage and low-power S-band wireless applications is proposed in this paper. In order to meet the requirement of low voltage applications, a differential configuration with two cross-coupled pairs by adopting admittance-transforming technique is employed. By using forward-body-biased metal oxide semiconductor field effect transistors, the proposed VCO can operate at 0.4 V supply voltage. Despite the low power supply near threshold voltage, the VCO achieves wide tuning range by using a voltage-boosting circuit and the standard mode PMOS varactors in the proposed oscillator architecture. The simulation results show that the proposed VCO achieves phase noise of \(-\) 120.1 dBc/Hz at 1 MHz offset and 39.3 % tuning range while consuming only \(594~\upmu \hbox {W}\) in 0.4 V supply. Figure-of-merit with tuning range of the proposed VCO is \(-\) 192.1 dB at 3 GHz.     

A low-power 2nd-order CT delta-sigma modulator with a single operational amplifier

We present a 2nd-order 4-bit continuous-time (CT) delta-sigma modulator (DSM) employing a 2nd-order loop filter with a single operational amplifier. This choice strongly reduces the power consumption, since operational amplifiers are the most power hungry blocks in the DSM. The DSM has been implemented in a 65 nm CMOS process, where it occupies an area of \(0.08\,\hbox {mm}^2\) . It achieves an SNDR of 64 dB over a 500 kHz signal bandwidth with an oversampling ratio of 16. The power consumption is \(76\,\upmu \hbox {W}\) from a 800 mV power supply. The DSM figure-of-merit is 59 fJ/conversion. The CT DSM is well suited for the receiver of an ultra-low-power radio.     

A Novel Design of Low Power Rectenna for Wireless Sensor and RFID Applications

In this paper, an efficient microstrip rectenna operating on ISM band with high harmonic rejection is presented. By using rotated E-shaped strip in the radiating patch, a new resonance at lower frequencies (2.4 GHz) can be achieved. Also by embedding cutting a rectangular slot with protruded interdigital strip inside the slot in the feed line a frequency band-stop performance can be achieved. The proposed structure has a major advantage in high harmonic rejection. The rectenna with integrated monopole antenna can eliminate the need for an low pass filter placed between the antenna and the diode as well as produce higher output power, with maximum conversion efficiency of 74 % using a 1 K \(\Omega \) load resistor at a power density of \(0.3\,\hbox {mW/cm}^{2}\) .