On Hamming Product Codes With Type-II Hybrid ARQ for On-Chip Interconnects

We present hardware performance analyses of Hamming product codes combined with type-II hybrid automatic repeat request (HARQ), for on-chip interconnects. Input flit width and the number of rows in the product code message are investigated for their impact on the number of wires in the link, codec delay, reliability, and energy consumption. Analytical models are presented to estimate codec delay and residual flit error rate. The analyses are validated by comparison with simulation results. In a case study using H.264 video encoder in a network-on-chip environment, the method of combining Hamming product codes with type-II HARQ achieves several orders of magnitude improvement in residual flit error rate. For a given residual flit error rate requirement (e.g., 10^-20), this method yields up to 50% energy improvement over other error control methods in high-noise conditions.     

An on-chip ECC circuit for correcting soft errors in DRAMs withtrench capacitors

A modified error-correcting code that can correct up to two soft errors on each row (word line) in a dynamic random-access memory (DRAM) chip is proposed. Double-bit soft errors frequently occur in DRAM cells with trench capacitors, when charged alpha particles impinge on the intervening space between two vertical capacitors causing plasma shorts between them. The conventional on-chip error-correcting codes (ECCs) cannot correct such double-bit word-line soft errors, which significantly increase the uncorrectable error rate (UER). An ECC circuit that uses an augmented rectangular product code to detect and correct double-bit soft errors is presented. The proposed circuit automatically corrects the addressed bit if it is faulty, and then quickly locates the other faulty bit. A comprehensive study is made to estimate improvements in soft error rate (SER) and mean time to failure (MTTF). The ability of the circuit to correct soft errors in the presence of multiple-bit errors has also been analyzed by combinatorial enumeration     

A Simple BCH Decoder for NoC Interconnects and SoC Buses

Network on a chip (NoC) uses packet-switched network to implement interconnections in System on chip (SoC). In SoC design, performance and energy efficiency are respectively the first and second priorities, and optimal on-chip communication should decrease the power consumption and area overhead. In this work, a simplified BCH codec is proposed for reliable communication in NoC and SoC. It performs BCH error corrections without Berlekamp's algorithm, only using reduced syndrome bits to determine error patterns. The error locations can be found by looking up tables, by which the possible errors are directly corrected. Only one matrix product and one ROM access are required in the BCH decoder. The proposed (20, 8, 2) and (31, 16, 3) decoders in the paper can be easily applied for error corrections of interconnects and buses for NoC and SoC. It is also beneficial to correct data lines without length definition and controllines without storage.     

Système de protection contre les erreurs pour la liaison ionosphérique

This paper presents an error correcting system designed for a 1 200 bit/s self adaptative modem operating on the HF channel. An analysis of error statistics has been made simulating a specific link whose characteristics had been measured beforehand by a HF backscattering probe. The coding system which has been chosen consists of a cascade of two cyclic codes. One corrects long bursts of errors (Kasami code), the other corrects single errors and small bursts (Reed Solomon code). Both codes are interleaved. The overall rate is 50 %. An error correction simulation has shown that in most of the cases studied, with a ber of 10^?4 a coding gain of at least 10^?2 has been achieved.     

Error correction performance in digital subscriber looptransmission systems

The author describes an error correction system for digital subscriber loop transmission systems which use time compression multiplexing (TCM). An interleaved block code is used to correct the burst errors due to impulse noise from analog telephone circuits. This interleaving method requires no extra hardware and contributes no additional delay. To evaluate the transmission performance of this error correction system, the bit error rate after decoding is derived on the basis of a burst error model for 200 kb/s digital subscriber transmission using the alternate mark inversion (AMI) line code. The experimental results for a 200 kb/s TCM system show that burst errors are substantially reduced     

Transition Skew Coding for Global On-Chip Interconnect

This paper presents new simulation results of the previously proposed transition skew coding (TSC) for global on-chip interconnects. Considering 2-GHz global clock frequency at the 90-nm node, we show that TSC can be applied to broad range of wire length on both semiglobal and global metal layers, while maintaining its energy efficiency and its advantages in terms of crosstalk reduction and signal integrity, and wiring and repeater area minimization.     

RS（16,12）缩短码编译码原理及性能分析

在各类数字通信系统以及计算机存储和运算系统经常利用差错控制编码降低误码率,提高通信质量,满足对数据传输通道可靠性的要求。RS码是一种性能优良的前向纠错码,具有同时纠正随机错误和突发错误的能力,它的构造特点决定了其非常适合于纠正突发性错误。文中在阐述RS系统码编译码原理的基础上,提出了RS（16,12）缩短码的编译码方法,利用MATLAB对R S（16,12）缩短码在高斯信道和瑞利信道条件下的纠错能力进行仿真,并分析其纠错性能。     

Energy Efficient Coded Communication for IEEE 802.15.4 Compliant Wireless Sensor Networks

The multipath nature of the wireless environment does not provide reliable links for robust communication in wireless senor networks (WSNs). These unreliable links increase the error level to a greater extent and therefore, reduces battery life. Hence, there arises a need for developing energy efficient forward error correction code that avoids more energy consuming Automatic Repeat request (ARQ) scheme used in WSNs to improve link reliability. In this paper, we consider a simple block error correction codes such as cyclic and Bose Chaudhuri Hocquenghem (BCH) codes to be used in IEEE 802.15.4 RF transceiver based sensor nodes. The simulations are performed to measure network parameters such as bit error rate, and energy spent per bit under Rayleigh fading channel environment. It is found that BCH code with code rate of 0.8 provides coding gain of 1.6 dB when compared with cyclic and ARQ schemes and proves to be an energy efficient code among the codes considered.     

纠正随机错误与长突发删除的多进制乘积码研究

考虑多进制LDPC码的符号特性，以及对其残留错误和删除的分析，本文采用多进制LDPC码作为内码，相同Galois域下的高码率RS码作为外码来构造多进制乘积码；并提出了一种低复杂度的迭代译码方案，减少信息传输的各类错误。在译码时，只对前一次迭代中译码失败的码字执行译码，并对译码正确码字所对应的比特初始概率信息进行修正，增强下一次迭代多进制LDPC译码符号先验信息的准确性，减少内码译码后的判决错误，从而充分利用外码的纠错能力。仿真结果显示，多进制乘积码相较于二进制LDPC乘积码有较大的编码增益，并通过迭代进一步改善了性能，高效纠正了信道中的随机错误和突发删除。对于包含2%突发删除的高斯信道，在误比特率为10-6时，迭代一次有0.4 dB左右的增益。      

Subband-multipulse digital audio broadcasting for mobile receivers

The audio quality, robustness and implementational complexity of a novel mobile digital audio broadcast scheme are addressed. The audio codec proposed is based on an efficient combination of subband coding (SBC) and multipulse excited linear prediction coding (MPLPC). The bit allocation is dynamically adapted according to both the signal power in different subbands and a perceptual hearing model. Typically a segmental signal to noise ratio (SEGSNR) in excess of 30 dB associated with high fidelity subjective quality was achieved for 2.67-b/sample transmissions at a bit rate of 86 kb/s. Perceptually unimpaired audio quality was achieved for a bit error rate (BER) of about 10^-4, when injecting random errors, which was degraded for increased BERs. In order to provide robust error protection, the audio codec was also subjected to a rigorous bit sensitivity analysis. Four different forward error correction schemes were investigated in order to explore the complexity, bit rate, and robustness tradeoffs     

一种低功耗抗串扰的自适应时空总线编码方法

深亚微米片上总线的功耗、布线面积约束和线间串扰是限制总线数据吞吐率的关键因素,为此该文提出一种自适应时空编码方法以降低总线的串扰延迟和功耗。该方法首先采用空间编码将总线分割为两个子总线,从而减小了恶性串扰发生几率;然后通过恶性串扰判决器分别判断子总线的原码数据及反码数据是否存在恶性串扰:对于任意子总线的原码数据与反码数据均存在恶性串扰的情况,传送屏蔽字;否则,选取无恶性串扰且动态功耗小的总线数据形式并传送。采用SPEC标准数据源对算法进行了评估,该方法在消除恶性串扰的同时使总线数据吞吐率提高了62.59%~81.62%,功耗比同类方法降低14.63%~54.67%,对于32位数据总线,仅需7根冗余线,在动态功耗、布线资源和性能方面获得了有效的优化。     

An error-correcting system for mobile radio data transmission

An error-correcting system for mobile radio data transmission with improved reliability and simple implementation is presented here. The new rate one-half code absolutely corrects two errors within 12 consecutive bits, while the (15, 7, 2) Bose-Chaudhuri-Hocquenquem (BCH) code corrects two errors within 15 bits and Hagelbarger's code corrects two errors within 14 bits. Error propagation in the feedback majority logic decoder is discussed, and it is proved empirically that the new code does not propagate infinite errors. In order to correct burst errors, a 12-column interleaving is proposed for fading channels.     

Performance of Forward-Error Correction Code in 10-Gb/s RSOA-Based WDM PON

We investigate the performance of the forward-error correction (FEC) code for the 10-Gb/s wavelength-division- multiplexed passive optical network (WDM PON) implemented by using reflective semiconductor optical amplifiers (RSOAs) with extremely limited modulation bandwidth and the electronic equalizers to compensate for the degradations resulting from the use of such RSOAs. We show that the error occurrences in this network strongly depend on the bit pattern and the burst errors are likely to occur. Thus, it is important to use the FEC code capable of correcting the burst errors such as Reed–Solomon (RS) code. In addition, since a significant penalty can be induced by the increased line rate resulting from the use of the FEC code, it is necessary to find the optimum redundancy required to minimize the bit-error rate. We also evaluate the tolerance to the chromatic dispersion of the proposed 10-Gb/s WDM PON implemented by using the RS code with the optimum redundancy.      

基于置信度的S模式信号随机多位纠错技术

针对现有纠错技术只能对少量随机错误或突发错误进行纠错的不足,提出了一种基于置信度的随机多位纠错方法。该方法在准确进行置信度判断的基础上,通过缩短循环冗余校验（CRC）处理时间或增加并行运算能力以增加纠错位数。同时给出了可运用于工程实际的保守技术和强力技术的联合纠错处理流程。通过解码纠错实验,统计结果表明该置信度判定法则的准确性为98.24%,通过图形处理器（GPU）强力纠错可实现高达83.37%的解码率,通过现场可编程门阵列（FPGA）强力纠错可实现73.66%的解码率,较现有强力纠错技术的纠错能力有较大提高,可增强对航空器监视的连续性。     

一种基于补偿校正的网络编码和信道编码联合设计

将信道编译码中性能较优的LDPC码运用到网络编码和信道编码联合设计,提出一种接收端补偿校正的网络编码和信道编码联合设计方案,该方案在中继节点进行解调和译码后硬判决,以降低中继节点处理数据的复杂性,然后进行网络编码而不考虑编码数据中存在的误码,通过接收节点对中继硬判决信息的错误概率进行补偿和校正来获取最大似然接收。仿真实验表明,提出的网络编码和信道编码联合设计方案不但降低了中继节点处理数据的复杂性,同时提高了传输系统的可靠性。     

Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects

This paper presents a set of circuit techniques to achieve high data rate point-to-point communication over long on-chip RC-limited wire-pairs. The ideal line termination impedances for a flat transfer function with linear phase (pure delay) are derived, using an s-parameter wire-pair model. It is shown that a driver with series capacitance on the one hand and a resistive load on the other, are fair approximations of these ideal terminations in the frequency range of interest. From a perspective of power efficiency, a capacitive driver is preferred, as the series capacitance reduces the voltage swing along the line which reduces dynamic power consumption. To reduce cross-talk and maintain data integrity, parallel differential interconnects with alternatingly one or two twists are used. In combination with a low offset dynamic sense amplifier at the receiver, and a low-power decision feedback equalization technique with analog feedback, gigabit communication is demonstrated at very low power consumption. A point-to-point link on a 90 nm CMOS test chip achieves 2 Gb/s over 10 mm long interconnects, while consuming 0.28 pJ/bit corresponding to 28 fJ/bit/mm, which is much lower than competing designs.      

Performance of Hybrid Error Control Schemes of Satellite Channels

The effectiveness of hybrid error control schemes involving forward error correction (FEC) and automatic repeat request (ARQ) is examined for satellite channels. The principal features of the channel are: large round-trip transmission delay due to the satellite link, and burst errors introduced by the terrestrial links that connect the users to the satellite link. The performance is estimated for two channels described by Fritchman's simple partitioned finite-state Markov model, and is compared to that obtainable if the channel is considered as a binary symmetric channel of the same bit error probability. Results show that the hybrid schemes offer substantial improvement over ARQ and FEC, and that an optimum exists for the number of errors corrected to obtain maximum throughput efficiency.     

Analysis of video transmission over lossy channels

A theoretical analysis of the overall mean squared error (MSE) in hybrid video coding is presented for the case of error prone transmission. Our model covers the complete transmission system including the rate-distortion performance of the video encoder, forward error correction, interleaving, and the effect of error concealment and interframe error propagation at the video decoder. The channel model used is a 2-state Markov model describing burst errors on the symbol level. Reed-Solomon codes are used for forward error correction. Extensive simulation results using an H.263 video codec are provided for verification. Using the model, the optimal tradeoff between INTRA and INTER coding as well as the optimal channel code rate can be determined for given channel parameters by minimizing the expected MSE at the decoder. The main focus of this paper is to show the accuracy of the derived analytical model and its applicability to the analysis and optimization of an entire video transmission system     

HVD: horizontal-vertical-diagonal error detecting and correcting code to protect against with soft errors

This paper presents a high level error detection and correction method called HVD code to tolerate multiple bit upsets (MBUs) occurred in memory cells. The proposed method uses parity codes in four directions in a data part to assure the reliability of memories. The proposed method is very powerful in error detection while its error correction coverage is also acceptable considering its low computing latency. HVD code is useful for applications whose high error detection coverage is very important such as memory systems. Of course, this code can be used in combination with other protection codes which have high correction coverage and low detection coverage. The proposed method is evaluated using more than one billion multiple fault injection experiments. Multiple bit flips were randomly injected in different segments of a memory system and the fault detection and correction coverages are calculated. Results show that 100% of the injected faults can be detected. We proved that, this method can correct up to three bit upsets. Some hardware implementation issues are investigated to show tradeoffs between different implementation parameters of HVD method.     

Near-optimal, single-synchronization-error-correcting code

A synchronization error is said to occur when either a bit which does not belong is detected in a channel between bits which were transmitted, or a bit which was transmitted is never detected at the output. A block code which corrects a single synchronization error per block is presented, and it is shown that this code has, at most, three bits more redundancy than that of an optimal code for this class of errors. The code has the beneficial property that it is possible to separate the information positions from the check positions, and an appropriate method of encoding is shown.