A Novel 2.5–3.1 GHz Wide-Band Low-Noise Amplifier in 0.18 \upmu \hbox {m} CMOS

Aiming for the simultaneous realization of constant gain, accurate input and output impedance matching and minimum noise figure (NF) over a wide frequency range, the circuit topology and detailed design of wide broadband low noise amplifier (LNA) are presented in this paper. A novel 2.5–3.1 GHz wide-band LNA with unique characteristics has been presented. Its design and layout are done by TSMC 0.18  \(\upmu \hbox {m}\) technology. Common gate stage has been used to improve input matching. In order to enhance output matching and reduce the noise as well, a buffer stage is utilized. Mid-stages which tend to improve the gain and reverse isolation are exploited. The proposed LNA achieves a power gain of 15.9 dB, a NF of 3.5 dB with an input return loss less than \(-\) 11.6, output return loss of \(-\) 19.2 to \(-\) 19 and reverse isolation of \(-\) 38 dB. The LNA consumes 54.6 mW under a supply voltage of 2 V while having some acceptable characteristics.     

A 3.1–10.6 GHz UWB LNA Based on Self Cascode Technique for Improved Bandwidth and High Gain

In this work, we present a self cascode based ultra-wide band (UWB) low noise amplifier (LNA) with improved bandwidth and gain for 3.1–10.6 GHz wireless applications. The self cascode (SC) or split-length compensation technique is employed to improve the bandwidth and gain of the proposed LNA. The improvement in the bandwidth of SC based structure is around 1.22 GHz as compared to simple one. The significant enhancement in the characteristics of the introduced circuit is found without extra passive components. The SC based CS–CG structure in the proposed LNA uses the same DC current for operating first stage transistors. In the designed UWB LNA, a common source (CS) stage is used in the second stage to enhance the overall gain in the high frequency regime. With a standard 90 nm CMOS technology, the presented UWB LNA results in a gain \(\hbox {S}_{21}\) of \(20.10 \pm 1.65\,\hbox {dB}\) across the 3.1–10.6 GHz frequency range, and dissipating 11.52 mW power from a 1 V supply voltage. However, input reflection, \(\hbox {S}_{11}\), lies below \(-\,10\) dB from 4.9–9.1 GHz frequency. Moreover, the output reflection (\(\hbox {S}_{22}\)) and reverse isolation (\(\hbox {S}_{12}\)), is below \(-\,10\) and \(-\,48\) dB, respectively for the ultra-wide band region. Apart from this, the minimum noise figure (\(\hbox {NF}_{min}\)) value of the proposed UWB LNA exists in the range of 2.1–3 dB for 3.1–10.6 GHz frequency range with a a small variation of \(\pm \,0.45\,\hbox {dB}\) in its \(\hbox {NF}_{min}\) characteristics. Linearity of the designed LNA is analysed in terms of third order input intercept point (IIP3) whose value is \(-\,4.22\) dBm, when a two tone signal is applied at 6 GHz with a spacing of 10 MHz. The other important benefits of the proposed circuit are its group-delay variation and gain variation of \(\pm \,115\,\hbox {ps}\) and \(\pm \,1.65\,\hbox {dB}\), respectively.     

A High Gain and Low Flicker Noise CMOS Mixer with Low Flicker Noise Corner Frequency Using Tunable Differential Active Inductor

This paper presents the design of a high conversion gain and low flicker noise down conversion CMOS double balanced Gilbert cell mixer using \(0.18\,\upmu \hbox {m}\) CMOS technology. The high conversion gain and low flicker noise mixer is implemented by using a differential active inductor (DAI) circuit and cross-coupled current injection technique within the conventional double-balanced Gilbert cell mixer. A cross-coupled current bleeding circuit is used to inject the current to the switching stage to decrease the flicker noise. Instead of spiral inductor, a DAI with high tunability of the inductor and quality factor is used to tune out the parasitic capacitance effect and decrease the leakage current that has a harmonic component and produce the flicker noise. By tuning the DAI, the flicker noise corner frequency is reduced to 150 Hz. The proposed circuit is simulated with Cadence Spectra and the simulation results shows the NF of 11.2 dB, conversion gain of 23.7 dB and IIP3 of \(-6\)  dB for an RF frequency of 2.4 GHz. The excellent LO-RF, LO-IF, RF-LO and RF-IF isolations of \(-60, -110, -52\) and \(-64\)  dB are achieved respectively. The total power consumption is 10.5 mW from a 1.8 V DC power supply.     

A 11.2 mW 48–62 GHz Low Noise Amplifier in 65 nm CMOS Technology

In this paper, a wideband low noise amplifier (LNA) for 60 GHz wireless applications is presented. A single-ended two-stage cascade topology is utilized to realize an ultra-wideband and flat gain response. The first stage adopts a current-reused topology that performs the more than 10 GHz ultra-wideband input impedance matching. The second stage is a cascade common source amplifier that is used to enhance the overall gain and reverse isolation. By proper optimization of the current-reused topology and stagger turning technique, the two-stage cascade common source LNA provides low power consumption and gain flatness over an ultra-wide frequency band with relatively low noise. The LNA is fabricated in Global Foundries 65 nm RFCMOS technology. The measurement results show a maximum \(S_{21}\) gain of 11.4 dB gain with a \(-\)3 dB bandwidth from 48 to 62 GHz. Within this frequency range, the measured \(S_{11}\) and \(S_{12}\) are less than \(-\)10 dB and the measured DC power consumption is only 11.2 mW from a single 1.5 V supply.     

A 0.1–1.1 GHz inductorless differential LNA with double <Emphasis Type="Italic">g</Emphasis><Subscript><Emphasis Type="Italic">m</Emphasis></Subscript>-boosting and positive feedback

A 0.1–1.1 GHz wideband low-noise amplifier (LNA) is proposed in this paper. The LNA is a fully differential common-gate structure. Large equivalent transconductance \((g_m)\) is realized by active \(g_m\)-boost and capacitive cross-coupling. By introducing a positive feedback path, the circuit increases design freedom. It alleviates the tradeoff between input matching, gain and noise performance. The proposed LNA avoids the use of on-chip inductors to save area and cost. A prototype is implemented in standard TSMC 180-nm CMOS technology. From the measurement, the proposed LNA shows a 19 dB voltage gain with a 1 GHz 3-dB bandwidth. The minimum noise figure (NF) is 3.1 dB. The LNA achieves a return loss greater than 10 dB across the entire band and the third-order input-referred intercept (IIP3) is better than \(-\,2.9\) dBm. The core consumes 3.8 mW from 1-V supply occupying an area of 0.03 \(\hbox {mm}^2\).     

A multi-band low noise amplifier with strong immunity to interferers

A multi-band low noise amplifier (LNA) is designed to operate over a wide range of frequencies (with center frequencies at 1.2, 1.7 and 2.2 GHz respectively) using an area efficient switchable \(\pi\) network. The LNA can be tuned to different gain and linearity combinations for different band settings. Depending upon the location of the interferers, a specific band can be selected to provide optimum gain and the best signal-to-intermodulation ratio. This is accomplished by the use of an on-chip built-in-self-test circuit. The maximum power gain of the amplifier is 19 dB with a return loss better than 10 dB for 7 mW of power consumption. The noise figure is 3.2 dB at 1 GHz and its third-order intercept point (\(IIP_3\)) ranges from ?15 to 0 dBm. Implemented in a 0.13 \(\upmu\)m CMOS technology, the LNA occupies an active area of about 0.29 mm\(^2\). This design can be used for cognitive radio and other wideband applications, which require a dynamic configuration of the signal-to-intermodulation ratio, when sufficient information about the power and the location of the interferers is not available.     

A High Gain,Low-Power Low-Noise Amplifier for Ultra-Wideband Wireless Systems

This paper presents a high gain, low-power common-gate ultra-wideband low-noise amplifier employing a simple configuration for wideband input matching. In our design, a series resistance-inductance network at the source combines with the parasitic capacitance of a transistor to form a parallel RLC input matching configuration in the common-gate input stage. Because of the additional resistance, this matching configuration partially alleviates the restriction of transconductance of the input transistor and also provides wideband matching. The low-noise amplifier was fabricated using the TSMC 0.18  \(\mu \) m technology with an average noise figure of 3.75 dB, a power gain of 18.68 dB with a ripple of \(\pm \)  0.8 dB, an input return loss less than \(-10\)  dB from 3 to 7.6 GHz, and DC power consumption of 8.56 mW, including the output buffer with a 1.8 V supply voltage.     

A 97 dB 400 MHz rail to rail fully differential opamp based on split length FGMOS-MOS cell

Recently introduced MOS-FGMOS split length cell has been used to increase the DC gain of a fully differential op amp. Resultant proposed opamp structure exhibits gain of 97 dB and unity gain bandwidth of 400 MHz with power consumption of 1.2 mW. An opamp design has been verified with Cadence Spectre using a 130 nm technology at 1.2 V and has a slew rate of \(53\,\hbox {V}/\mu \hbox {s}\) with a phase margin of \(78^{\circ }\) .     

A 0.8V 40 Gb/s Novel CMOS Regulated Cascode Trans-impedance Amplifier for Optical Sensing Applications

This paper describes a 0.8 V 700 μW CMOS low-voltage regulated cascode trans-impedance amplifier (TIA). It reduces the need for extra bias voltages compared to other recent low-voltage regulated cascode topologies. A trans-impedance gain of around 60 dBΩ along with a 40 GHz bandwidth was achieved using the 0.13 μm IBM CMOS process technology. The input referred noise current spectral density was below $ {{{18{\mathrm{pA}}}} \left/ {{\sqrt {\mathrm{Hz}} }} \right.} $ within the -3 dB noise bandwidth. Eye diagram simulations using a ?53dBm input photo-diode current signal and a 2³¹-1 pseudo random bit sequence data pattern, indicates an eye opening of 90 % at 10Gbit/s and 50 % at 40Gbit/s. This proposed RGC TIA is thus a robust building block for numerous optical sensing applications with low bit error ratio (BER) figure.     

A 3–10 GHz Ultra Wideband Receiver LNA in 0.13 \mu m CMOS

A fully integrated low-power, low-complexity ultra wideband (UWB) 3–10 GHz receiver front-end in standard 130 nm CMOS technology is proposed for UWB radar sensing applications. The receiver front-end consists of a full UWB band low-noise amplifier and an on-chip diplexer. The on-chip diplexer has a 1 dB insertion loss and provides a \(-\) 30 dB isolation. The diplexer switch was co-designed with the receiver input matching network to optimize the power matching while simultaneously achieving good noise matching performance. The receiver low-noise amplifier provides a 3–10 GHz bandwidth input matching and a power gain of 17 dB. The overall receiver front-end consumes an average power of 13 mW. The core area of the transceiver circuit is 500 \(\mu \) m by 700 \(\mu \) m.     

Triple cascaded current-reuse low noise amplifier

A triple cascaded current-reuse CMOS low noise amplifier for 3.5 GHz WiMAX application is presented. Three common-source amplifiers are stacked and reuse the same current. This triple cascaded topology is able to enhance power gain but needs two coupling networks which costs enormous chip size. In order to have reasonable chip size, two coupling methods are investigated. For obtaining simultaneous input and noise matching, an additional capacitor is employed to adjust quality factor and reduce the gate induced current noise. The measurement results show a maximum power gain of 21.7 dB and minimum noise figure of 3.11 dB. The chip size is 1.05 mm \(\times\) 0.93 mm including all pads and the power consumption is 5.16 mW with a supply voltage of 1.5 V. A figure-of-merit of 49.7 is reached.     

High-temperature characterisation and analysis of leakage-current-compensated,low-power bandgap temperature sensors

This paper presents a low-power, high-performance current-feedback instrumentation amplifier (CFIA) for portable bio-potential sensing applications. Noise analysis is performed to assign an optimized current for the input stage of the amplifier. Analysis on selecting nested chopping frequencies is performed, further reducing 1/f noise and the residual offset. Enhanced power efficiency is achieved by sharing cascode branches and using a Class-AB output stage. Through these methods, a good balance between noise performance and other parameters such as output ripples and power consumption of the ripple reduction feedback loop (RRFL) is achieved. The amplifier is developed using a 1-poly 6-metal 0.18 μm CMOS process. Three gain stages with a gain-boosting input stage provide a low-frequency, open-loop gain >250 dB. When configured to a closed-loop gain of 60 dB, the amplifier achieves a noise voltage density of 18 \({\text{nV}}/\sqrt {{\text{H}}z}\) and a 1/f noise corner of 3 Hz. With a current of 75 μA and a supply voltage of 3.3 V, a CMRR of 110 dB and a PSRR of 120 dB are achieved, with an average input offset of about 6.5 μV. The amplifier achieves a state-of-art noise efficiency factor of 4.2. Practical application of the CFIA is demonstrated with an in vivo electrocardiogram detection.     

A Wide Tuning Range Voltage Controlled Oscillator with a High Tunable Active Inductor

This paper presents a wide tuning range CMOS voltage controlled oscillator (VCO) with a high-tunable active inductor circuit. In this VCO circuit, the coarse frequency is achieved by tuning the integrated active inductor circuit. The VCO circuit is designed in 0.18  \(\upmu \hbox {m}\) CMOS process and simulated with Cadence Spectra. The simulation results show the frequency tuning range from 120 MHz to 2 GHz resulting in a tuning range of 94 %. The phase noise variation is from \(-\) 80 to \(-\) 90 dBc/Hz at a 1 MHz frequency offset, and output power variation is from \(-\) 4.7 to \(+\) 11.5 dBm. The active inductor power consumption is 2.2 mW and the total power dissipation is 7 mW from a 1.8 V DC power supply. By comparing the proposed VCO circuit with the general VCO topology, the results show that this VCO architecture by using the novel, high-tunable and low power active inductor circuit, presents a better performance regarding low chip size, low power consumption, high tuning range and high output power.     

Six Order Cascaded Power Line Notch Filter for ECG Detection Systems with Noise Shaping

This paper presents the design of an operational transconductance amplifier-C (OTA-C) notch filter for a portable Electrocardiogram (ECG) detection system. A six order cascaded filter is utilized to reduce the effect of the power line interference at (50/60 Hz). The proposed filter is based on a programmable balanced OTA circuit. Based on this, PSPICE post layout simulation results for the extracted filter using 0.25  \(\upmu \) m technology and operating under \(\pm \) 0.8 V voltage supply are also given. The six order notch filter provides a notch depth of 65 dB (43 dB for 4th order), input referred noise spectral density with noise shaping of 9  \(\upmu \) Vrms/ \(\surd \) Hz at the pass band frequencies and 9 mVrms/ \(\surd \) Hz at the notch (zero) frequency which provide noise shaping for the ECG signal. These results demonstrate the ability of the filter to be used for ECG signal filtering which is located within 150 Hz.     

A broadband, differential transimpedance amplifier in 0.35 μm SiGe BICMOS technology for 10 Gbit/s fiber optical front-ends

This study focuses on 10 Gbit/s differential transimpedance amplifier. At the beginning of the work, the amplifier circuit is deeply analyzed and is optimized for the best phase linearity over the bandwidth resulted in a group delay variation less than 1 ps. The amplifier circuit is designed with 0.35 μm SiGe heterojunction bipolar transistor BICMOS process. 9 GHz bandwidth, almost 58 dBΩ transimpedance gain with less than 11.18 pA/ $ \sqrt {\text{Hz}} $ averaged input-referred noise current are achieved. Electrical sensitivity is 15 μA_pp. Power consumption is 71 mW at 3.3 V single power supply.     

Linearity improvement of cascode low-noise amplifiers using double DS method with a tuned inductor

We propose a highly linear low-noise amplifier (LNA) using the double derivative superposition method with a tuned inductor. This topology has an auxiliary common gate stage of the cascode amplifier to cancel each third-order intermodulation distortion (IMD3) component and can provide a high third-order input intercept point (IIP3) for the 5.25 GHz frequency band. From the simulation results using the TSMC 0.18 μm RF CMOS process, the IIP3 in the proposed cascode LNAs can be improved by 9 dB, compared with the conventional derivative superposition method. The proposed LNA achieves an IIP3 of + 15 dBm with a gain of 10.5 dB, a noise figure of 2.4 dB, and a power consumption of 6 mA at 1.5 V.     

A 1 GS/s, 31 MHz BW, 76.3 dB dynamic range, 34 mW CT-\Updelta\Upsigma ADC with 1.5 cycle quantizer delay and improved STF

A 1 GS/s continuous-time delta-sigma modulator (CT- $\Updelta\Upsigma$ M) with 31 MHz bandwidth, 76.3 dB dynamic range and 72.5 dB peak-SNDR is reported in a 0.13 μm CMOS technology. The design employs an excess loop delay (ELD) of more than one clock cycle for achieving higher sampling rate. The ELD is compensated using a fast-loop formed around the last integrator by using a sample-and-hold. Further, the effect of this ELD compensation scheme on the signal transfer function (STF) of a feedforward CT- $\Updelta\Upsigma$ architecture has been analyzed and reported. In this work, an improved STF is achieved by using a combination of feed-forward, feed-back and feed-in paths and power consumption is reduced by eliminating the adder opamp. This CT- $\Updelta\Upsigma$ M has a conversion bandwidth of 31 MHz and consumes 34 mW from the 1.2 V power supply. The relevant design trade-offs have been investigated and presented along with simulation results.     

Inductor-less PVT robust gain switching balun LNA for multistandard applications

An inductor-less single to differential low-noise amplifier (LNA) is proposed for multistandard applications in the frequency band of 0.2–2 GHz. The proposed LNA incorporates noise cancellation and voltage shunt feedback configuration to achieve minimum noise characteristics and low power consumption. In addition to noise cancellation, trans-conductance of common-source stage is scaled to improve the noise performance. In this way, noise figure (NF) of LNA below 3 dB is achieved. An additional capacitor C_c is used to correct the gain and phase imbalance at the output. The gain switching has been enabled with a step size of 4 dB for high linearity and power efficiency. The bias point of all transistors is chosen such that the variation in g_m is not more than 10%. The proposed LNA is implemented in UMC 0.18-μm RF CMOS technology. The core area is 182 μm × 181 μm. Moreover, the LNA has better ratio of relevant performance to area. The proposed balun LNA is validated by rigorous Monte Carlo simulation. The 3σ deviation of gain and NF is less than 5%. Finally, the proposed LNA is robust to unavoidable PVT variations.     

A Low-Voltage and Low-Power 3-GHz CMOS LC VCO for S-Band Wireless Applications

A fully integrated 0.18- \(\upmu \hbox {m}\) CMOS LC-tank voltage-controlled oscillator (VCO) suitable for low-voltage and low-power S-band wireless applications is proposed in this paper. In order to meet the requirement of low voltage applications, a differential configuration with two cross-coupled pairs by adopting admittance-transforming technique is employed. By using forward-body-biased metal oxide semiconductor field effect transistors, the proposed VCO can operate at 0.4 V supply voltage. Despite the low power supply near threshold voltage, the VCO achieves wide tuning range by using a voltage-boosting circuit and the standard mode PMOS varactors in the proposed oscillator architecture. The simulation results show that the proposed VCO achieves phase noise of \(-\) 120.1 dBc/Hz at 1 MHz offset and 39.3 % tuning range while consuming only \(594~\upmu \hbox {W}\) in 0.4 V supply. Figure-of-merit with tuning range of the proposed VCO is \(-\) 192.1 dB at 3 GHz.     

Design of a capacitor cross-coupled dual-band LNA with switched current-reuse technique

This paper presents the design of a 2.5/3.5-GHz dual-band low-power and low-noise CMOS amplifier (LNA), which uses the capacitor cross-coupling technique and current-reuse method with four switches. The proposed LNA uses a single RF block and a broadband input stage, which is a key aspect for the easy reconfiguration of a dual-band LNA. Switching at the inter-stage and output allows for the selection of a different standard. The dual-band LNA attenuates the undesired interference of a broadband gain response circuit, which allows the linearity of the amplifier to be improved. The capacitor cross-coupled gm-boosting method improves the NF and reduces the current consumption. The proposed LNA employs a current-reused structure to decrease the total power consumption. The inter-stage and output switched resonators switch the LNA between the 2.5-GHz and 3.5-GHz bands. The proposed dual-band LNA optimises power consumption by the securing gain, noise figure and linearity. The simulated performance reveals gains of 16.7 dB and 19.6 dB, and noise figures of 3.04 dB and 2.63 dB at the two frequency bands, respectively. The linearity parameters of IIP3 are ?5.7 dBm at 2.5 GHz and ?9.7 dBm at 3.5 GHz. The proposed dual-band LNA consumes 5.6 mW from a 1.8 V power supply.