基于IEEE Std1500标准的互连检测构架设计

摘要：随着电路系统向着高密度、高速度的方向发展,引发了严重的信号完整性问题。针对串扰故障,MT故障检测模型具有较好的故障覆盖率,但也存在含有大量矢量冗余的问题。通过对传统MT故障模型的精简,提出了一种新的串扰故障检测模型—改进型MT模型。模型对种子进行筛选及施加,测试矢量有规律跳变,产生了全部的测试矢量。通过对基于IEEE Std 1500标准的IP核测试壳各部分进行设计,特别是对测试环单元进行设计,实现了改进型MT模型故障检测。设计的IP核测试壳能够对IP核与核间互连线进行串行测试和并行测试。通过quartus ii平台仿真及数据计算,验证了该测试构架的有效性和故障检测的高效性。     

Multiple-Constraint Driven System-on-Chip Test Time Optimization

The cost of testing SOCs (systems-on-chip) is highly related to the test application time. The problem is that the test application time increases as the technology makes it possible to design highly complex chips. These complex chips include a high number of fault sites, which need a high test data volume for testing, and the high test data volume leads to long test application times. For modular core-based SOCs where each module has its distinct tests, concurrent application of the tests can reduce the test application time dramatically, as compared to sequential application. However, when concurrent testing is used, resource conflicts and constraints must be considered. In this paper, we propose a test scheduling technique with the objective to minimize the test application time while considering multiple conflicts. The conflicts we are considering are due to cross-core testing (testing of interconnections between cores), module testing with multiple test sets, hierarchical conflicts in SOCs where cores are embedded in cores, the sharing of the TAM (test access mechanism), test power limitations, and precedence conflicts where the order in which tests are applied is important. These conflicts must be considered in order to design a test schedule that can be used in practice. In particular, the limitation on the test power consumption is important to consider since exceeding the system's power limit might damage the system. We have implemented a technique to integrate the wrapper design algorithm with the test scheduling algorithm, while taking into account all the above constraints. Extensive experiments on the ITC'02 benchmarks show that even though we consider a high number of constraints, our technique produces results that are in the range of results produced be techniques where the constraints are not taken into account.     

基于仿真视频的光电跟踪器测试

介绍了一种基于仿真视频的光电跟踪器测试方案。先制作、编辑仿真视频,并经PCI总线下载至视频输出卡,再统一发送至跟踪器。通过对比实时采集的跟踪器脱靶量信息、仿真图像的目标质心坐标、图像中心坐标,判定跟踪器的跟踪准确度和稳定度,达到对跟踪器测试目的。     

一种基于BFT型拓扑结构片上网络低费用测试方法

随着集成电路制作工艺的进步,多核与众核系统是片上系统的发展趋势.传统的二维网格(2D-mesh)型拓扑结构通信效率低、功耗高和时延长等缺点变得越来越明显.本文首先分析对比了几种常用拓扑结构在多核与众核情况下的性能,进而采用布线复杂度较低、性能较好的蝴蝶型胖树(BFT)拓扑结构来解决片上系统的设计和测试问题.随后,本文针...     

TA-PSV—Timing Analysis for Partially Specified Vectors

We propose a new concept-timing analysis for partially specified vectors (TA-PSV)-that enables the computation of tight timing windows. At one extreme, when the vectors are completely unspecified, TA-PSV reduces to static timing analysis (STA). At the other extreme, when the vectors are completely specified, TA-PSV performs timing simulation (TS). We present a systematic approach to construct a computationally feasible TA-PSV framework using a delay model that captures simultaneous to-controlling switching effects. We also demonstrate how TA-PSV can improve timing validation and also that TA-PSV significantly improves efficiency of timing-oriented test generation by reducing the search space.