Wafer-level packaging technology for high-Q on-chip inductors and transmission lines

In the current trend toward portable applications, high-Q integrated inductors have gained considerable importance. Hence, much effort has been spent to increase the performance of on-chip Si inductors. In this paper, wafer-level packaging (WLP) techniques have been used to integrate state-of-the-art high-Q on-chip inductors on top of a five-levels-of-metal Cu damascene back-end of line (BEOL) silicon process using 20-/spl Omega//spl middot/cm Si wafers. The inductors are realized above passivation using thick post-processed low-K dielectric benzocyclobutene (BCB) and Cu layers. For a BCB-Cu thickness of 16 /spl mu/m/10 /spl mu/m, a peak single-ended Q factor of 38 at 4.7 GHz has been measured for a 1-nH inductor with a resonance frequency of 28 GHz. Removing substrate contacts slightly increases the performance, though a more significant improvement has been obtained by combining post-processed passives with patterned ground shields: for a 2.3-nH above integrated-circuit (above-IC) inductor, a 115% increase in Q/sub BW//sup max/ (37.5 versus 17.5) and a 192% increase in resonance frequency (F/sub res/: 12 GHz versus 5 GHz) have been obtained as compared to the equivalent BEOL realization with a patterned ground shield. Next to inductors, high-quality on-chip transmission lines may be realized in the WLP layers. Losses below -0.2 dB/mm at 25 GHz have been measured for 50-/spl Omega/ post-processed coplanar-waveguide lines, above-IC thin-film microstrip lines have measured losses below -0.12 dB/mm at 25 GHz.     

Characterization of spiral inductors with patterned floating structures

The impact of two different types of floating patterns on spiral inductors was investigated. Both patterned trench isolation with a floating p/n junction and floating metal poles were implemented underneath reference spiral inductors. All three types of inductors have an identical spiral geometry. Combination of patterned trench isolation with a floating p/n junction increases maximum quality factor (Q/sub max/) by 17% compared to the reference inductors. The floating metal poles enable adjustment of the frequency at Q/sub max/ (f/sub max/) without hampering the Q/sub max/. A ladder-type lump-element model was employed to analyze inductor performance after it was demonstrated to precisely capture behavior of all three inductors. Enhancement of the quality factor due to patterned trench isolation with a floating p/n junction was found to result from an increment of effective resistivity in substrates. Reduction of the frequency f/sub max/ due to the floating metal poles was caused by increasing effective coupling capacitance between the spiral inductors and substrate.     

Design and fabrication of deep submicron CMOS technology compatible suspended high-Q spiral inductors

In this paper, deep submicron complementary metal-oxide-semiconductor (CMOS) process compatible high-Q suspended spiral on-chip inductors were designed and fabricated. In the design, the electromagnetic solver, SONNET, and the finite element program, ANSYS, were used for electrical characteristics, maximum endurable impact force, and thermal conduction simulations, respectively. Based on the design, suspended spiral inductors with different air cavity structures, i.e., diamond opening, circle opening, triangle opening, and full suspended with pillar supports were developed for various applications. Among these structures, the suspended inductor with pillar support possesses the highest Q/sub max/ (maximum of quality factor) of 6.6 at 2 GHz, the least effective dielectric constant of 1.06, and the lowest endurable impact force 0.184 Newton. On the other hand, the spiral inductor with diamond opening has a lowest Q/sub max/ of 4.3, the largest effective dielectric constant of 3.44 and highest endurable impact force 4 Newton. The former is suitable for station telecommunication applications in which the mechanical vibration is not a serious concern, while the latter can be used for mobile telecommunication applications subject to strong mechanical vibrations. Additionally, the conventional on-chip spiral inductor embraced by SiO/sub 2/ with a dielectric constant of 4 was prepared for comparison and found its Q/sub max/ is 3.8 at 1.2 GHz.     

An ultralow-loss and broadband micromachined RF inductor for RFIC input-matching applications

In this brief, we demonstrate that ultralow-loss and broadband inductors can be obtained by using the CMOS process compatible backside inductively coupled-plasma (ICP) deep-trench technology to selectively remove the silicon underneath the inductors. The results show that a 378.5% increase in maximum Q-factor (Q/sub max/) (from 10.7 at 4.7 GHz to 51.2 at 14.9 GHz), a 22.1% increase in self-resonant frequency (f/sub SR/) (from 16.5 to 20.15 GHz), a 16.3% increase (from 0.86 to 0.9999) in maximum available power gain (G/sub Amax/) at 5 GHz, and a 0.654-dB reduction (from 0.654 dB to 4.08/spl times/10/sup -4/ dB) in minimum noise figure (NF/sub min/) at 5 GHz were achieved for a 2-nH inductor after the backside ICP dry etching. In addition, state-of-the-art ultralow-loss G/sub Amax//spl les/0.99 (i.e., NF/sub min//spl les/0.045 dB) for frequencies lower than 12.5 GHz was achieved for this 2-nH inductor after the backside inductively coupled-plasma dry etching. This means this on-chip inductor-on-air can be used to realize an ultralow-noise 3.1-10.6 GHz ultrawide-band RFIC. These results show that the CMOS process compatible backside ICP etching technique is very promising for system-on-a-chip applications.     

High-Q factor three-dimensional inductors

In this paper, the great flexibility of three-dimensional (3-D) monolithic-microwave integrated-circuit technology is used to improve the performance of on-chip inductors. A novel topology for high-Q factor spiral inductor that can be implemented in a single or multilevel configuration is proposed. Several inductors were fabricated on either silicon substrate (/spl rho/ = 30 /spl Omega/ /spl middot/ cm) or semi-insulating gallium-arsenide substrate demonstrating, more particularly, for GaAs technology, the interest of the multilevel configuration. A 1.38-nH double-level 3-D inductor formed on an Si substrate exhibits a very high peak Q factor of 52.8 at 13.6 GHz and a self-resonant frequency as high as 24.7 GHz. Our 4.9-nH double-level GaAs 3-D inductor achieves a peak Q factor of 35.9 at 4.7 GHz and a self-resonant frequency of 8 GHz. For each technology, the performance limits of the proposed inductors in terms of quality factor are discussed. Guidelines for the optimum design of 3-D inductors are provided for Si and GaAs technologies.     

High Q multilayer spiral inductor on silicon chip for 5/spl sim/6 GHz

High Q-values of spiral inductors at frequency around 5/spl sim/6 GHz have been achieved with a multilayer spiral (MLS) structure on a high loss silicon substrate. Compared to a one-layer spiral (OLS) inductor, the Q-value of a 4-nH inductor has been improved by about 80% at 5.65 GHz. The impact of the structure on Q-value and resonant frequency has been analyzed, which shows that an optimal height for the via of MLS inductors should be considered when inductors are designed. The fabrication process is compatible with Cu/SiO/sub 2/ interconnect technology.     

SOI technology for radio-frequency integrated-circuit applications

This paper presents a silicon-on-insulator (SOI) integration technology, including structures and processes of OFF-gate power nMOSFETs, conventional lightly doped drain (LDD) nMOSFETs, and spiral inductors for radio frequency integrated circuit (RFIC) applications. In order to improve the performance of these integrated devices, body contact under the source (to suppress floating-body effects) and salicide (to reduce series resistance) techniques were developed for transistors; additionally, locally thickened oxide (to suppress substrate coupling) and ultra-thick aluminum up to 6 /spl mu/m (to reduce spiral resistance) were also implemented for spiral inductors on high-resistivity SOI substrate. All these approaches are fully compatible with the conventional CMOS processes, demonstrating devices with excellent performance in this paper: 0.25-/spl mu/m gate-length offset-gate power nMOSFET with breakdown voltage (BV/sub DS/) /spl sim/ 22.0 V, cutoff frequency (f/sub T/)/spl sim/15.2 GHz, and maximal oscillation frequency (f/sub max/)/spl sim/8.7 GHz; 0.25-/spl mu/m gate-length LDD nMOSFET with saturation current (I/sub DS/)/spl sim/390 /spl mu/A//spl mu/m, saturation transconductance (g/sub m/)/spl sim/197 /spl mu/S//spl mu/m, cutoff frequency /spl sim/ 25.6 GHz, and maximal oscillation frequency /spl sim/ 31.4 GHz; 2/5/9/10-nH inductors with maximal quality factors (Q/sub max/) 16.3/13.1/8.95/8.59 and self-resonance frequencies (f/sub sr/) 17.2/17.7/6.5/5.8 GHz, respectively. These devices are potentially feasible for RFIC applications.     

一种采用LC谐振电路的高频差分有源电感

提出了一种采用LC并联谐振电路的新型差分有源电感,实现了宽的工作频带、高的Q值、较大的电感值和可调谐功能.采用无源电感和MOS晶体管可变电容构成LC谐振电路,减小了等效串联电阻和等效并联电容,在增大电感值、Q值的同时,扩大了工作频带.仿真结果表明,在2～7.6 GHz频率范围内,该新型差分有源电感的电感值大于26 nH...     

MMIC用多层磁膜电感研究

采用磁控溅射生长磁膜工艺,结合BCB(苯并环丁烯)平坦化技术,首次制作了"金属线圈/磁膜/金属线圈(M/F/M)"和"磁膜/金属线圈/磁膜/金属线圈(F/M/F/M)"两种结构的多层磁膜电感,整个工艺与标准MMIC工艺兼容.在2 GHz处,"金属线圈/磁膜/金属线圈"结构电感的电感量为7.5 nH,品质因数为7.17,...     

Selective metal parallel shunting inductor and its VCO application

The methodology to calculate the parasitic capacitances in differential symmetric inductors will be presented in this paper. Inspired by the proposed methodology, a method called selective metal parallel shunting (SMPS) can move f/sub Qmax/ onto the desired frequency without additional processing steps. Based on the proposed methodology, a customized program is developed to predict Q/sub max/s and f/sub Qmax/s of on-chip inductors. Differential symmetric inductors and spiral ones with planar, all metal parallel shunting (AMPS), and SMPS configurations have been implemented in a 1P4M 0.35-/spl mu/m CMOS process to verify the proposed method. Moreover, three 2.3-2.4 GHz voltage-controlled oscillators (VCOs) using planar, AMPS, and SMPS inductors, have also been realized. The phase noise of the VCO using SMPS inductors can be improved by 9.3 and 6 dB at 100-kHz offset frequency, respectively, compared to the VCOs using planar and AMPS inductors. The proposed SMPS technique can not only be applicable to VCO but also other RF circuits.     

Improvement of the quality factor of RF integrated inductors bylayout optimization

A systematic method to improve the quality (Q) factor of RF integrated inductors is presented in this paper. The proposed method is based on the layout optimization to minimize the series resistance of the inductor coil, taking into account both ohmic losses, due to conduction currents, and magnetically induced losses, due to eddy currents. The technique is particularly useful when applied to inductors in which the fabrication process includes integration substrate removal. However, it is also applicable to inductors on low-loss substrates. The method optimizes the width of the metal strip for each turn of the inductor coil, leading to a variable strip-width layout. The optimization procedure has been successfully applied to the design of square spiral inductors in a silicon-based multichip-module technology, complemented with silicon micromachining postprocessing. The obtained experimental results corroborate the validity of the proposed method. A Q factor of about 17 have been obtained for a 35-nH inductor at 1.5 GHz, with Q values higher than 40 predicted for a 20-nH inductor working at 3.5 GHz. The latter is up to a 60% better than the best results for a single strip-width inductor working at the same frequency     

On the design of RF spiral inductors on silicon

This review of design principles for implementation of a spiral inductor in a silicon integrated circuit fabrication process summarizes prior art in this field. In addition, a fast and physics-based inductor model is exploited to put the results contributed by many different groups in various technologies and achieved over the past eight years into perspective. Inductors are compared not only by their maximum quality factors (Q/sub max/), but also by taking the frequency at Q/sub max/, the inductance value (L), the self-resonance frequency (f/sub SR/), and the coil area into account. It is further explained that the spiral coil structure on a lossy silicon substrate can operate in three different modes, depending at first order on the silicon doping concentration. Ranging from high to low substrate resistivity, inductor-mode, resonator-mode, and eddy-current regimes are defined by characteristic changes of Q/sub max/, L, and f/sub SR/. The advantages and disadvantages of patterned or blanket resistive ground shields between the inductor coil and substrate and the effect of a substrate contact on the inductor are also addressed in this paper. Exploring optimum inductor designs under various constraints leverages the speed of the model. Finally, in view of the continuously increasing operating frequencies in advancing to new generations of RF systems, the range of feasible inductance values for given quality factors are predicted on the basis of optimum technological features.     

Q-factor definition and evaluation for spiral inductors fabricated using wafer-level CSP technology

A novel Q-factor definition and evaluation method are proposed for low-loss high-Q spiral inductors fabricated by using the wafer-level chip-size package (WLP) on silicon substrates, where the copper wiring technology with a polyimide isolation layer is used. In conventional Q-factor evaluation for inductors, a short-circuited load condition is used, where the Q factor is represented by using Y-parameters as Q=Im{1/Y/sub 11/}/Re{1/Y/sub 11/}. This conventional method provides a Q factor of 20 with 2-5-nH inductance around 3.9 GHz. However, since structures for the spiral inductors are asymmetrical, the short-circuited load condition and short-circuited source condition give different Q values, respectively. The Q-value differences of approximately 100% have often been observed in the WLP. The differences mainly come from differences in loss estimation. In a novel method, a complex conjugate impedance-matching condition is retained both at an input port and an output port of the inductor. The maximum available power gain (G/sub AMAX/) is introduced to evaluate the energy loss in one cycle. This condition provides a unique insertion loss of passive devices. Thus, the difference of the Q factor depends only on the difference of magnetic and electric energy. The difference of the Q value is reduced.     

High-performance large-inductance embedded inductors in thin array plastic packaging (TAPP) for RF system-in-package applications

We report the first demonstration of high-Q embedded inductors fabricated using a thin-array-plastic-packaging (TAPP) technology. The TAPP technology provides a platform that integrates digital, analog, RF integrated circuits, along with high-performance passive components for system-in-package implementation. Embedded inductors ranging from 14 to 300 nH were fabricated. All the inductors with inductance less than 100 nH exhibit self-resonant frequency above 1 GHz. For a 14-nH inductor, Q factor of 35 was achieved at 1.6 GHz and the self-resonance frequency was measured at 6.15 GHz.     

A 1.3-V 5-mW fully integrated tunable bandpass filter at 2.1 GHz in 0.35-/spl mu/m CMOS

A 2.1-GHz 1.3-V 5-mW fully integrated Q-enhancement LC bandpass biquad programmable in f/sub o/, Q, and peak gain is implemented in 0.35-/spl mu/m standard CMOS technology. The filter uses a resonator built with spiral inductors and inversion-mode pMOS capacitors that provide frequency tuning. The Q tuning is through an adjustable negative-conductance generator, whereas the peak gain is tuned through an input G/sub m/ stage. Noise and nonlinearity analyses presented demonstrate the design tradeoffs involved. Measured frequency tuning range around 2.1 GHz is 13%. Spiral inductors with Q/sub o/ of 2 at 2.1 GHz limit the spurious-free dynamic range (SFDR) at 31-34 dB within the frequency tuning range. Measurements show that the peak gain can be tuned within a range of around two octaves. The filter sinks 4 mA from a 1.3-V supply providing a Q of 40 at 2.19 GHz with a 1-dB compression point dynamic range of 35 dB. The circuit operates with supply voltages ranging from 1.2 to 3 V. The silicon area is 0.1 mm/sup 2/.     

Air Cavity Incorporation to LTCC Spiral Inductor for High Q-factor and SRF

We have devised a new LTCC spiral inductor incorporating an air cavity underneath for high Q-factor and high self-resonant frequency (SRF). The air cavity employed under the spiral reduces the shunt capacitance of the inductor, and results in high Q-factor and SRF of the embedded inductors. The optimized spiral inductor with the embedded air cavity shows a maximum Q of 51 and SRF of 9.1 GHz, while conventional spiral inductor has a maximum Q of 43 and SRF of 8 GHz with effective inductance of 2.7 nH.     

Temperature and substrate-impedance dependence of noise figure of monolithic RF inductors on silicon

In this letter, we analyze the effects of temperature (from -50/spl deg/C to 200/spl deg/C) and substrate impedance on the noise figure (NF) and quality factor (Q-factor) performances of monolithic RF inductors on silicon. The results show a 0.75 dB (from 0.98 to 0.23 dB) reduction in minimum NF (NF/sub min/) at 8 GHz, an 86.1% (from 15.1 to 28.1) increase in maximum Q-factor (Q/sub max/), and a 4.8% (from 16.5 to 17.3 GHz) improvement in self-resonant frequency (f/sub SR/) were obtained if post-process of proton implantation had been done. This means the post-process of proton implantation is effective in improving the NF and Q-factor performances of inductors on silicon mainly due to the reduction of eddy current loss in the silicon substrate. In addition, it was found that NF increases with increasing temperature but show a reverse behavior within a higher frequency range. This phenomenon can be explained by the positive temperature coefficients of the series metal resistance (R/sub s/), the parallel substrate resistances (R/sub sub1/ and R/sub sub2/), and the resistance R/sub s1/ of the substrate transformer loop. The present analyzes are helpful for RF designers to design less temperature-sensitive high-performance fully on-chip low-noise-amplifiers (LNAs) and voltage-controlled-oscillators (VCOs) for single-chip receiver front-end applications.     

Add-on Cu/SiLKTM module for high Q inductors

Thick Cu single damascene inductors are integrated on top of a standard aluminum three-levels-of-metal (3LM) back-end of line (BEOL) silicon process. The obtained Q factors are more than four times higher than Q factors of the inductors of the same geometry processed in the Al 3LM BEOL. For an inductor of 3 nH designed for 2-GHz frequency applications and fabricated in thick Cu/SiLK^TM1 as an add-on module, a Q factor of ~24 is reached. A compact two-section lumped element SPICE model is proposed and validated for both inductors in thick Cu/SiLK^TM and inductors in standard aluminum 3LM BEOL     

氧化多孔硅上制作Cu电感的研究

给出了一种厚膜氧化多孔硅(OPS)层上制作Cu电感的新型工艺技术。由于OPS是一种低损耗的材料,铜的电阻率很低,采用OPS隔离硅衬底和Cu线圈能够降低电感的寄生损耗,提高电感Q值。实验过程中将孔隙度>56%的多孔硅厚膜利用两步氧化法氧化为OPS厚膜,通过种子层溅射/光刻/电镀Cu/刻蚀种子层的方法完成了Cu线圈的电镀。获得了1nH的电感,其Q值在10GHz的频率下达到了9,电感的自谐振频率超过20GHz。     

Impedance Measurements of Microwave Lumped Elements from 1 to 12 GHz

The impedance measurement of small, microwave lumped elements of the order of 1 mm has been extended up to 12 GHz by a technique in which the frequency and Q of a resonant transmission line are perturbed by the connection of a lumped element. With the use of low-loss resonant coaxial lines, the technique has been applied to the measurement of lumped-element capacitors ranging from 0.4 to 3.6 pF and inductors ranging from 1.1 to 4.3 nH. Conductor Q values for capacitors as high as 1700 at 1.4 GHz and 100 at 12 GHz have been measured and estimates of dielectric Q values for capacitors of over 5000 have been obtained. Single-turn 1.1-nH inductor Q's of 40 at 1 GHz and 90 at 7 GHz have also been measured. The capacitors and single-turn inductors are found to have constant C and L values up to 12 GHz.