Improved reliability of low-temperature polysilicon TFT by post-annealing gate oxide

We have investigated the electrical characteristics of gate oxide films deposited by plasma enhanced chemical vapor deposition (PECVD) with respect to gate oxide integrity (GOI) and its reliability. In the investigation, post-annealed gate oxide was compared with as-deposited oxide. It was shown that the characteristics of GOI strongly depended on the charge trapping characteristics and deep level interface states generation under FN stress, which was remarkably improved by post-annealing after gate oxide deposition. Improved FN stress and hot carrier stress reliability of CMOS devices implemented on the glass substrate are also discussed.     

Lateral n-channel inversion mode 4H-SiC MOSFETs

Advances in MOS devices on silicon carbide (SiC) have been greatly hampered by the low inversion layer mobilities. In this paper, the electrical characteristics of lateral n-channel MOSFETs fabricated on 4H-SiC are reported for the first time. Inversion layer electron mobilities of 165 cm²/V·s in 4H-SiC MOSFETs were measured at room temperature. These MOSFETs were fabricated using a low temperature deposited oxide, with subsequent oxidation anneal, as the gate dielectric     

Refractory metal silicon device technology

Films 2000–5000 Å thick of Mo or W deposited over thin films of thermally grown SiO₂ are shown to be effective high temperature diffusion masks against both phosphorous and boron. These metal films may be precisely patterned and their diffusion masking properties can be used to define the source and drain regions of MOSFETs. In this manner, self-registered MOSFETs can be fabricated with a portion of the diffusion masking metal film acting as the gate electrode. Using P or B doped deposited glasses as diffusion sources, n or p channel enhancement mode MOSFETs were made by diffusion through the exposed thin SiO₂ film into p and n type Si to form source and drain junctions. Contact was subsequently made by etching holes through the oxide layers to the source and drain regions and to the refractory metal gate electrode buried within the oxide layers. These devices exhibit channel mobilities between 200 and 300 cm²/V-sec at gate voltages about 10 V above threshold. The stability of MOS structures processed in a similar manner has been measured. After being stressed at ±6 × 10⁵ V/cm and 250°C for 15 hr, these devices exhibited shifts in their C---V characteristics less than 200 mV.     

Reduction of the parasitic charge generation during silicon nitride deposition in a LOCOS isolation without field implant

MOS integrated circuits use the Local oxidation of silicon to isolate laterally adjacent devices (LOCOS isolation). The insulation structure is typically formed by a semiconductor region doped by ion implantation (field implant) and covered by a thick thermal oxide (field oxide). Other insulators (plasma enhanced chemical vapor deposited (PECVD) silicon oxides and LPCVD silicon nitride) and metal interconnection are subsequently deposited on the field oxide. The ion implant together with the thick insulator ensure a high threshold voltage value of the parasitic MOS transistor formed by source and drain of the adjacent active devices and by the insulator/interconnection gate.However, economical purpose leads to the extension of the application field of lower cost technology, addressing the problem of LOCOS isolation without any field implant. As already shown in a previous work [Fay JL, Beluch J, Allirand L, Brosset D, Despax B, Bafleur M, Sarrabayrose G. Jpn J Appl Phys 38(9A):5012–7] for inter-layer dielectric applications, our PECVD oxides suffer from excessive concentration of fixed positive charges brought about by the silicon nitride deposition, and causing the N-channel field threshold voltage to decrease.Characterization reveals that these charges are generated by diffusion of species coming from the gas phase during the silicon nitride process. These generated charges can be reduced either by increasing the O₂/tetra-ethyl orthosilicate ratio or by doping the oxide with boron and phosphorus. To avoid diffusion and generation of charges, we minimized the thermal budget using a PECVD silicon nitride. With this process, we have achieved a high threshold voltage and an acceptably low leakage current of the NMOS parasitic transistor.     

Fabrication and Performance of 0.25-$mu$m Gate Length Depletion-Mode GaAs-Channel MOSFETs With Self-Aligned InAlP Native Oxide Gate Dielectric

The fabrication and performance of 0.25- mum gate length GaAs-channel MOSFETs using the wet thermal native oxide of InAlP as the gate dielectric are reported. A fabrication process that self-aligns the gate oxidation to the gate recess and metallization to reduce the source access resistance is demonstrated for the first time. The fabricated devices exhibit a peak extrinsic transconductance of 144 mS/mm, an on-resistance of 3.46 Omega-mm, and a threshold voltage of -1.8 V for typical 0.25 -mum gate devices. A record cutoff frequency of 31 GHz for a GaAs-channel MOSFET and a maximum frequency of oscillation f_max of 47 GHz have also been measured.     

Electrical properties of Ru-based alloy gate electrodes for dualmetal gate Si-CMOS

In this letter, low resistivity Ru and Ru-Ta alloy films, deposited via reactive sputtering, were evaluated as gate electrodes for p- and n-MOSFET devices, respectively. MOSFETs fabricated via a conventional process flow indicated that the work functions of Ru and Ru-Ta alloys were compatible with p- and n-MOSFET devices, respectively. Both of the metal gated devices eliminated gate depletion effects. Good MOSFET characteristics, such as I_DS-V_GS and mobility, were obtained for both Ru-gated PMOSFETs and Ru-Ta gated NMOSFETs     

Enhancement-Mode Buried-Channel $hbox{In}_{0.7} hbox{Ga}_{0.3}hbox{As/In}_{0.52}hbox{Al}_{0.48}hbox{As}$ MOSFETs With High- $kappa$ Gate Dielectrics

The operation of long- and short-channel enhancement-mode In_0.7Ga_0.3As-channel MOSFETs with high-k gate dielectrics are demonstrated for the first time. The devices utilize an undoped buried-channel design. For a gate length of 5 mum, the long-channel devices have V_t= +0.25 V, a subthreshold slope of 150 mV/dec, an equivalent oxide thickness of 4.4 +/ - 0.3 nm, and a peak effective mobility of 1100 cm²/Vldrs. For a gate length of 260 nm, the short-channel devices have V_t=+0.5 V and a subthreshold slope of 200 mV/dec. Compared with Schottky-gated high-electron-mobility transistor devices, both long- and short-channel MOSFETs have two to four orders of magnitude lower gate leakage.     

90nm pMOSFET脱耦等离子体制备氮氧化硅的负偏压温度失稳性(英文)

MOSFET器件继续微缩则闸极氧化层厚度将持续减小,在0.13μm的技术闸极二氧化硅的厚度必须小于2nm,然而如此薄的氧化层直接穿透电流造成了明显的漏电流。为了降低漏电流,二氧化硅导入高浓度的氮如脱耦等离子体氮化制备氮氧化硅受到高度重视。然而,脱耦等离子体氮化制备氮氧化硅的一项顾虑是pMOSFET负偏压温度的失稳性。在此研究里测量了脱耦等离子体氮化制备氮氧化硅pMOSFET负偏压温度失稳性,并且和传统的二氧化硅闸电极比较,厚度1.5nm的脱耦等离子体氮化制备氮氧化硅pMOSFET和厚度1.3nm的二氧化硅pMOSFET经过125℃和10.7MVcm的电场1h的应力下比较阈值电压,结果显示脱耦等离子体氮化制备氮氧化硅pMOSFET在负偏压温度应力下性能较差。在15%阈值电压改变的标准下,延长10年的寿命,其最大工作电压是1.16V,可以符合90nm工艺1V特操作电压的安全范围内。     

Process damage-free damascene metal gate technology for gentle integration of epitaxially grown high-k

This paper presents the first successful attempt to integrate crystalline high-k gate dielectrics into a virtually damage-free damascene metal gate process. Process details as well as initial electrical characterization results on fully functional gate Gd₂O₃ dielectric MOSFETs with equivalent oxide thickness (EOT) down to 1.9 nm are discussed and compared with devices with rare-earth gate dielectrics fabricated previously in a conventional CMOS process.     

90 nm pMOSFET脱耦等离子体制备氮氧化硅的负偏压温度失稳性

MOSFET器件继续微缩则闸极氧化层厚度将持续减小,在0.13μm的技术闸极二氧化硅的厚度必须小于2 nm,然而如此薄的氧化层直接穿透电流造成了明显的漏电流.为了降低漏电流,二氧化硅导入高浓度的氮如脱耦等离子体氮化制备氮氧化硅受到高度重视.然而,脱耦等离子体氮化制备氮氧化硅的一项顾虑是pMOSFET负偏压温度的失稳性.在此研究里测量了脱耦等离子体氮化制备氮氧化硅pMOSFET负偏压温度失稳性,并且和传统的二氧化硅闸电极比较,厚度1.5 nm的脱耦等离子体氮化制备氮氧化硅pMOSFET和厚度1.3 nm的二氧化硅pMOSFET经过125℃和10.7MV/cm的电场1 h的应力下比较阈值电压,结果显示脱耦等离子体氮化制备氮氧化硅pMOSFET在负偏压温度应力下性能较差.在15%阈值电压改变的标准下,延长10年的寿命,其最大工作电压是1.16 V,可以符合90 nm工艺1 V特操作电压的安全范围内.     

Off-state gate current in n-channel MOSFETs with nitrided oxidegate dielectrics

The authors report on the off-state gate current (I_g ) characteristics of n-channel MOSFETs using thin nitrided oxide (NO) gate dielectrics prepared by rapid thermal nitridation at 1150°C for 10-300 s. New phenomena observed in NO devices are a significant I_g at drain voltages as low as 4 V and an I_g injection efficiency reaching 0.8, as compared to 8.5 V and 10^-7 in SiO₂ devices with gate dielectrics of the same thickness. Based on the drain bias and temperature dependence, it is proposed that I_g in MOSFETs with heavily nitrided oxide gate dielectrics arises from hot-hole injection, and the enhancement of gate current injection is due to the lowering of valence-band barrier height for hole emission at the NO/Si interface. The enhanced gate current injection may cause accelerated device degradation in MOSFETs. However, it also presents potential for device applications such as EPROM erasure     

Improved high-voltage lateral RESURF MOSFETs in 4H-SiC

High-voltage lateral RESURF metal oxide semiconductor field effect transistors (MOSFETs) in 4H-SiC have been experimentally demonstrated, that block 900 V with a specific on-resistance of 0.5 Ω-cm² . The RESURF dose in 4H-SiC to maximize the avalanche breakdown voltage is almost an order of magnitude higher than that of silicon; however this high RESURF dose leads to oxide breakdown and reliability concerns in thin (100-200 nm) gate oxide devices due to high electric field (>3-4 MV/cm) in the oxide. Lighter RESURF doses and/or thicker gate oxides are required in SiC lateral MOSFETs to achieve highest breakdown voltage capability     

Polysilicon gate enhancement of the random dopant induced thresholdvoltage fluctuations in sub-100 nm MOSFETs with ultrathin gateoxide

In this paper, we investigate various aspects of the polysilicon gate influence on the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFETs with ultrathin gate oxides. The study is done by using an efficient statistical three-dimensional (3D) “atomistic” simulation technique. MOSFETs with uniform channel doping and with low doped epitaxial channels have been investigated. The simulations reveal that even in devices with a single crystal gate the gate depletion and the random dopants in it are responsible for a substantial fraction of the threshold voltage fluctuations when the gate oxide is scaled to thickness in the range of 1-2 nm. Simulation experiments have been used in order to separate the enhancement in the threshold voltage fluctuations due to an effective increase in the oxide thickness associated with the gate depletion from the direct influence of the random dopants in the gate depletion layer. The results of the experiments show that the both factors contribute to the enhancement of the threshold voltage fluctuations, but the effective increase in the oxide thickness has a dominant effect in the investigated range of devices. Simulations illustrating the effect of the polysilicon grain boundaries on the threshold voltage variation are also presented     

A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs

A compact, physical, short-channel threshold voltage model for undoped symmetric double-gate MOSFETs has been derived based on an analytical solution of the two-dimensional (2-D) Poisson equation with the mobile charge term included. The new model is verified by published numerical simulations with close agreement. Applying the newly developed model, threshold voltage sensitivities to channel length, channel thickness, and gate oxide thickness have been comprehensively investigated. For practical device designs the channel length causes 30-50% more threshold voltage variation than does the channel thickness for the same process tolerance, while the gate oxide thickness causes the least, relatively insignificant threshold voltage variation. Model predictions indicate that individual DG MOSFETs with good turn-off behavior are feasible at 10 nm scale; however, practical exploitation of these devices toward gigascale integrated systems requires development of novel technologies for significant improvement in process control.     

全耗尽SOI MOSFETs阈值电压解析模型

提出了一种新的全耗尽SOI MOSFETs阈值电压二维解析模型.通过求解二维泊松方程得到器件有源层的二维电势分布函数,氧化层-硅界面处的电势最小值用于监测SOI MOSFETs的阈值电压.通过对不同栅长、栅氧厚度、硅膜厚度和沟道掺杂浓度的SOI MOSFETs的MEDICI模拟结果的比较,验证了该模型,并取得了很好的一致性.     

Unpinned GaAs MOS capacitors and transistors

Metal-oxide-semiconductor (MOS) capacitors and field-effect transistors (MOSFETs) in the GaAs semiconductor system using an unpinned interface are described. The structures utilize plasma-enhanced chemical-vapor deposition (PECVD) for the silicon-dioxide insulator on GaAs that has been terminated with a few monolayers of silicon during growth by molecular beam epitaxy. Interface densities in the structures have been reduced to ~10¹² cm^-2·eV^-1 . High-frequency characteristics indicate strong inversion of both p-type and n-type GaAs. The excellent insulating quality of the oxide has allowed demonstration of quasi-static characteristics. MOSFETs operating in depletion mode with a transconductance of 60 mS/mm at 8.0-μm gate lengths have been fabricated     

Effect of CF/sub 4/ plasma pretreatment on low temperature oxides

This study describes a novel technique for forming low temperature oxides (<350/spl deg/C) using a replacement metal gate process. Low temperature oxides were generated by N/sub 2/O plasma in a PECVD system with pretreatment in CF/sub 4/. Fabricated oxides demonstrate excellent current-voltage (I-V) characteristics, such as low leakage current, high breakdown charge and good reliability. Experimental results indicate that CF/sub 4/ plasma treatment can significantly improve the mobility and resistance against hot carrier stress of MOSFETs. With excellent electrical properties, this technique is suitable for fabrication low temperature devices.     

Improved hot-carrier resistance with fluorinated gate oxides

Improved OFF-state hot-carrier resistance in n-channel MOSFETs observed for fluorinated gate oxides is discussed. One-micrometer fluorinated devices consistently showed approximately three times smaller transconductance reduction and threshold-voltage shift relative to the control (nonfluorinated) MOSFETs. The fluorine was incorporated into the gate oxide by low-energy ion implantation followed by a 920°C diffusion. Subthreshold measurements taken before and after hot-electron stress explicitly show the reduction in interface state generation with fluorine incorporation     

Ultrathin gate oxide CMOS with nondoped selective epitaxial Sichannel layer

The nondoped selective epitaxial Si channel technique has been applied to ultrathin gate oxide CMOS transistors. It was confirmed that drain current drive and transconductance are improved in the epitaxial channel MOSFETs with ultrathin gate oxides in the direct-tunneling regime. It was also found that the epitaxial Si channel noticeably reduces the direct-tunneling gate leakage current. The relation between channel impurity concentration and direct-tunneling gate leakage current was investigated in detail. It was confirmed that the lower leakage current in epitaxial channel devices was not completely explained by the lower impurity concentration in the channel. The results suggest that the improved leakage current in the epitaxial channel case is attributable to the improvement of some aspect of the oxide film quality, such as roughness or defect density, and that the improvement of the oxide film quality is essential for ultrathin gate oxide CMOS. AFM and 1/f noise results support that SiO₂-Si interface quality in epitaxial Si channel MOSFETs is improved. Good performance and lower leakage current of TiN gate electrode CMOS was also demonstrated     

An assessment of single-electron effects in multiple-gate SOI MOSFETs with 1.6-nm gate oxide near room temperature

This letter provides an assessment of single-electron effects in ultrashort multiple-gate silicon-on-insulator (SOI) MOSFETs with 1.6-nm gate oxide. Coulomb blockade oscillations have been observed at room temperature for gate bias as low as 0.2 V. The charging energy, which is about 17 meV for devices with 30-nm gate length, may be modulated by the gate geometry. The multiple-gate SOI MOSFET, with its main advantage in the suppression of short-channel effects for CMOS scaling, presents a very promising scheme to build room-temperature single-electron transistors with standard silicon nanoelectronics process.