恒电流应力引起HfO2栅介质薄膜的击穿特性

利用磁控溅射的方法在p-Si上制备了高k(高介电常数)栅介质HfO2薄膜的MOS电容,对薄栅氧化层电容的软击穿和硬击穿特性进行了实验研究.利用在栅极加恒电流应力的方法研究了不同面积HfO2薄栅介质的击穿特性以及击穿对栅介质的I-V特性和C-V特性的影响.实验结果表明薄栅介质的击穿过程中有很明显的软击穿现象发生,与栅氧化层面积有很大的关系,面积大的电容比较容易发生击穿.分析比较了软击穿和硬击穿的区别,并利用统计分析模型对薄栅介质的击穿机理进行了解释.     

HfO2高K栅介质薄膜的电学特性研究

研究了高 K(高介电常数 )栅介质 Hf O2 薄膜的制备工艺 ,制备了有效氧化层厚度为 2 .9nm的超薄MOS电容。对电容的电学特性如 C-V特性 ,I-V特性 ,击穿特性进行了测试。实验结果显示 :Hf O2 栅介质电容具有良好的 C-V特性 ,较低的漏电流和较高的击穿电压。因此 ,Hf O2 栅介质可能成为 Si O2 栅介质的替代物。     

超薄HfO2高K栅介质薄膜的软击穿特性

研究了高K(高介电常数)栅介质HfO2薄膜的制备工艺,制备了有效氧化层厚度为2.9nm的超薄MOS电容。当栅氧化层很薄时会发生软击穿现象,软击穿和通常的硬击穿是不同的现象。分别利用在栅介质上加恒流应力和恒压应力两种方法研究了HfO2薄膜的击穿特性,实验结果表明,在两种应力方式下HfO2栅介质均发生了软击穿现象,软击穿和硬击穿的机理不同。     

氮化H2-O2合成薄栅介质的击穿特性

研究了14～16nm的H2-O2合成薄栅介质击穿特性.实验发现,N2O气氛氮化H2-O2合成法制备的薄栅介质能够有效地提高栅介质的零时间击穿特性.H2-O2合成法制备的样品,其击穿场强分布特性随测试MOS电容面积的增加而变差,而氮化H2-O2合成薄栅介质的击穿特性随测试MOS电容面积的增加基本保持不变.对于时变击穿,氮化同样能够明显提高栅介质的击穿电荷及其分布.     

氮化H2-O2合成薄栅介质的击穿特性

研究了14～16nm的H2-O2合成薄栅介质击穿特性.实验发现,N2O气氛氮化H2-O2合成法制备的薄栅介质能够有效地提高栅介质的零时间击穿特性.H2-O2合成法制备的样品,其击穿场强分布特性随测试MOS电容面积的增加而变差,而氮化H2-O2合成薄栅介质的击穿特性随测试MOS电容面积的增加基本保持不变.对于时变击穿,氮化同样能够明显提高栅介质的击穿电荷及其分布.     

Al_2O_3高k栅介质的可靠性

利用反应溅射方法制备了等效氧化层厚度为3 45nm的Al2 O3栅介质MOS电容,研究了Al2 O3作为栅介质的瞬时击穿和恒压应力下的时变击穿等可靠性特征.击穿实验显示,样品的Al2 O3栅介质的等效击穿场强大小为1 2 8MV/cm .在时变击穿的实验中,Al2 O3栅介质表现出类似于SiO2 的软击穿现象.不同栅压应力作用的测试结果表明,介质中注入电荷的积累效应是引起软击穿的主要因素,其对应的介质击穿电荷QBD约为30～60C/cm2 .     

3—6nm超薄SiO_2栅介质的特性

采用栅氧化前硅表面在 H2 SO4/ H2 O2 中形成化学氧化层方法和氮气稀释氧化制备出 3.2、 4和 6 nm的 Si O2超薄栅介质 ,并研究了其特性 .实验结果表明 ,恒流应力下 3.2和 4nm栅介质发生软击穿现象 .随着栅介质减薄 ,永久击穿电场强度增加 ,但恒流应力下软击穿电荷下降 .软击穿后栅介质低场漏电流无规则增大 .研究还表明 ,用软击穿电荷分布计算超薄栅介质有效缺陷密度比用永久击穿场强分布计算的要大 .在探讨软击穿和永久击穿机理的基础上解释了实验结果     

Al2O3高k栅介质的可靠性

利用反应溅射方法制备了等效氧化层厚度为3.45nm的Al2O3栅介质MOS电容,研究了Al2O3作为栅介质的瞬时击穿和恒压应力下的时变击穿等可靠性特征.击穿实验显示,样品的Al2O3栅介质的等效击穿场强大小为12.8MV/cm.在时变击穿的实验中,Al2O3栅介质表现出类似于SiO2的软击穿现象.不同栅压应力作用的测试结果表明,介质中注入电荷的积累效应是引起软击穿的主要因素,其对应的介质击穿电荷QBD约为30～60C/cm2.     

超薄Si3N4/SiO2叠层栅介质可靠性研究

实验成功地制备出等效氧化层厚度为亚2nm的Nitride/Oxynitride(N/O)叠层栅介质难熔金属栅电极PMOS电容并对其进行了可靠性研究.实验结果表明相对于纯氧栅介质而言,N/O叠层栅介质具有更好的抗击穿特性,应力诱生漏电特性以及TDDB特性.进一步研究发现具有更薄EOT的难熔金属栅电极PMOS电容在TDDB特性以及寿命等方面均优于多晶硅栅电极的相应结构.     

Al2O3高k栅介质的可靠性

利用反应溅射方法制备了等效氧化层厚度为3．45nm的Al2O3栅介质MOS电容，研究了Al2O3作为栅介质的瞬时击穿和恒压应力下的时变击穿等可靠性特征．击穿实验显示，样品的Al2O3栅介质的等效击穿场强大小为12.8MV／cm.在时变击穿的实验中，Al2O3栅介质表现出类似于SiO2的软击穿现象．不同栅压应力作用的测试结果表明，介质中注入电荷的积累效应是引起软击穿的主要因素，其对应的介质击穿电荷QBD约为30～60C／cm^2．     

Assessment of oxide reliability and hot carrier degradation in CMOS technology

The techniques and methodologies to be applied in R&D laboratories for the assessment of thin gate dielectrics reliability and hot carrier degradation are reviewed. Examples are given on how the application of these techniques allows to obtain a better insight in the physics of the degradation process. Two such examples are given related to the Dielectric breakdown of thin gate dielectrics and on the Stress-Induced Leakage Current in thin dielectrics.     

薄栅氮化物的击穿特性

研究了含 N MOS薄栅介质膜的击穿电场和电荷击穿特性。结果表明 :MOS栅介质中引入一定的 N后 ,能提高介质的电荷击穿强度 ,电荷击穿强度受 N2 O退火温度的制约 ;N对薄栅介质的击穿电场强度影响甚微 ,击穿电场受栅偏压极性的制约。用一定模型解释了实验结果     

Effects of radiation and charge trapping on the reliability of high-κ gate dielectrics

The radiation response and long term reliability of alternative gate dielectrics will play a critical role in determining the viability of these materials for use in future space applications. The total dose radiation responses of several near and long term alternative gate dielectrics to SiO₂ are discussed. Radiation results are presented for nitrided oxides, which show no change in interface trap density with dose and oxide trapped charge densities comparable to ultra thin thermal oxides. For aluminum oxide and hafnium oxide gate dielectric stacks, the density of oxide trapped charge is shown to depend strongly on the film thickness and processing conditions. The alternative gate dielectrics discussed here are shown to have effective trapping efficiencies that are up to 15 to 20 times larger than thermal SiO₂ of equivalent electrical thickness. A discussion of single event effects in devices and ICs is also provided. It is shown that some alternative gate dielectrics exhibit excellent tolerance to heavy ion induced gate dielectric breakdown. However, it is not yet known how irradiation with energetic particles will affect the long term reliability of MOS devices with high-κ gate dielectrics in a space environment.     

Atomic-layer-deposited silicon-nitride/SiO2 stack––a highly potential gate dielectrics for advanced CMOS technology

An extremely thin (2 monolayers) silicon nitride layer has been deposited on thermally grown SiO₂ by an atomic-layer-deposition (ALD) technique and used as gate dielectrics in metal–oxide–semiconductor (MOS) devices. The stack dielectrics having equivalent oxide thickness (T_eq=2.2 nm) efficiently reduce the boron diffusion from p⁺ poly-Si gate without the pile up of nitrogen atoms at the SiO₂/Si interface. The ALD silicon nitride is thermally stable and has very flat surface on SiO₂ especially in the thin (<0.5 nm) thickness region.An improvement has been obtained in the reliability of the ALD silicon-nitride/SiO₂ stack gate dielectrics compared with those of conventional SiO₂ dielectrics of identical thickness. An interesting feature of soft breakdown free phenomena has been observed only in the proposed stack gate dielectrics. Possible breakdown mechanisms are discussed and a model has been proposed based on the concept of localized physical damages which induce the formation of conductive filaments near both the poly-Si/SiO₂ and SiO₂/Si-substrate interfaces for the SiO₂ gate dielectrics and only near the SiO₂/Si-substrate interface for the stack gate dielectrics.Employing annealing in NH₃ at a moderate temperature of 550 °C after the ALD of silicon nitride on SiO₂, further reliability improvement has been achieved, which exhibits low bulk trap density and low trap generation rate in comparison with the stack dielectrics without NH₃ annealing.Because of the excellent thickness controllability and good electronic properties, the ALD silicon nitride on a thin gate oxide will fulfill the severe requirements for the ultrathin stack gate dielectrics for sub-0.1 μm complementary MOS (CMOS) transistors.     

Study of low-frequency charge pumping on thin stacked dielectrics

The application of low-frequency charge pumping to obtain near-interface, or bulk trap densities, on thin stacked gate dielectrics is studied. A review of the theory governing the low-frequency charge pumping technique, developed to extract bulk trap densities from metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated with thick SiO₂ dielectrics, is given. In this study, the technique is applied to a series of n-channel MOSFETs fabricated with stacked gate dielectrics. The dielectric stacks were comprised of rapid thermal oxide (RTO) interface layers and rapid thermal chemical vapor deposited (RTCVD) oxynitride layers, which incorporated varying concentrations of nitrogen. The effect of DC tunneling currents on the technique is studied, and a procedure to remove these components from the measured substrate current is outlined. Distortions in the experimentally measured charge pumping current plotted as a function of gate bias is modeled and found to be due to the contribution of bulk traps. Finally, the limitations of applying a model that was originally developed for thick SiO₂ dielectrics to thin stacked gate dielectrics are discussed     

Carrier mobility in p-MOSFET with atomic-layer-deposited Si-nitride/SiO/sub 2/ stack gate dielectrics

P/sup +/-poly-Si gate MOS transistors with atomic-layer-deposited Si-nitride/SiO/sub 2/ stack gate dielectrics (EOT=2.50 nm) have been fabricated. Similar to the reference samples with SiO/sub 2/ gate dielectrics (T/sub ox/=2.45 nm), clear saturation characteristics of drain current are obtained for the samples with stack gate dielectrics. Identical hole-effective mobility is obtained for the samples with the SiO/sub 2/ and the stack gate dielectrics. The maximum value of hole-effective mobility is the same (54 cm/sup 2//Vs) both for the stack and the SiO/sub 2/ samples. Hot carrier-induced mobility degradation in transistors with the stack gate dielectrics was found to be identical to that in transistors with the SiO/sub 2/ gate dielectrics. In addition to the suppression of boron penetration, better TDDB characteristics, and soft breakdown free phenomena for the stack dielectrics (reported previously), the almost equal effective mobility (with respect to that of SiO/sub 2/ dielectrics) has ensured the proposed stack gate dielectrics to be very promising for sub-100-nm technology generations.     

Solution‐Processed HafSOx and ZircSOx Inorganic Thin‐Film Dielectrics and Nanolaminates

New thin‐film dielectrics and nanolaminates have been synthesized via aqueous‐solution deposition of Hf and Zr sulfates, where facile gelation and vitrification of the precursor solution have been achieved without organic additives. X‐ray reflectivity, imaging, and metal‐insulator‐metal capacitor performance reveal that smooth, atomically dense films are readily produced by spin coating and modest thermal treatment (T < 325 °C). Dielectric characteristics include permittivities covering the range of 9–12 with breakdown fields up to 6 MV cm^–1. Performance as gate dielectrics is demonstrated in field‐effect transistors exhibiting small gate‐leakage currents and qualitatively ideal device performance. The low‐temperature processing, uniformity, and pore‐free nature of the films have also allowed construction of unique, high‐resolution nanolaminates exhibiting individual layers as thin as 3 nm.     

Electrical Properties of Ultra Thin Nitride/Oxynitride Stack Dielectrics pMOS Capacitor with Refractory Metal Gate

Electrical properties of high quality ultra thin nitride/oxynitride（N/O）stack dielectrics pMOS capacitor with refractory metal gate electrode are investigated，and ultra thin (＜2 nm＝ N/O stack gate dielectrics with significant low leakage current and high resistance to boron penetration are fabricated.Experiment results show that the stack gate dielectric of nitride/oxynitride combined with improved sputtered tungsten/titanium nitride (W/TiN) gate electrode is one of the candidates for deep sub-micron metal gate CMOS devices.