Fully integrated CMOS fractional-N frequency divider for wide-band mobile applications with spurs reduction

A spurs reduction fractional-N frequency divider with a frequency range which is 3.5 times larger than that of a conventional fractional-N divider is presented in this paper. A 1.2-GHz quadrature voltage-controlled oscillator (VCO) is designed as the input source of the frequency divider. The circuit was fabricated using the 0.25-/spl mu/m CMOS technology. The power consumption of the frequency divider and the quadrature VCO are 3 and 6 mW, respectively, at a 2-V supply.     

Transmission-line stabilized monolithic oscillators

A novel technique for frequency stabilization and phase-noise reduction of monolithic oscillators is presented in this paper. It employs simple transmission-line resonators, which are many wavelengths long to increase the oscillator quality factor. Monolithic oscillators at 20 and 40 GHz are realized for the application of this technique. Phase noise reduction of more than 20 dB was achieved for both oscillators. The single-sideband phase noise obtained was -100 dBc/Hz at 100-kHz offset for the 20-GHz oscillator and -90 dBc/Hz at 1-MHz offset for the 40-GHz oscillator. The approach is implemented by using readily available transmission lines, which are open- or short-circuited at one end and connected to the monolithic-microwave integrated-circuit (MMIC) oscillator at the other end. Thus, it presents significant potential in the development of low-cost MMIC oscillators with enhanced noise performance     

K-band and millimeter-wave MMICs for emerging commercial wirelessapplications

The recent K-band monolithic-microwave integrated-circuit (MMIC) technologies for the local multipoint distribution service systems and novel MMIC technologies for potential low-cost millimeter-wave MMICs are presented in this paper via a review of Fujitsu Quantum Devices Limited technology. The devices being demonstrated are a 23-26-GHz 2-W power amplifier module with a broad-band driver amplifier, a 19-33-GHz miniature low-noise amplifier, a frequency multiplier by four for K-band local oscillators, a flip-chip MMIC module for radar application, and three-dimensional MMIC image-rejection harmonic mixers. Through these devices, the recent trend of design and fabrication methodologies for the K-band and millimeter-wave devices will be described     

MMIC family for DBS down-converter with pulse-doped GaAs MESFETs

A monolithic microwave integrated circuit (MMIC) family was demonstrated as a low-noise block (LNB) downconverter for use in direct broadcast satellite (DBS) receivers operating from 11.7 to 12 GHz. A 12-GHz low-noise amplifier (LNA), a 12-GHz mixer (MIX), a 10.7-GHz dielectric resonator oscillator (DRO), and a 1-GHz IF amplifier (IFA) were designed with GaAs MMIC technology. These MMIC chips were designed to form a complete LNB downconverter function with the exception of the dielectric resonator. The most significant result of this work is that practical low-noise performance can be achieved without the use of high-electron-mobility transistors (HEMTs) in a preceding stage of the MMIC LNB downconverter. Almost noise-free satellite broadcast TV pictures were seen by using a parabolic antenna, 40 cm in diameter, without needing any additional circuit adjustment     

Low phase noise millimeter-wave frequency sources using InP-basedHBT MMIC technology

A family of millimeter-wave sources based on InP heterojunction bipolar transistor (HBT) monolithic microwave/millimeter-wave integrated circuit (MMIC) technology has been developed. These sources include 40-GHz, 46-GHz, 62-GHz MMIC fundamental mode oscillators, and a 95-GHz frequency source module using a 23.8-GHz InP HBT MMIC dielectric resonator oscillator (DRO) in conjunction with a GaAs-based high electron mobility transistor (HEMT) MMIC frequency quadrupler and W-band output amplifiers. Good phase noise performance was achieved due to the low 1/f noise of the InP-based HBT devices. To our knowledge, this is the first demonstration of millimeter-wave sources using InP-based HBT MMIC's     

Development of 60-GHz front-end circuits for a high-data-rate communication system

Recent results from a Swedish program for development of 60-GHz monolithic microwave integrated circuits (MMICs) for high-data-rate communication links are presented. Front-end circuits such as mixers, amplifiers, frequency multipliers, IF amplifiers with gain control, and voltage-controlled oscillators (VCOs) have been realized utilizing GaAs PHEMT and MHEMT technologies. A newly developed 7.5-GHz coupled Colpitt VCO shows a minimum phase noise of -95 dBc at 100 kHz offset. A second-harmonic 14-GHz VCO shows a minimum phase noise of less than -90 dBc at 100 kHz. A novel balanced 7-28-GHz MMIC frequency quadrupler is described and compared with a single-ended quadrupler at the same input frequencies. To demonstrate its feasibility and potential application, the quadrupler is combined with the Colpitt VCO and the output characteristics of the resulting 30-GHz MMIC source are measured. A three-stage MHEMT wide-band amplifier covering 43-64 GHz with a gain of 24 dB, a minimum noise figure of 2.5 dB, and a passband ripple of 2 dB is also described. In future 60-GHz systems for mass markets where cost is of utmost importance, Si-based technologies, especially CMOS, are highly interesting. Some recent circuit results based on a 90-nm CMOS technology are also reported.     

A 2.4-GHz ring-oscillator-based CMOS frequency synthesizer with a fractional divider dual-PLL architecture

A 2.4-GHz frequency synthesizer was designed that uses a fractional divider to drive a dual-phase-locked-loop (PLL) structure, with both PLLs using only on-chip ring oscillators. The first-stage narrow-band PLL acts as a spur filter while the second-stage wide-band PLL suppresses VCO phase noise so that simultaneous suppression of phase noise and spur is achieved. A new low-power, low-noise, low-frequency ring oscillator is designed for this narrow-band PLL. The chip was designed in 0.35-/spl mu/m CMOS technology and achieves a phase noise of -97 dBc/Hz at 1-MHz offset and spurs of -55 dBc. The chip's output frequency varies from 2.4 to 2.5 GHz; the chip consumes 15 mA from a 3.3-V supply and occupies 3.7 mm/spl deg/.     

卫星应答机用30GHz单片微波集成电路接收机

木文首先介绍了全微波集成电路(MMIC)化接收机的构成,然后讨论了低噪声放大器、宽带相移网络的镜像抑制型混频器、压控振荡器、模拟分频器、倍频器的MMlC电路设计和试验结果,以及利用这些MMIC电路构成镜像抑制型变频器和锁相环型本振,研制全MMIC化接收机的实践.     

Intra-chip wireless interconnect for clock distribution implementedwith integrated antennas, receivers, and transmitters

A wireless interconnect system which transmits and receives RF signals across a chip using integrated antennas, receivers, and transmitters is proposed and demonstrated. The transmitter consists of a voltage-controlled oscillator, an output amplifier, and an antenna, while the receiver consists of an antenna, a low-noise amplifier, a frequency divider, and buffers. Using a 0.18-μm CMOS technology, each of these individual circuits is demonstrated at 15 GHz. Wireless interconnection for clock distribution is then demonstrated in two stages. First, a wireless transmitter with integrated antenna generates and broadcasts a 15-GHz global clock signal across a 5.6-mm test chip, and this signal is detected using receiving antennas. Second, a wireless clock receiver with an integrated antenna detects a 15-GHz global clock signal supplied to an on-chip transmitting antenna located 5.6 mm away from the receiver, and generates a 1.875-GHz local clock signal. This is the first known demonstration of an on-chip clock transmitter with an integrated antenna and the second demonstration of a clock receiver with an integrated antenna, where the receiver's frequency and interconnection distance have approximately been doubled over previous results     

A compact full MMIC module for Ku-band phase-lockedoscillators

A compact Ku-band phase-locked oscillator module has been developed in a full MMIC (monolithic microwave integrated circuit) configuration. The module includes an MMIC voltage-controlled oscillator, an analog frequency divider, and interstage amplifiers. The constituent monolithic chips are integrated in a very small single-package module and operate at the target frequencies without any external trimming or matching network. The oscillator is tuned more than 1 GHz with a constant output amplitude. The frequency-divided output is also obtained over the whole tuning range. Spurious output is not found at any frequency up to 22 GHz. In spite of the very low-Q factor of GaAs monolithic circuitry, the oscillator phase noise exhibited is less than -80 dBc/Hz, due to the high-gain, high-speed phase lock     

A highly integrated dual-band multimode wireless LAN transceiver

A fully integrated radio transceiver chip for the 2.4- and 5-GHz WLAN standards 802.11a/b/g is presented in a 0.25-/spl mu/m 40-GHz BiCMOS technology. The chip integrates the low-noise amplifiers, mixers, channel filters, programmable gain control, synthesizers with voltage-controlled oscillators and reference oscillator, transmitters, antialiasing filters, and voltage regulators. The key performances of the presented transceiver are a receive sensitivity of -85 dBm and -74 dBm for 11-Mb/s complementary code keying (CCK) and 54 Mb/s orthogonal frequency division multiplexing (OFDM) modes, respectively, and an error vector magnitude of -35 dB measured at the transmitter with an output power of -4 dBm at 54-Mb/s 802.11a mode. The transceiver exceeds all IEEE requirements for the 802.11a/b/g CCK and OFDM standards and supports a frequency range of 4.9 to 6 GHz for the future extensions of the 802.11a standard in different countries.     

Development and evaluation of a GaAs MMIC phase-locked loop chipset for space applications

GaAs monolithic microwave integrated circuit (MMIC) chips designed for a phase-locked loop frequency source to be used in space applications have been developed. The chip set includes a three-stage resistive feedback amplifier with 13-dB gain in a 275 MHz to 5.85 GHz bandwidth, a 2.0-GHz voltage-controlled oscillator, a 2.8-GHz digital prescaler, and a VHF/UHF digital phase/frequency discriminator. Both analog and buffered-FET logic digital circuits were fabricated on the same wafer. The MMIC process which was developed for this application comprises molecular beam epitaxial deposition of the active layer, proton isolation, submicron gates, thin film TaN resistor deposition, and silicon nitride passivation. The chip set was used successfully to implement a 2.0 GHz all-GaAs phase-locked loop     

A 60-GHz push-push InGaP HBT VCO with dynamic frequency divider

We present a 60-GHz push-push voltage-controlled oscillator (VCO) with dynamic frequency divider, which is implemented in an InGaP/GaAs heterojunction bipolar transistor technology. A common-base inductive feedback topology is used in the push-push VCO, which generates a pair of 30GHz differential outputs and a single-ended 60GHz push-push output. The 30GHz differential outputs are followed by the proposed dynamic frequency divider. The proposed dynamic frequency divider incorporates active loads with inductive peaking to achieve the higher bandwidth. The maximum operating frequency of the divider was found to be much higher than f/sub T//2 of transistor. To the best of our knowledge, this is the first report demonstrating the extended bandwidth performance of the dynamic frequency divider with active loads and inductive peaking.     

Voltage-controlled oscillators up to 98 GHz in SiGe bipolar technology

In this paper, two fully integrated voltage-controlled oscillators (VCOs) in a 200-GHz f/sub T/ SiGe bipolar technology are presented. The oscillators use on-chip transmission lines at the output for impedance transformation. One oscillator operates up to 98 GHz and achieves a phase noise of -85dBc/Hz at an offset frequency of 1 MHz. It can be tuned from 95.2 to 98.4 GHz and it consumes 12 mA from a single -5-V supply. The second oscillator operates from 80.5 GHz up to 84.8 GHz with a phase noise of -87dBc/Hz at 1-MHz offset frequency. The output power of both circuits is about -6dBm.     

A 5.9-GHz voltage-controlled ring oscillator in 0.18-/spl mu/m CMOS

This paper presents the design of three- and nine-stage voltage-controlled ring oscillators that were fabricated in TSMC 0.18-/spl mu/m CMOS technology with oscillation frequencies up to 5.9 GHz. The circuits use a multiple-pass loop architecture and delay stages with cross-coupled FETs to aid in the switching speed and to improve the noise parameters. Measurements show that the oscillators have linear frequency-voltage characteristics over a wide tuning range, with the three- and nine-stage rings resulting in frequency ranges of 5.16-5.93 GHz and 1.1-1.86 GHz, respectively. The measured phase noise of the nine-stage ring oscillator was -105.5 dBc/Hz at a 1-MHz offset from a 1.81-GHz center frequency, whereas the value for the three-stage ring oscillator was simulated to be -99.5 dBc/Hz at a 1-MHz offset from a 5.79-GHz center frequency.     

Performance-optimized microstrip coupled VCOs for 40-GHz and 43-GHz OC-768 optical transmission

In this paper, we present 40- and 43-GHz voltage-controlled oscillators (VCOs) for use in SONET/SDH optical transmission systems operating at OC-768 rates. SONET system jitter requirements are explained, as are methods for achieving the requisite performance in manufacturable oscillators. We describe in detail a technique for using quadrature-coupled VCOs to achieve a fundamental improvement in jitter power performance. The 40-GHz oscillator has a tuning range of 5 GHz, a single-sideband phase-noise power spectral density of -99 dBc/Hz at 1-MHz offset from the carrier, and consumes 207 mW in the oscillator core. Total power consumption is 363 mW (including biasing and output buffers) from a 3-V supply. The oscillator occupies 0.189 mm/sup 2/ of die area and is implemented in a 120-GHz f/sub T/ SiGe BiCMOS process.     

A high-frequency electronically tunable quadrature oscillator

An architecture composed of mutually regenerative oscillators is introduced. It has been used to design a low-noise high-frequency voltage-controlled oscillator (VCO) capable of producing two output signals in quadrature with essentially identical properties. The phase relation between the quadrature outputs is frequency dependent and extremely stable. A novel way of coupling the regenerative oscillators is suggested in order to improve the frequency stability of the coupled oscillator system. Results obtained from a test chip have verified the viability of the oscillator concept. The oscillator circuit has been realized in a medium-frequency bipolar process. The tuning range extends to 500 MHz. At an oscillation frequency of 200 MHz, measured phase noise was -121 dBc/Hz at 1-MHz distance from the carrier.<>     

Elitist nondominated sorting genetic algorithm based RF IC optimizer

An optimization tool for radio frequency integrated circuits (RFICs) based on an elitist nondominated sorting genetic algorithm is introduced. It casts RF circuit synthesis as a multi-objective optimization problem and produces multiple solutions along the Pareto optimal front. Optimization is followed by sensitivity assessment wherein Monte Carlo simulations are performed for the Pareto points with respect to process, voltage, and temperature variations. The tool is validated in the synthesis of a 5.2-GHz direct-conversion receiver front-end that includes a common-gate differential low-noise amplifier, I/Q down-conversion mixers, and a quadrature voltage-controlled oscillator in a 250-nm SiGe BiCMOS process.     

U-band shield suspended-stripline Gunn DRO and VCO

A millimeter-wave IC dielectric resonator oscillator (DRO) is proposed. Equations that give the resonant frequency of the dielectric resonator DR in suspended stripline (SSL) are derived. A U-band voltage-controlled oscillator (VCO) with varactor tuning also has been developed. The Gunn diode and varactor used in both of the oscillators are commercially available packaged devices. Restrictions on the performance of the oscillators imposed by packaged and mounted networks and the self-characteristics of the solid-state devices have been analyzed. An electronic tuning range greater than 1000 MHz with an output power exceeding 15 dBm across the bandwidth in the 53-GHz region has been realized for the SSL VCO. An SSL DRO with an output power of more than 17 dBm and a mechanical tuning range of 1.5 GHz in the 54-GHz region has been achieved     

A 140-GHz fundamental mode voltage-controlled oscillator in 90-nm CMOS technology

Fundamental mode voltage-controlled oscillators in F-band (90-140GHz) were fabricated using the UMC 90-nm logic CMOS process. The maximum operating frequencies of these three oscillators are 110, 123, and 140GHz, respectively. The 140-GHz voltage controlled oscillator provides -22 to -19-dBm output power, a frequency tuning range of 1.2GHz and phase noise of -85dBc/Hz at 2-MHz offset from the carrier, while consuming 8mA from a 1.2-V supply.