SILK compatibility with the IMD process using copper metallization

This work presents the results of SILK compatibility with the materials used in the damascene structure with copper metallization. Firstly, the thermal stability of the material was carefully evaluated; excellent stability at 450°C was confirmed. Moreover, 450°C is a good curing temperature for obtaining a low dielectric constant (2.7). The conventional PECVD hard masks, SiO₂ (from SiH₄ or TEOS precursors) and Si_xN_y do not affect the SILK properties. Finally, it was verified that an OMCVD TiN barrier is efficient in preventing copper diffusion. It was demonstrated that SILK should reach the performance requested for IMD materials in the damascene structure with Cu metallization.     

Enhancing the reliability of n-p junction diodes using plasma treated tantalum barrier film

The properties of Ta barrier films treated with various plasma nitridations have been investigated by Cu/barrier/Si. An amorphous layer is formed on Ta barrier film after plasma treatments. The thickness of the amorphous layer is about 3 nm. Plasma treated Ta films possess better barrier performance than sputtered Ta and TaN films. It is attributed to the formation of a new amorphous layer on Ta surface after the plasma treatment. Cu/Ta(N,H)/Ta (10 nm)/Si remained stable after annealing at 750 °C. Ta(N,H)/Ta possesses the best thermal stability and excellent electrical properties. Cu/Ta/n⁺-p and Cu/Ta(N,O)/Ta/n⁺-p diodes resulted in large reverse-bias junction leakage current after annealing at 500 °C and 600 °C, respectively. On the other hand, Ta(N,H)/Ta and Ta(N)/Ta diffusion barriers improve the thermal stability of junction diodes to 650 °C. Ta(N,H)/Ta barrier film possesses lowest resistivity among Ta, Ta(N,O)/Ta, and Ta(N)/Ta films. Hydrogen plays an important role in enhancement of barrier properties. It is believed that hydrogen not only induces amorphization on Ta, but also eliminates the oxygen in the film. It is believed that the enhancement of ability against the copper diffusion is due to the combined effects of the hydrogen reaction and nitridation.     

Barrier studies on porous silk semiconductor dielectric

Barrier integrity of Ta-films deposited using the enhanced coverage by re-sputtering (EnCoRe¹) barrier was investigated on untreated surfaces of blanket porous SiLK^{, 2} semiconductor dielectric (developmental version 7, hereinafter v7). Barrier integrity of a bi-layer EnCoRe Ta(N)/Ta film was studied on single damascene lines using v7 and porous SiLK semiconductor dielectric (developmental version 9, hereinafter v9). On blanket wafers more than 30 nm barrier thickness is necessary to achieve complete pore sealing. Analysis of the sheet resistance showed that when tantalum is deposited, a low resistivity -phase is nucleated on the low-k surface. When deposited onto single damascene structures, EnCoRe Ta(N)/Ta is successful in providing a continuous metallic barrier layer over v7 and v9 semiconductor dielectric lines.     

Diffusion barrier integrity and electrical performance of Cu/porous dielectric damascene lines

One issue accompanying the introduction of porous dielectrics in Cu damascene interconnects is the integrity of diffusion barriers. For the first time a direct correlation is shown between the physical integrity of the barrier layer and the electrical performance of damascene lines embedded in a dielectric with a k value of 2.0. The breakdown field at 100/spl deg/C for lines with a porous barrier layer is considerably lower than that for lines with an efficient sealing barrier. Irreversible degradation is also observed in the leakage current of structures with a porous barrier after thermal and electrical stress. Contamination of the porous dielectric can take place already during damascene processing, so the use of a barrier layer that can efficiently seal the pores after dielectric patterning is essential for a proper functioning of future interconnects.     

Reliability studies of barrier layers for Cu/PAE low-k interconnects

Electromigration and electrical breakdown are two of the most important concerns in the reliability of modern electronic devices. The electromigration lifetimes and electrical breakdown field (E_BD) in single damascene copper lines/porous polyarylene ether (PAE) dielectric with different diffusion barrier materials (i.e., amorphous-SiC:H and TaN/Ta) were studied. The results showed a “wafer edge effect” in both groups of samples. The electromigration lifetime of samples taken from the center of the wafer is five to nine times longer of those taken from the wafer edge in the accelerated test. The samples from wafer edge showed a bi-modal failure characteristic. It was also found that electromigration resistance of the structure with new diffusion barrier a-SiC:H/Ta was comparable to that with the conventional TaN/Ta. On the other hand, the electrical testing showed that E_BD of the a-SiC:H/Ta structure is about twice of that with TaN/Ta barrier, indicating a significant improvement of the electrical performance.     

Characteristics of W and Cu/W gate MOS diodes fabricated by a process utilizing LPCVD of W and Cu lift-off

MOS diodes having double layer Cu/W, W, or Al gates were fabricated using tungsten chemical vapor deposition, copper evaporation and lift-off and were characterized before and after thermal anneals. The breakdown field statistics were determined for all kinds of devices, while the high field conduction and charge trapping in the oxide were investigated. The W gate devices exhibited high performance and very low degradation even after annealing at 650 °C. In Cu/W gate diodes good barrier action of our LPCVD tungsten films against copper penetration after annealing at 510 °C was observed, while reduced breakdown integrity and degradation due to copper diffusion occurred after annealing at 650 °C.     

Impact of barrier deposition process on electrical and reliability performance of Cu/CVD low k SiOCH metallization

Integration of Cu with low k dielectrics provided solution to reduce both resistance-capacitance time delay and parasitic capacitance of BEOL interconnections for 130 nm and beyond technology node. The motivation of this work is to study and improve electrical and reliability performance of two-level Cu/CVD low k SiOCH metallization from the results of diffusion barrier deposition schemes. Barrier deposition schemes are (a) high-density-plasma 250 Å Ta; (b) surface treatment of forming gas followed by high-density-plasma 250 Å Ta and (c) bi-layer of 100 Å Ta(N)/150 Å Ta. In this work, we demonstrated the superior and competency of high-density-plasma Ta deposition for Cu/CVD low k metallization and achieved excellent electrical and reliability results. Wafers fabricated with high-density-plasma Ta barrier scheme resulted in the best electrical yields, >90% for testing vehicles of dense via chains (via size=200 nm) and interspersed comb structures (width/space=200 nm/200 nm). Dielectric breakdown strength of the interspersed comb structures obtained at electric field of 0.3 MV/cm was ∼4 MV/cm.     

The performance of GaAs power MESFET’s using backside copper metallization

The performance of GaAs power MESFET’s using backside copper metallization has been evaluated. 10 nm Ta metal was used as the diffusion barrier between GaAs and Cu for copper film metallization in this study. Microstructural characterization shows that the Cu/Ta films with GaAs remained stable up to 400 °C, indicating that Ta is a good diffusion barrier for Cu in GaAs MESFET’s. A copper metallized 6 mm power MESFET was thermal stressed to test the device stability. After annealing at 200 °C for 3 h, the devices showed very little degradation in power performance, and the thermal resistance of the device was 65 °C mm/W with 1.4 W/mm DC input power. Results in this study demonstrate that the feasibility of using Cu/Ta films for the backside metallization of GaAs power devices with stable electrical and thermal characteristics.     

Improving electrical performance of Cu/porous ultra-low k dielectrics single damascene lines

An additional dielectric barrier layer SiCN was deposited on the sidewalls prior to Ta(N) metal barrier deposition. It was found that the leakage decreased with three to four orders of magnitude and breakdown voltage increased 200% compared with that without SiCN layer after burn-in at 200/spl deg/C for 40 h.     

[1 1 1]B-oriented GaAsSb grown by gas source molecular beam epitaxy

We report the GaAsSb bulk layers and GaAsSb/GaAs quantum wells (QWs) grown on (1 1 1)B GaAs substrates by gas source molecular beam epitaxy. We found that Sb composition in the GaAsSb epilayers is very sensitive to the substrate temperature. The composition drops from 0.35 to 0.16 as the substrate temperature increases from 450 to 550 °C. The [1 1 1]B-oriented GaAsSb epilayers show phase separation when the substrate temperature is lower than 525 °C. For a GaAsSb/GaAs multiple quantum wells (MQWs) structure composed of five periods of 5 nm GaAs_0.73Sb_0.27 QW and 30 nm GaAs barrier, the room temperature photoluminescence emission is located at 1255, 80 nm longer than the [1 0 0]-oriented sample with the same Sb composition. The peak wavelength shows significant blue shift as the excitation level increases, which evidences the type-II band alignment in this heterostructure.     

High temperature ohmic contacts to 3C–silicon carbide films

Currently, large-area 3C–SiC films are available from a number of sources and it is imperative that stable high temperature contacts be developed for high power devices on these films. By comparing the existing data in the literature, we demonstrate that the contact behavior on each of the different polytypes of SiC will vary significantly. In particular, we demonstrate this for 6H–SiC and 3C–SiC. The interface slope parameter, S, which is a measure of the Fermi-level pinning in each system varies between 0.4–0.5 on 6H–SiC, while it is 0.6 on 3C–SiC. This implies that the barrier heights of contacts to 3C–SiC will vary more significantly with the choice of metal than for 6H–SiC. Aluminum, nickel and tungsten were deposited on 3C–SiC films and their specific contact resistance measured using the circular TLM method. High temperature measurements (up to 400°C) were performed to determine the behavior of these contacts at operational temperatures. Aluminum was used primarily as a baseline for comparison since it melts at 660°C and cannot be used for very high temperature contacts. The specific contact resistance (ρ_c) for nickel at room temperature was 5×10⁻⁴ Ω cm², but increased with temperature to a value of 1.5×10⁻³ Ω cm² at 400°C. Tungsten had a higher room temperature ρ_c of 2×10⁻³ Ω cm², which remained relatively constant with increasing temperature up to 400°C. This is related to the fact that there is hardly any reaction between tungsten and silicon carbide even up to 900°C, whereas nickel almost completely reacts with SiC by that temperature. Contact resistance measurements were also performed on samples that were annealed at 500°C.     

A study of post-etch wet clean on electrical and reliability performance of Cu/low k interconnections

Integration of Cu with low k dielectrics has gained wide acceptance for 130 nm and beyond technology nodes at back-end-of-line (BEOL) interconnection in order to reduce both the RC delay and parasitic capacitance. Wet clean is one of the critical steps to remove post plasma etch residues. In this paper, the impacts of wet clean process after etching of (a) via, (b) metal 2 trench and (c) Cu cap of dual damascene structure on electrical performance of 130 nm Cu/CVD low k SiOCH metallization were explored and discussed. Electrical yields and dielectric breakdown strength of interconnects from the use of batch spray and single wafer processing systems of wet clean were also compared. We observed that electrical yields of interconnects were considerably dependant on optimized processing conditions (temperature, time, and mega-sonic power) and appropriate wet clean chemistry. The use of fluoride-based mixture of wet clean chemical for all three post-etch clean is very effective in cleaning the via and trench line before Ta barrier/Cu seed deposition. As a result, we successfully integrated double level Cu/CVD low k BEOL interconnection with excellent electrical and reliability performance.     

The effect of Si addition and Ta diffusion barrier on growth and thermal stability of NiSi nanolayer

Formation and thermal stability of nanothickness NiSi layer in Ni(Pt 4 at.%)/Si(1 0 0) and Ni_0.6Si_0.4(Pt 4 at.%)/Si(1 0 0) structures have been investigated using magnetron co-sputtering deposition method. Moreover, to study the effect of Si substrate in formation of NiSi and its thermal stability, we have used Ta diffusion barrier between the Ni_0.6Si_0.4 layer and the Si substrate. Post annealing treatment of the samples was performed in an N₂ environment in a temperature range from 200 to 900 °C for 2 min. The samples were analyzed by four point probe sheet resistance (R_s) measurement, X-ray diffraction (XRD) and atomic force microscopy (AFM) techniques. It was found that the annealing process resulted in an agglomeration of the nanothickness Ni(Pt) layer, and consequently, phase formation of discontinuous NiSi grains at the temperatures greater than 700 °C. Instead, for the Ni_0.6Si_0.4(Pt)/Si structure, 100 °C excess temperature in both NiSi formation and agglomeration indicated that it can be considered as a more thermally stable structure as compared with the Ni(Pt 4 at.%)/Si(1 0 0) structure. XRD, AFM and R_s analyses confirmed formation of a continuous NiSi film with R_s value of 5 Ω/□ in a temperature range of 700−800 °C. Use of Ta diffusion barrier showed that the role of diffusion of Ni atoms into the Si substrate is essential in complete silicidation of a NiSi layer.     

Study on ta diffusion barrier in Al/Si system

The property of Ta as a diffusion barrier is studied for Al/Ta/Si structure. Interfacial reactions of Al(180 nm)/Ta(130 nm)/Si and Al(180 nm)/Ta(24 nm)/Si, in the temperature range 450∼600°C for 30 min, have been investigated. In Al/Ta(130 nm)/Si system, which is Ta-excess case, Al₃Ta is formed at 500°C. At 575°C, TaSi₂ is formed at the interface of Ta Si. At 600°C, after Al₃Ta decomposes at the interface of Al₃Ta TaSi₂, free Ta is bonded to TaSi₂ with the supply of Si from Si substrate and free Al diffuses through TaSi₂, resulting in Al spiking. In Al/Ta(24 nm)/Si system, which is Al-excess case, Al₃Ta is formed at 500°C. At the same temperature of 500°C, after Al₃Ta decomposes at the interface of Al₃Ta/Si, free Ta reacts with Si to form TaSi₂ and free Al diffuses to Si substrate, resulting in Al spiking. The results of interfacial reactions can be understood from the calculated Al-Si-Ta ternary phase diagram. It can be concluded that the reaction at Al/Ta should be suppressed to improve the performance of Ta diffusion barrier in Al/Si system.     

Evaluation of a PECVD advanced barrier (k = 3.7) for 32 nm CMOS technology and below

An advanced dielectric barrier proposed for sub-45 nm CMOS technology nodes is firstly characterized on 300 mm full sheet wafers. The barrier is a bi-layer deposited by PECVD. The copper diffusion barrier property is ensured by a depositing dense initiation layer with the efficiency of a standard SiCN barrier (k = 5.0). The top layer, thicker, with lower density, enables the decrease of the barrier k-value to 3.66 and plays the role of etch stop layer. Combined with a PECVD porous a-SiOC:H dielectric (k-value = 2.5), the advanced dielectric barrier is successfully integrated in a C65 dual damascene architecture reaching a 3% gain in RC. A high via chain resistance yield is evidence of good via opening. Finally, the advanced barrier shows the same electromigration performance than the standard SiCN barrier.     

Temperature effect on gate leakage currents in gate dielectric films of GaAs MOSFET

The gate dielectrics of Ga₂O₃(As₂O₃) of the GaAs MOSFET were prepared by a low-cost and low-temperature liquid-phase chemically enhanced oxidation method. The temperature and oxide thickness dependence of gate dielectric films on GaAs MOSFET have been investigated. The leakage current and dielectric breakdown field were both studied. Both gate leakage current density and breakdown electrical field were found to depend on the oxide thickness and operating temperature. The increasing trend in gate leakage current and the decreasing trend in breakdown electrical field were observed upon reducing oxide thickness from 30 to 12 nm and increasing operating temperature from −50°C to 200°C.     

Normally-off 4H-SiC trench-gate MOSFETs with high mobility

A new 4H-SiC trench-gate MOSFET structure with epitaxial buried channel for accumulation-mode operation, has been designed and fabricated, aiming at improving channel electron mobility. Coupled with improved fabrication processes, the MOSFET structure eliminates the need of high dose N⁺ source implantation. High dose N⁺ implantation requires high-temperature (1550 °C) activation annealing and tends to cause substantial surface roughness, which degrades MOSFET threshold voltage stability and gate oxide reliability. The buried channel is implemented without epitaxial regrowth or accumulation channel implantation. Fabricated MOSFETs subject to ohmic contact rapid thermal annealing at 850 °C for 5 min exhibit a high peak field-effect mobility (μ_FE) of 95 cm²/V s at room temperature (25 °C) and 255 cm²/V s at 200 °C with stable normally-off operation from 25 °C to 200 °C. The dependence of channel mobility and threshold voltage on the buried channel depth is investigated and the optimum range of channel depth is reported.     

Texture and strain in narrow copper damascene interconnect lines: An X-ray diffraction analysis

The behaviour of submicron damascene copper lines raises a number of fundamental issues such as grain growth in narrow trenches, thermomechanical properties of copper in these confined geometries, etc. This experimental study is aimed at evaluating the influence of annealing, polishing and line width on the room temperature strain and texture of narrow copper damascene lines. X-ray diffraction has been performed on arrays of lines with widths ranging between 3 μm and 0.09 μm. Two annealing conditions (150 °C and 400 °C) have been used either prior or after Chemical Mechanical Polishing (CMP). A clear influence of the Cu overburden on the in-line microstructure is evidenced. X-ray diffraction analysis shows that strains in line longitudinal direction are higher in those annealed at 400 °C and decrease with the width of the lines.Effect of CMP on structure and relationship between both texture and strain and temperature of thermal treatments is discussed in light of these observations.     

高温氧化对SiC MOS器件栅氧可靠性的影响

SiC金属氧化物半导体(MOS)器件中SiO2栅氧化层的可靠性直接影响器件的功能.为了开发高可靠性的栅氧化层,将n型4H-SiC (0001)外延片分别在1 200,1 250,1 350,1 450和1 550℃5种温度下进行高温干氧氧化实验来制备SiO2栅氧化层.在室温下,对SiC MOS电容样品的栅氧化层进行零时击穿(TZDB)和与时间有关的击穿(TDDB)测试,并对不同干氧氧化温度处理下的栅氧化层样品分别进行了可靠性分析.结果发现,在1 250℃下进行高温干氧氧化时所得的击穿场强和击穿电荷最大,分别为11.21 MV/cm和5.5×10-4 C/cm2,势垒高度(2.43 eV)最接近理论值.当温度高于1 250℃时生成的SiO2栅氧化层的可靠性随之降低.     

Effects of material interfaces in Cu/low-/spl kappa/ damascene interconnects on their performance and reliability

The performance and reliability of Cu/Low-/spl kappa/ damascene interconnects are investigated from the view point of the material interface structure. We are focusing especially on the heterointerfaces between the Cu and the barrier metal (BM), as well as between the hard mask (HM) and the capping barrier dielectrics (CAP) covered on the Cu interconnects. It is found that the highest via reliabilities of electromigration (EM) and thermal cycle are established by the barrier-metal-free (BMF) structure without the heterointerface between the Cu and the BM due to the strong Cu-to-Cu connection at the via bottom. The interline time-dependant dielectric breakdown lifetime is improved mostly by using a HM with the same materials as the CAP layer, referred to as an unified structure, which diminishes the heterointerface between the HM and the CAP. These ideal structures without the material heterointerfaces derive the highest reliability and performance. Structural control of the material heterointerfaces in the actual Cu/low-/spl kappa/ damascene interconnect is crucial for the high reliability and performance.