On the performance of an ATM switch with multichannel transmissiongroups

A routing architecture applying the concept of multichannel transmission groups (MCTGs) for ATM systems is proposed. A queuing analysis of an internally nonblocking ATM switch employing this MCTG concept with partially shared output buffers is presented. The analysis is based on the discrete-time DA///D/c /B queuing model. Both bulk input traffic bulk-size distribution (A) and deterministic traffic (D₁ +. . .+D_N) are considered. The impact of switch speedup on the performance is also taken into account. It is shown that the MCTG architecture yields better performance in terms of delay and cell loss probability than its single channel counterpart. It is also found that the switch speedup required to closely approximate the optimal performance obtained by having the switch fabric run N times as fast as the input and output channels, where N is the size of the switch, is rather small compared to N. This makes the practical realization of the proposed switch architecture feasible     

ATM接入交换机上行链路性能的仿真研究

本文介绍了一种以太网ＡＴＭ接入交换机的设计方案,并对其上行链路的性能进行了计算机仿真研究,重点研究了负荷与信元丢失率及负荷与队列时延等的关系。针对以太网分组的特点,我们采用了Ｂａｔｃｈ模型进行实际的仿真。利用该仿真结果指导了一种具体交换机的设计。     

8端口ATM工作组交换机设计与性能分析

本文概述了基于FPGA的8端口155Mbit/s(25Mbit/s)ATM工作组交换机的设计,对其关键部分如输入输出端口处理,交换结构等进行了阐述,并对其性能进行了分析,试验运行表明各项指标均满足设计要求。     

A control-ahead ATM switch architecture and its performance

An asynchronous transfer mode (ATM) switch architecture that uses the broadcasting transmission medium for transmission of cells from input ports to output ports is introduced. Cell transmission and its control are separated completely, and cell transmission control, i.e. header operation, is executed before cell transmission (control ahead). With this operation, cell transmission and its control can be executed in a pipeline style, allowing high-speed cell exchange and making transmission control easier. One of the essential problems for ATM switches which use the broadcasting transmission medium is high-speed operation of the transmission medium. The switch fabric performance is analyzed according to its switching speed. Numerical results show that the ATM switch proposed shows good cell loss performance even when its switching speed is restricted, provided that switch utilization is below 1. Extensions to the switch that lead to robustness against bursty traffic are shown     

Buffer sizing in an ATM switch for both ATM and STM traffics

Specific queueing models are derived in order to size the buffers of ATM switching elements in the cases of ATM or STM multiplexed traffic. Buffering is performed either at the outputs or in a central memory for ATM multiplexed traffic; for STM multiplexed traffic, buffers can also be provided at the inputs. The buffer size is chosen in order to ensure a loss probability in the switch smaller than 10^?10. It is shown that the buffer size per output in the case of central queueing is smaller than the buffer size in case of output queueing for both ATM and STM multiplexed traffics. Moreover, for STM multiplexed traffic, buffer sizes are identical for input and output queueing. Lastly, it is pointed out that buffers used for STM multiplexed traffic should be 4 to 20 times larger than the corresponding buffers for ATM multiplexed traffic.     

Design of an ATM switch for handoff support

In a wireless ATM system, a network must provide seamless services to mobile users. To support this, mobility function should be added to existing ATM networks. Through a handoff operation, a mobile user can receive a service from the network without disconnecting the communication. A handoff results in connection path rerouting during an active connection. To avoid cell loss during a handoff, cell buffering and rerouting are required in the network. A handoff switch is a connection breakdown point on an original connection path in the network from which a new connection sub‐path is established. It performs cell buffering and rerouting during a handoff. Cell buffering and rerouting can introduce a cell out‐of‐sequence problem. In this paper we propose a handoff switch architecture with a shared memory. The architecture performs cell buffering and rerouting efficiently by managing logical queues of virtual connections in the shared memory and sorting head‐of‐line cells for transmission, thus achieving in‐sequence cell delivery during a handoff. We also present simulation results to understand the impacts of handoffs on switch performance. This revised version was published online in July 2006 with corrections to the Cover Date.     

Design and evaluation of a high-performance ATM firewall switch andits applications

We present the design of a value-added ATM switch that is capable of performing packet-level (IP) filtering at the maximum throughput of 2.88 Gbit/s per port. This firewall switch nicely integrates the IP level security mechanisms into the hardware components of an ATM switch so that most of the filtering operations are performed in parallel with the normal cell processing, and most of its cost is absorbed into the base cost of the switch. The firewall switch employs the concept of “last cell hostage” (LCH) to avoid or reduce the latency caused by filtering. We analyze in detail the performance of the firewall switch in terms of the throughput and the latency and address related design issues. Applications of our firewall switch as Internet and intranet security solutions are also discussed     

Performance evaluation of a high-speed ATM switch with multiplecommon memories

We consider a common-memory (CM) type N × N ATM switch, where CM block consists of K (K ⩾ N) separated submemories. We propose an address assignment algorithm to avoid input/output contentions so that we can have the read/write speed of submemories as low as the interface (input/output) port speed. Taking a replication-at-sending approach to multicast, we pursue memory efficiency and maximum throughput. We develop an analytical model to evaluate the system in terms of cell loss ratio and average delay time. In the analysis, we take into account two loss factors causing losses of incoming cells: (1) the failure of scheduling to avoid the input/output contentions and (2) overflow in the CM block. The first factor is dominating and can be significantly reduced by increasing K. From our analytical results compared with simulations, it is observed that we can take K ≈ 3N as a guide of system design     

Traffic performance evaluation of an optical packet switch with multicast operation

We recently proposed a multicast-enabled optical packet switch architecture utilizing multicast modules. In this paper, we evaluate the traffic performance of our earlier proposed packet switch under a hybrid traffic model through simulations. The multicast packets are given higher priority than unicast packets so that only a small number of multicast modules are needed. The results show that the switch can achieve an acceptable packet loss probability in conjunction with a packet scheduling technique.     

Design of multicast ATM switch

The proposed ATM switch has very high throughput under heavy-traffic conditions. The cell blocking scenario described in the comment [see ibid., vol. 35, no 5, 1999] is of no importance. Directly after the switch is reset, the first four cells will not be placed in the same RAM with the help of the cell-in stage. Under heavy-traffic conditions, the number of cells in each RAM is well balanced and no blocking effect would occur for unicast traffic. That scenario would only arise at the end of transmission when no more cells would be entering the switch. However, the probability of that scenario ocurring is extremely low. Therefore, an internal memory speedup would not be needed and the throughput would not be degraded. The proposed dynamic multicast scheme can fully utilise the available bandwidth     

Design of multicast ATM switch

The architecture of a shared multibuffer ATM switch that uses the cyclic address queue method is described. No memory speedup is required. The blocking effect is eliminated for unicast traffic. Multicast functions are efficiently carried out via a multicast queue. A dynamic scheme is used to improve the unfairness problem     

The design and analysis of an ATM multicast switch with adaptivetraffic controller

The paper describes several improvements to a nonblocking copy network proposed previously for multicast packet switching. The improvements provide a complete solution to some system problems inherent in multicasting. The input fairness problem caused by overflow is solved by a cyclic running adder network (CRAN), which can calculate running sums of copy requests starting from any input port. The starting point can change adaptively in every time slot based on the overflow condition of the previous time slot. The CRAN also serves as a multicast traffic controller to regulate the overall copy requests. The throughput of a multicast switch can be improved substantially if partial service of copy request is implemented when overflow occurs. Call-splitting can also be implemented by the CRAN in a straightforward manner. Nonuniform distribution of replicated packets at outputs of the copy network may affect the performance of the following routing network. This output fairness problem due to underflow is solved by cyclically shifting the copy packets in every time slot. An approximate queueing model is developed to analyze the performance of this improved copy network. It shows that if the loading on each output of the copy network is maintained below 80%, the average packet delay in an input buffer would be less than two time slots     

Measurement-based evaluation of operating system fault tolerance

The authors demonstrate a methodology for evaluating the fault-tolerance characteristics of operational software and illustrate it through case studies of three operating systems: the Tandem GUARDIAN fault-tolerant system, the VAX/VMS distributed system, and the IBM/MVS system. Based on measurements from these systems, software error characteristics are investigated by analyzing error distributions and correlation. Two levels of models are developed to analyze the error and recovery processes inside an operating system and the interactions among multiple copies of an operating system running in a distributed environment. Reward analysis is used to evaluate the loss of service due to software errors and the effect of fault-tolerant techniques implemented in the systems     

Reliability analysis of an optical ATM switch based on wavelength routing

Reliability studies of a demonstrated asynchronous transfer mode (ATM) switch with all-optical packet routing are presented. Calculations are based on available reliability data for commercial components. An additional inherent redundancy is shown to improve switch availability. Our calculation results further show that a proposed multiplane switch satisfies the general reliability requirement for switching systems.     

Performance of an input-queued ATM switch with even/odd switchingplanes

A switch architecture is proposed for alleviating the HOL blocking by employing even/odd dual FIFO queues at each input and even/odd dual switching planes dedicated to each even/odd queue. Under random traffic, it gives 76.4% throughput without output expansion and 100% with output expansion r=2, with the same amount of crosspoints as for the ordinary output expansion scheme     

Scalable performance evaluation of a hybrid optical switch

This paper provides new loss models for a hybrid optical switch (HOS) combining optical circuit switching (OCS) and optical burst switching (OBS). Exact blocking probabilities are computed when 1) no priority is given to either circuits or bursts and 2) circuits are given preemptive priority over bursts. Because it is difficult to exactly compute in realistic scenarios, computationally scalable approximations are derived for the blocking probability. The sensitivity of the analytical results to burst length and circuit holding-time distributions is quantified by simulation. It is demonstrated how the proposed approximations can be used for multiplexing-gain evaluation of a hybrid switch. In addition, the extension of the proposed single-node model to a network model composed of OCS, OBS, and hybrid switches is outlined.     

Dimensioning an ATM switch based on a three-stage Clos interconnection network

ATM (asynchronous transfer mode) is a new technique for transmitting voice, data and video. The performance of atm networks will depend on switch structure. Performance analysis of an atm switch based on a three-stage Clos network is presented. In this paper two types of switches are studied: a switch with input queues in the switching elements and a switch with output queues. This study is at the cell level and intends to dimension the switch. First, the traffic is supposed to be uniform, cells arrive on each input according to a geometric arrival process, they are uniformly directed over all the network outputs. An analytic model is proposed for both input and output queues in the switching elements. A study of the saturation throughput is proposed for input buffer switching elements. This work proves the influence of buffer dimensioning on the different stages of the switch. Dissymmetric switching elements are shown to be better than symmetric ones. A model is then designed for nonuniform traffic patterns and output buffers. Two types of non-uniform traffic are presented: single source to single destination (sssd) and multi-hot spots traffic (mhs). Discrete event simulations are used to validate the different models.     

Buffer dimensioning of ATM25 switch

ATM25 is a 25.6 Mbit/s ATM specification approved by the ATM Forum. The authors present a queueing solution for dimensioning the buffer cell loss requirement of an ATM25 switch which was implemented using field programmable gate arrays     

Design and performance of Multinet switch: a multistage ATM switcharchitecture with partially shared buffers

A new ATM switch architecture is presented. Our proposed Multinet switch is a self-routing multistage switch with partially shared internal buffers capable of achieving 100% throughput under uniform traffic. Although it provides incoming ATM cells with multiple paths, the cell sequence is maintained throughout the switch fabric thus eliminating the out-of-order cell sequence problem. Cells contending for the same output addresses are buffered internally according to a partially shared queueing discipline. In a partially shared queueing scheme, buffers are partially shared to accommodate bursty traffic and to limit the performance degradation that may occur in a completely shared system where a small number of calls may hog the entire buffer space unfairly. Although the hardware complexity in terms of number of crosspoints is similar to that of input queueing switches, the Multinet switch has throughput and delay performance similar to output queueing switches     

Maximum throughput of an input queueing packet switch with twopriority classes

The maximum throughput of an N×N nonblocking packet switch with input queues and two priority classes is analyzed. Packets are of fixed length and the switch operation is slotted. Packets of both priority classes are queued when waiting for service. High-priority packets preempt low-priority ones and move ahead of all low-priority packets waiting in the queue. A new method of analysis is employed. The calculated results of the maximum throughput obtained are close to the simulation results