A high-speed digital filter LSI for video signal processing

A ninth-order symmetrical filter has been developed for use in two-dimensional (2-D) processing in TV video systems, especially in high-definition TV receivers. A 2-D filter that is composed of only two types of LSIs (one-dimensional (1-D) digital filter LSI and delay-line) is discussed. The architecture of the digital filter LSI and circuit techniques are presented to obtain high-speed operation, to save chip area, and to decrease power consumption. The order and the transfer function of the filter can be altered by means of the external terminals. The chip, achieved through 2-/spl mu/m CMOS technology, contains about 52000 transistors and occupies an area of 50 mm/SUP 2/. It operates at a high clock frequency of over 33 MHz, and dissipates only 600 mW of power.     

Digital signal processing for video

Applications of the digital signal processing of video signals in broadcasting, communication, and consumer electronics are reviewed. These include: digital encoding systems, digital video effect equipment, and the television standards converter for broadcasting; videoconferencing and video telephone equipment; and TV receivers, including those for extended definition and high-definition television (EDTV and HDTV). Performance requirements for video signal processing (VSP) are discussed, and an example of a video signal processor comprising a parallel processor system composed of multiple VSP modules is examined. Future trends in VSP are predicted     

A single-chip storage LSI for home networks

Network direct attached storage (NDAS) is a network storage architecture that allows direct attachment of existing ATA/ATAPI devices to Ethernet without a separate server. Unlike other architectures such as NAS, SAN, and USB mass storage, no server computer intervenes between the storage and the client hosts. We describe an NDAS disk controller (NDC) amenable to low-cost single-chip implementation that processes a simplified L3/L4 protocol and converts commands between ATA/ATAPI and Ethernet, while the remaining complex tasks are performed by remote hosts. Unlike NAS architectures that use TCP/IP, NDAS uses a TCP-like lean protocol that lends itself well to high-performance hardware realization. Thanks to the simple NDAS architecture and protocol, an NDC implemented on a single 4 mm /spl times/ 4 mm chip in 0.18 /spl mu/m CMOS technology achieves a maximum throughput of 55 Mbytes/s on gigabit Ethernet, which is comparable to that of a high-performance disk locally attached to a host computer.     

Digital signal processing for video applications

Digital video signal processing is one result of the fast progress in NMOS-VLSI techniques. The attractions of using digital data processing methods in an analog application field are the availability of CAD tools for the design of digital ICs and the integration of digital filter functions. Besides the key components such as microcomputers, A/D, and D/A converters, the digital filter techniques are the most important functions in this application field. It is demonstrated that digital signal processing is not only restricted to amplitude modulated video signals, but also that frequency modulated signals can be processed and methods for FM modulation and demodulation have been developed.     

A single-chip NMOS analog front-end LSI for modems

Presents a fully integrated analog front-end LSI chip which is an interface system between digital signal processors and existing analog telecommunication networks. The developed analog LSI chip includes many high level function blocks such as A/D and D/A converters with 11 bit resolution, various kinds of SCFs, an AGC circuit, an external control level adjuster, a carrier detector, and a zero crossing detector. Design techniques employed are mainly directed toward circuit size reductions. The LSI chip is fabricated in a 5 /spl mu/m line double polysilicon gate NMOS process. Chip size is 7.14/spl times/6.51 mm. The circuit operates on /spl plusmn/5 V power supplies. Typical power consumption is 270 mW. By using this analog front-end LSI chip and a digital signal processor, modern systems can be successfully constructed in a compact size.     

A single-board video signal processor module employing newlydeveloped LSI devices

A single-board 14.3-MOPS (million operations per second) video signal processor module (VSPM) has been developed. The module is fully microprogrammable and processes up to a 128 pel×128 pel subimage every 16.7 ms. Using a number of homogeneous VSPMs aligned in parallel, a real-time video signal processing environment is provided on the basis of an overlap-save or overlap-add technique. An experimental system has been constructed in order to demonstrate the signal processor approach's effectiveness for video signals by implementing picture coding algorithms. Due to software control capability, various kinds of picture coding techniques can be evaluated by the system     

Vlsi programmable digital filter for video signal processing

High speed digital filtering is required in real time video signal processing, as well as high order filters are needed to match television studio signal quality. The hardware complexity involved by such system constraints may be faced by a two-fold approach, concerning both the architecture and the technological aspects of a specific electronics device devoted to the above task.This article deals with a processor especially developed for the purpose of fast digital video signal applications, such as filtering, equalization, interpolation and so on. The nonrecursive transposed F.I.R. (Finite Impulse Response) structure has been selected, which exhibits a linear phase behavior. A novel approach has been developed for the multipliers implementation, by optimizing an EPROM based look-up table storing the products between all video samples and the filter coefficients significant bits, resulting in a programmable system.TheProgrammable Filter Processor has been designed with a high level of parallelism and pipelining and a 1.2 µm CMOS EPROM, single metal technology has been employed for the integration process of the chip. This has been successfully production-tested for 40 Msamples/s throughput rate, thus both allowing to meet most video filtering applications and demonstrating the potentialities of nonvolatile memory technologies in embedded applications.Moreover multiple devices can be interconnected to yield multiprocessor structures for more demanding performances such as, cascaded or longer filters, input signal precision extension, computation improved accuracy, increased throughput rate, and two-dimensional signal processing.Work carried out in the framework of the agreement between the Italian P.T. Administration and the Fondazione UGO BORDONI.     

Switched-current signal processing for video frequencies and beyond

Switched-current (SI) signal processing circuits with video frequency performance are presented. The delay cells employ negative feedback to produce a `virtual earth' at the input node to improve transmission accuracy. Fully differential structures with common-mode feedback are used to reduce charge injection errors and crosstalk from digital signals. An IC test circuit, in a 1 μm standard digital CMOS process, containing simple delay lines and an FIR filter section is described, and measured performance is given. Typically, a 2T delay line sampling at 13.3 MHz gave a low-frequency gain error of -54 dB, a settling error of -60 dB, a third-harmonic distortion of -40 dB with 75% modulation, and an S/N ratio of 60 dB. Scaling of the memory cell device dimensions and currents should permit SI operation at clock frequencies beyond 100 MHz     

一种适合模拟与视频信号处理的高速IC工艺

Zetex 公司(位于纽约州的Hauppauge)推出了一种新的制造高速双极型模拟集成电路的新工艺技术,并且正用它来生产音响与视频信号处理集成电路产品。这种命名为ZA工艺的生产工艺,是0.6微米、两层金属层的工艺技术。它采用氧化物隔离技术,可以降低线     

A single-chip frequency-shift keyed modem implemented using digital signal processing

A single-chip modem that uses digital signal processing (DSP) to perform the modem functions is described. The DSP modem is a complete single-chip modem which handles all of the popular international standards for frequency-shift keyed modems. These specifications include the Bell 103 and 202 specifications for North America, and the CCITT V.21 and V.23 specifications in Europe. The authors describe modem system aspects, the architecture and philosophy underlying the design of this modem, and some of the special features that are incorporated into the modem through the use of digital signal processing.     

A single-chip 16-bit 25-ns real-time video/image signal processor

A single-chip 16-b microprogrammable real-time video/image signal processor (VISP) has been developed for use in real-time motion picture encoding during low-bit-rate transmission for TV conference systems. In addition to stand-alone microprocessor functional units, the VISP integrates a high-speed variable seven-stage pipeline arithmetic circuit for video/image data processing and various controllers for easy I/O (input/output) and multiple-chip connections A 25-ns instruction cycle time is attained by using complementary reduced-swing CMOS logic circuits. The chip (14 mm×13.4 mm) was fabricated using a double-metal-layer 1.2-μm CMOS process technology and contains 220000 transistors     

Error analysis of DPCM video signal processing

An error analysis of the 2D FIR digital filters realisation using DPCM video signal processing is outlined. Quantisation errors due to coding and finite word length are studied. Simulation results demonstrating the coherence between the theoretical and the experimental results are presented. The main conclusion that can be drawn from the theoretical and empirical results is that there is a minimum value of the filter coefficients' word length after which no improvement in the signal-to-noise ratio (SNR) is possible. However, subjective tests have shown that images obtained using the DPCM realisation with this minimum word length have similar visual quality as that obtained using conventional filters with infinite precision.<>     

A single-chip video ghost canceller

A 450 K-transistor video ghost canceller chip, which implements a flexibly configurable IIR and FIR filter, is described. A very compact digital filter tap operating at a pixel rate of 14.32 MHz (4×F _sc) allows 180 programmable taps to be implemented in a die area of 56.25 mm² in a 1 μm TLM CMOS process. The device operates with 3.3- or 5-V power supplies     

A single-chip adaptive DPCM video codec

A differential pulse-code modulation (DPCM) video codec with two-dimensional intrafield prediction and adaptive quantizer is presented. An approach for the arithmetic implementation of the DPCM structure and the design of a test chip, fabricated in a 1.5 μm CMOS technology, is described. This is the first VLSI realization of a DPCM codec with adaptive quantizer. For the test chip transmitter or receiver mode, application as part of a three-dimensional interframe codec and processing of luminance or chrominance signals are optional. A line buffer and ten different quantizer characteristics are realized on-chip. Correct operation has been verified up to 26 MHz     

100-Mbit/s single-chip Q-VLMS MLSE equalizer LSI for TDMA mobileradio communications

A single-chip 100-Mbit/s burst-operation two-tap maximum likelihood sequence estimation (MLSE) equalizer LSI for QPSK signals is introduced. It also supports two-branch diversity combining. Three new techniques are used to realize this fast equalizer LSI: the quantized variable-gain least mean squares (VLMS) algorithm, which has small processing delay with fast convergence characteristics; a simple complex-valued multiplication scheme based on inverting the sign and switching the in-phase and quadrature-phase components; and a parallel structure to minimize the processing delay of path memory. The chip, containing 75 kgates, is manufactured using the 0.45-μm-CMOS gate array process. The supply voltage is 3.3 V. This LSI offers higher processing speed than any other conventional equalizer chip for mobile radio communications     

一种CCD相机的视频处理电路设计与噪声分析

为使CCD相机系统能够捕获到高信噪比的图像,介绍了一种视频处理器TDA9965的应用电路设计,简述了其内部组成框图及工作原理。利用某型号TDI CCD作为系统传感器,成功实现了对CCD输出模拟视频信号的量化处理,能够使相机系统完成实时采集图像等任务。同时分析了视频处理器电路设计对相机系统图像信噪比的影响,以电源噪声为干扰源,具体计算了在电路设计不合理和改进设计后两种情况下,CCD相机图像信噪比的变化,并通过试验测试验证,合理的电路设计可以使图像的信噪比提高20 dB以上,从而说明了视频处理电路合理设计的重要性,为高速高信噪比CCD相机的研制提供了技术基础。     

压缩域内的视频图像处理算法

介绍了一些在压缩域内处理已压缩视频流的算法，主要关注如何对DCT系数直接进行处理的算法，对于带有运动估计的压缩系统(如MPEG视频压缩码)介绍了一些解码算法及相应压缩域内的重构操作，这些算法也应用于视频转码。     

Parallel video signal processor configuration based on overlap-save technique and its LSI processor element: VISP

A parallel signal processor architecture has been developed for real time motion picture encoding. The architecture is based on spatial parallelism utilization in a picture signal. Plural element processors handle subregional pictures simultaneously without communicating with other element processors. However, due to an overlapsave technique where every sub-picture input area is chosen to be wider than the output area, element processors can carry out continuous processing over an entire picture. In order to increase motion picture processing efficiency as well as system implementation simplicity, a specific element processor LSI chip, composed of a pipeline arithmetic unit, two dimensional address generators, a raster scan signal handler, and a sequence controller, has been developed by using more than 220,000 transistors. The developed parallel processor is shown to be applicable to a software programmable low bit rate TV codec.     

LSI processing technology for planar GaAs integrated circuits

A planar GaAs integrated circuit (IC) fabrication technology capable of LSI complexity has been developed. The circuit and fabrication approaches were chosen to satisfy LSI requirements for high yield, high density, and low power. This technology utilizes Schottky-diode FET logic (SDFL) incorporating both high-speed switching diodes and 1-µ m GaAs MESFET's. Circuits are fabricated directly on semi-insulating GaAs using multiple localized implantations. Rapid progress in the development of this technology has already led to the successful demonstration of high-speed (tau_{d} sim 100ps) low-power (∼500 µW/gate) GaAs MSI (∼60-100 gates) circuits. Extension of the current MSI technology to the LSI/VLSI domain will depend critically on device yield which will be dictated by the GaAs material properties and by the fabrication processes used. The purpose of this paper is to describe a GaAs IC process technology which combines advanced planar device and multilevel interconnect structures with several LSI compatible processes including multiple localized ion implantations, reduction photolithography, plasma etching, reactive ion etching, and ion milling.