CMOS video filters using switched capacitor 14 MHz circuits

In order to realize self-contained analog video LSI, video band switched-capacitor (C) filters, including a two-dimensional filter, have been experimentally fabricated. By using 2-/spl mu/m/spl middot/CMOS technology and high-speed/high-precision circuits, an LSI clock rate of 14 MHz, signal swing of 2 V p-p with a single 5-V supply, random noise S/N of 60-70 dB p-p/r.m.s at LSI output, and power dissipation of less than 5 mW per amplifier have been achieved. Single-stage cascode amplifiers are extensively used to attain video band speed. Neutralization is introduced into fully differential filters to improve their frequency response.     

High-Speed Digital Switching Technology Using Space-Division-Switch LSI's

NTT is planning a high-speed broad-band switching network that offers high-speed digital and 4 MHz video services. This paper discusses the hardware design of the high-speed space-division digital switching network and requirements for a switch LSI. In addition, the design and measured performance of a 32 × 32 CMOS space-division-switch LSI are described. In this network, video signals are converted into 32 Mbit/s digital signals by band-compression technology. In order to switch such digital signals, space-division switches are more advantageous than time-division switches. This is because time-division switches cannot multiplex many channels at that bit rate. Furthermore, the use of the space-division-switch LSI is the most effective way to miniaturize the switching system.     

A microprogrammable real-time video signal processor (VSP) formotion compensation

A video signal processor (VSP) LSI circuit with a three pipelined architecture has been developed for pattern matching, which is fundamental for the motion compensation necessary for teleconferencing systems. A high-speed arithmetic logic unit with absolute-value calculation capability and a minimum/maximum value detector, which are essential to pattern matching, have been integrated on the VSP LSI. The chip was fabricated with a 2.5-μm CMOS and double-layer metallization technology. The number of MOSFETs integrated on the 9.91×9.50-mm ² chip is about 48000. It operates at a 14.3-MHz clock frequency with a single 5-V power supply and typically consumes 240 mW. An experimental video signal processing system, using a single VSP LSI chip, is discussed     

A 2Gb/s throughput GaAs digital time switch LSI using LSCFL

A GaAs four-channel digital time switch LSI with a 2.0-Gb/s throughput is developed. This switch consists of 4-bit shift registers, data latches, a counter, a control unit, and I/O buffer gates. The LSI includes 1176 devices (FET's, diodes, and resistors) and its equivalent gate number is 231 gates. Low Power Source Coupled FET Logic (LSCFL) operating in a true/complementary mode is used to ensure high-speed and low-power performance. MESFET's with 0.55-µm gate length are fabricated by the buried p-layer SAINT process, which satisfactorily suppresses short channel effects. Dislocation-free wafers are also used to provide high chip yields of 75 percent. The propagation delay time of the LSCFL basic circuit is 48 ps/gate with 1.4-mW/equivalent gate. The total power dissipation including input and output buffers is 0.64 W. The LSI speed performance is evaluated by measuring toggle frequency of the 1/4 frequency divider. The divider operates typically at 5.1 GHz, maximum 7.5 GHz. The newly developed high-speed digital time switch LSI makes possible time division switching services in TV and high-definition TV transmission systems.     

BiCMOS circuit technology for a 704 MHz ATM switch LSI

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W     

A 200-MHz 16-bit super high-speed signal processor (SSSP) LSI

A 200-MHz 16-b BiCMOS super high-speed signal processing (SSSP) circuit has been developed for high-speed digital signal processor (DSP) LSIs. In order to produce extremely fast LSI circuits, several novel techniques have been combined for integration of the SSSP. They include a redundant binary convolver architecture, a double-stage pipelined convolver architecture, and submicrometer BiCMOS drivers with large capacitive load drivability. The SSSP performs 200-MHz addition. The chip, which was fabricated with 0.8-μm BiCMOS and triple-layer metallization technology, has an area of 5.87 mm×5.74 mm and contains 20150 transistors. It operates at a clock frequency of 200 MHz with a single 5-V power supply and typically consumes 800 mW     

An ultralow power CMOS/SIMOX programmable counter LSI

We designed and fabricated an extremely low-power CMOS/SIMOX programmable counter large scale integrated circuits (LSI) for high-speed phase-locked loop (PLL) frequency synthesizer applications. This was to verify the potential usefulness of ultrathin-film 0.24-μm-gate CMOS/SIMOX process technology for creating an extremely low-power LSI containing high-speed circuits operating at frequencies of at least 1 GHz and at low supply voltages. While operating at up to 2.2 GHz and consuming only 4.5 mW at 1.5 V, it is capable of 4-GHz performance with power consumption of 19 mW at 2.5 V. Even at a low supply voltage of 1.5 V, high input-sensitivity was also achieved in the 1- to 2-GHz frequency range. These low-power and high input-sensitivity characteristics outperform those of state-of-the-art BiCMOS PLL LSIs     

A video codec LSI for high-definition TV systems withone-transistor DRAM line memories

A video codec LSI for high-definition television (HDTV) systems has been developed. By using a time-compressed integration encoding technique, it converts a 20.0-MHz bandwidth luminance signal and two 5.0-MHz chrominance signals into a compressed image signal at 48.6-MHz sampling frequency. It is useful in many HDTV application systems, such as 400-Mb/s digital transmission system, a video disk player system, or an analog transmission system. Over 288000 elements, including a 52-kb one-transistor DRAM (dynamic random access memory) line memory specially developed for this LSI, were integrated on a 12.16×12.10-mm² chip. A standard cell layout method and a 1.2-μm CMOS logic LSI process were used     

A 1.8 Gb/s GaAs optoelectronic universal switch LSI withmonolithically integrated photodetector and laser driver

A high-speed monolithic optical interface switch LSI is developed using a GaAs MSM photodetector and large-scale integrated electric circuits. This LSI operates universally as a 1.8 Gb/s optical-input/optical-output four-channel time-division switch, a 1.8 Gb/s optical-input/electrical-output 1:4 demultiplexer, a 2.0 Gb/s electrical-output 4:1 multiplexer, and a 2.8 Gb/s electrical-input/electrical-output 4×4 space-division switch. It uses a new multistage 2×2 switch block with small hardware and high-speed operation. It can be expanded to a 16×16 optical-input/optical-output time-division switch operating at up to 1.8 Gb/s for broadband-ISDN     

High-Speed Time Switch Using GaAs LSI Technology

A high-speed time switch using GaAs LSI technology is discussed. A new high-speed time switch structure consisting primarily of shift registers is proposed. This structure requires relatively minimal hardware in designing LSI. As the first stage of study, a GaAs 4-channel time switch LSI is manufactured using this structure. Switching speed of the LSI is 2 Gbits/s and the power consumption 0.64 W/chip. Largecapacity switch configurations using this time switch are proposed. This high-speed time switch makes possible the time-division switching of such services as T.V. and high-definition T.V.     

Deep-submicron HEMT technology

The current status of HEMT technology and its impact on computers and communications are presented, focusing on the advantages of the device in the deep-submicrometre dimensional range, self-aligned HEMT processing, and the HEMT LSI implemented in supercomputer and communication systems.

Ultra-low-noise HEMTs are already commercially available in satellite communications, and have made a great impact in expanding the broadcasting satellite market. For ultra-high-speed digital LSI applications the 1 k gate bus-driver logic LSI has been developed to demonstrate high-speed data transfer in a high-speed parallel processing supercomputer system at room temperature, operating at 10·92 Gflops. The 7 k gate asynchronous transfer mode (ATM) switch LSI has alsi been developed to evaluate high-speed data switching for Broadband Integrated Service Digital Network (B-ISDN). The maximum operation frequency was 1·2 GHz at room temperature. The single-chip throughput was 9·6 Gb/s and a throughput of 38·4 Gb/s was achieved in a 4 × 4 ATM switching module.     

A 0.8-μm BiCMOS ATM switch on an 800 Mb/s asynchronous bufferedbanyan network

An experimental element switch LSI for asynchronous transfer mode (ATM) switching systems was realized using 0.8-μm BiCMOS technology. The element switch transfers cells asynchronously when used in a buffered banyan network. Three key features of the element switch architecture are CASO buffers to increase the throughput, a synchronization technique called SCDB (synchronization in a clocked dual port buffer) to make possible asynchronous cell transmission on the element switches with simple hardware, and an implementation technique for virtual cut through, called CELL-BYPASS, which lowers the latency. An implementation of elastic store is proposed to achieve high-speed synchronization with simple hardware. The element switch LSI adopts an emitter-coupled-logic (ECL) interface. The maximum operation frequency of the element switch LSI is 200 MHz (typical)     

New paradigm of silicon technology

We present a new paradigm of Si technologies to establish a gigahertz-operation gigascale integrated system large-scale integration (LSI), including digital and analog circuits. According to the theoretical analysis of high-speed signal propagation properties in the practical LSI structure, a gas-isolated-interconnect high-k gate dielectric metal-gate metal-substrate silicon-on-insulator (SOI) LSI structure is proposed as a possible solution for a future gigahertz GSI system LSI, where the clock rate is improved up to beyond 10 GHz and the minimum feature size is reduced down to 0.035 μm in keeping with the continuous progress of the LSI's speed performance. Perfect scientific manufacturing free from fluctuations consisting of total low-temperature high-quality and high-speed processes based on very high-density plasma having very low electron temperatures is essential to realize them     

Application of advanced microelectronics to large-scalecommunication equipment-compact and maintenance-free TDMA equipment

An architecture is proposed for TDMA (time division multiple access) equipment and functional-module realization in microelectronics to increase reliability and to reduce hardware size and development time. The approach described basically involves digitization of analog circuits (allowing their realization using digital LSI circuits) and analog IC implementation for high-speed circuits. In order to use general-purpose LSI circuits and ICs, TDMA equipment is reconfigured into a hardware-oriented and simplified architecture. Using this architecture and optimal function assigning to each module, six types of general-purpose synchronization unit LSI circuits have been developed in addition to eleven types of LSI circuits and ICs, i.e. three types of digital LSI circuits, four types of MAICs (monolithic analog ICs), and four types of HICs (hybrid ICs) for a burst modem. As a result of this LSI circuit and IC implementation, the hardware size of TDMA equipment has been reduced to one-fifth of the conventional size, and maintenance-free capability has been achieved     

80 Gbit/s ATM switch MCM based on multilayer ceramic technology

An 80 Gbit/s asynchronous transfer mode (ATM) switch multichip module (MCM) of dimensions 114×160×6.5 mm has been fabricated. This MCM can support high-density mounting and high-speed interconnection among large-scale-integrated (LSI) chips. Using LSI, ceramic-substrate, high-speed/high-power connector, and compact liquid-cooling technologies, an 80 Gbit/s ATM switching module has been built     

64-Gb/s highly reliable network switch (RHiNET-2/SW) using paralleloptical interconnection

RHiNET-2/SW is a network switch that enables high-performance optical network based parallel computing system in a distributed environment. The switch used in such a computing system must provide high-speed, low-latency packet switching with high reliability. Our switch allows high-speed 8-Gb/s/port optical data transmission over a distance of up to 100 m, and the aggregate throughput is 64 Gb/s. In RHiNET-2/SW, eight pairs of 800-Mb/s×12-channel optical interconnection modules and a one-chip CMOS ASIC switch LSI (a 784-pin BGA package) are mounted on a single compact board. To enable high-performance parallel computing, this switch must provide high-speed, highly reliable node-to-node data transmission. To evaluate the reliability of the switch, we measured the bit error rate (BER) and skew between the data channels. The BER of the signal transmission through one I/O port was better than 10^-11 at a data rate of 800 Mb/s ×10 b with a large timing-budget margin (870 ps) and skew of less than 140 ps. This shows that RHiNET-2/SW can provide high-throughput, highly reliable optical data transmission between the nodes of a network-based parallel computing system     

A single-chip 16-bit 25-ns real-time video/image signal processor

A single-chip 16-b microprogrammable real-time video/image signal processor (VISP) has been developed for use in real-time motion picture encoding during low-bit-rate transmission for TV conference systems. In addition to stand-alone microprocessor functional units, the VISP integrates a high-speed variable seven-stage pipeline arithmetic circuit for video/image data processing and various controllers for easy I/O (input/output) and multiple-chip connections A 25-ns instruction cycle time is attained by using complementary reduced-swing CMOS logic circuits. The chip (14 mm×13.4 mm) was fabricated using a double-metal-layer 1.2-μm CMOS process technology and contains 220000 transistors     

A 1.5 Gb/s 8×8 cross-connect switch using a time reservationalgorithm

An input queuing type switching architecture that uses a high-performance contention resolution algorithm to achieve high-speed and large-capacity cross-connect switching is presented. The algorithm, called the time reservation algorithm, features time scheduling and pipeline processing. The performance of this switch is evaluated by computer simulation. The throughput of this switch is about 90%, without requiring high internal operation speeds. Three LSI designs are developed to verify the feasibility of the high-speed switch. They are the input buffer controller LSI, the contention-resolution module LSI, and the space-division switching LSI. The LSIs were constructed with an advanced Si-bipolar high-speed process. Also, 8×8 cross-connect switching boards are introduced. The measured maximum port speed is 1.55 Gb/s     

20.8 Gb/s GaAs LSI self-routing switch for ATM switching systems

An 8×8 self-routing hardware switch providing 20.8 Gb/s throughput has been developed for asynchronous transfer mode (ATM) switching systems. The basic architecture of this switch is a Batcher-Banyan network. A new mechanism for data processing and distributing high-speed signals is proposed. This switching system consists of three LSIs using a 0.5-μm gate GaAs MESFET technology. These LSIs are a switching network LSI for exchanging packet cells with eight cell channels, a negotiation network for screening of cells destined for the same output port, and a demultiplexer LSI for converting the cell streams from the switching network LSI to the eight streams per channel. These LSIs are mounted in a 520-pin multichip module package. The total number of logic gates is 13.3 k, and the power dissipation is 24 W. The switching system fully operates at a data rate of 2.6 Gb/s, and its throughput is 20.8 Gb/s     

A single-chip CMOS analog/digital mixed NTSC decoder

A single-chip CMOS LSI that integrates all analog-to-digital (A/D), digital-to-analog (D/A), peripheral, and digital signal processing circuits necessary for a digital National Television System Committee (NTSC) signal decoder is described. The LSI chip accepts composite NTSC video signals in analog form, digitizes them using the on-chip A/D converter, converts them to component RGB signals, and then converts the signals to analog form by using the on-chip D/A converters. The development of circuits that maximize use of the input digital data is discussed. A 6-b A/D circuit is used to reduce the circuit size. Circuits that help maintain acceptable picture quality despite 6-b resolution were developed. Besides analog NTSC signal input and RGB signal output, the IC can also input and output digital NTSC signals, Y/C (luminance, chrominance) signals, and RGB signals. Applications of the LSI are presented