SoC测试中低成本、低功耗的芯核包装方法

提出一种SoC测试中新颖的并行芯核包装方法（parallel core wrapper design,pCWD）,该包装方法利用扫描切片重叠这一特点,通过缩短包装扫描链长度来减少测试功耗和测试时间．为了进一步减少测试时间,还提出了一种测试向量扫描切片划分和赋值算法．实验结果表明,针对ITC2002基准SoC集中d695芯片,应用并行包装方法和测试向量切片划分及赋值算法,能够减少50％的测试时间及95％的测试功耗．     

SoC测试访问机制和测试壳的蚁群联合优化

针对系统级芯片(SoC)测试壳优化和测试访问机制的测试总线划分问题,提出了基于蚁群算法的SoC Wrapper/TAM联合优化方法.构造蚁群算法时首先进行IP核的测试壳优化,用于缩短最长扫描链长度,减少单个IP核的测试时间;在此基础上进行TAM结构的蚁群优化,通过算法迭代逼近测试总线的最优划分,从而缩短SoC测试时间.对ITC2002基准SoC电路进行实验的结果表明,该方法能有效地解决SoC测试优化问题.     

三维片上网络研究综述

三维片上网络以其更短的全局互连、更高的封装密度、更小的体积等诸多优势,已引起国内外学术界和产业界的高度重视.对三维片上网络的研究,将直接影响一个国家未来三维集成电路和三维芯片产业的发展,也关系到国家安全.近年来,三维片上网络逐渐成为片上网络研究领域的一个重要方向,已取得了许多研究进展,但仍然存在许多挑战性的课题.对三维片上网络的基本问题作了简介;分析了三维片上网络在国内外的研究现状;讨论了三维片上网络研究中的关键问题,归纳出网络拓扑结构、路由机制、性能评估、通信容错、功耗、映射、测试、交换技术、服务质量、流量控制、资源网络接口等12类研究课题;分类综述了关键问题的研究进展;分析了三维片上网络存在的问题;指出,在三维片上网络拓扑结构方面:个性化拓扑结构设计、仿真平台研究开发、基于新型拓扑结构的三维芯片样片试制以及无线技术的引入等,在路由算法方面:适合3D Torus的路由算法、结合无关路由与自适应路由算法优点的新路由算法、适合各种新型拓扑结构的高效路由算法等,在性能评估方面:永久故障的容错、改进仿真程序增加对物理链路的建模、充分考虑通信的局部性等,在功耗方面:对拓扑结构/映射算法/路由算法和布局进行综合优化、动态和静态控制相结合、更为精确的3D NoC功耗模型等,在映射方面:发热均匀性、动态路由策略下映射评估模型的优化、低功耗映射算法、基于优化算法的组合映射等,都将是三维片上网络未来的重要研究课题.     

SoC测试调度的进程代数模型

功耗约束下的SoC核流水测试可避免过高功耗毁坏待测芯片,对SoC核的流水测试进行调度可合理地分配测试资源、减少测试时间.以进程代数为理论基础,提出了一种SoC核流水测试的测试调度方法.通过建立并发测试进程的时间标记变迁系统模型,形成了将前者转化为共享资源的通信代数(ACSR)描述的几个定理;建立了SoC测试调度模型;将核的流水测试映射为并发执行的进程、把测试资源建模为ACSR资源,用优先级解决测试冲突,使得功耗约束下的测试获得最大并行性,同时使测试应用时间最小.实验结果证明进程代数ACSR在处理SoC测试调度问题方面优于已有的经典算法.     

3D SoC测试结构优化与测试调度的博弈模型

硅通孔技术是实现三维系统芯片的一种新兴的方法.而作为测试基础,测试访问机制和测试外壳则方便了三维系统芯片模块化测试,测试结构优化问题是研究的热点.提出基于博弈论的3D SoC测试结构优化技术,使基于核的三维系统芯片测试时间最少,TAM带宽最大,并且满足TSV数目约束.提出的方法利用二人合作博弈论方法的优点,对测试结构和测试调度问题进行建模,给出了基于博弈实现3D SoC测试结构优化的算法.用ITC02 SoC测试基准电路搭建成堆叠SoC,并在其上对提出的算法进行了模拟.实验结果显示,与之前的2D IC上开发的方法相比较,本文提出的测试结构优化与测试调度方法结果更优越.     

基于信道功耗测试的Petri网故障诊断算法

Petri网在路由信道变迁和功率耗散过程中,易产生路由引擎故障,通过故障诊断增强Petri网的自适应性,实现路由修复,降低网络功耗.传统方法采用统计特征的Petri网通信过程故障诊断方法,会在网络通信信道中产生具有不等长间歇的混叠谱,路由故障修复性能不好.提出一种网络密集信道混叠谱功耗测试的Petri网故障诊断算法.构建Petri网位置信息路由信道模型和能量消耗模型,测试Petri网络路由引擎转发损耗和功率放大损耗,把网络簇头节点帧级偏移输入相关矩阵,构建Petri网络节点之间发射和接收信号的路由节点耦合状态方程,优化故障特征目标函数,在混叠谱频段实现自适应能量均衡处理.根据功耗能量阈值进行控制限判别,实现故障节点定位和路由修复.仿真结果表明,改进算法故障检测率高,有效克服了Petri网络通信的串扰,使网络数据传输丢包率减低,性能优于传统方法.     

基于前缀的片上网络容错源路由算法

为克服片上网络链路永久性错误带来的路由问题,提出一种基于前缀的片上网络容错源路由算法PFTSR。该算法适用于二维mesh片上网络,采用预测路径并根据反馈信息调整路径的方法进行路由探测。在仿真平台NIRGAM上进行仿真,实验结果表明,与传统片上网络容错源路由算法SRN相比,PFTSR极大降低了片上系统的功耗,并且在大多数情况下能减少探测到第一条路径的时间。     

基于一种新网络拓扑结构的低功耗研究

随着芯片集成度的提高,片上网络(Network on Chip,NoC)是片上系统(System on Chip,SoC)发展的必然趋势,其中功耗成为限制性能提高的瓶颈.为了降低NoC的功耗,提出一种新的拓扑结构HMesh(Hexagon Mesh)及适用于该拓扑结构的HM路由算法,并对Mesh、Torus和HMesh结构的功耗进行了仿真实验.实验结果表明,在网络不发生拥塞时,HMesh结构的平均功耗比Mesh结构和Torus结构分别降低了12.9％和11.24％,更适合片上网络的构造.     

片上网络芯片——完美解决由路由拥塞引起的互联成本上涨问题

随着有线路由的纳米化发展,网络互联设计已成为制作系统芯片(SoC)的一个重要的考虑因素.而系统芯片进行IP互联所引起的导线消耗成为了芯片发展的制约因素.另一方面,路由的拥塞也间接地限制了系统芯片平面布局的紧凑性.因此芯片设计供应商已投入大量资金来研发物理综合工具,优化系统芯片,用于改善芯片布局和减少网络互联环节导线的使用量.此外,片上网络芯片(NoC)的研发也以最大限度地减少导线使用量作为设计的第一考虑因素.     

基于布谷鸟算法的3D NoC测试优化研究

在路由器数量、测试带宽、TSV数量和功耗的多重约束下进行三维片上网络(Three Dimensional Network-on-Chip,3D NoC)资源内核测试研究中,使测试时间最小化的同时降低测试功耗是NP难问题。在测试带宽和路由器数目等的限制下,采用改进的布谷鸟算法协同优化测试时间与功耗,避免过大的功耗产生热量影响芯片性能。通过logistic函数改进布谷鸟算法,利用其变化特性避免算法早熟,同时快速寻找到全局最优解。采用余弦递减函数动态改变发现概率,寻找和替换劣质解。采用ITC'02 SOC测试集作为实验对象,结果表明:对该算法进行改进后得到的最优解,实现了在多约束下最小化测试时间的同时减少测试功耗的目的,保证3D NoC的可靠性和测试效率。     

面向测试优化的片上网络映射算法

针对复杂片上系统(SoC)芯片的片上网络(NoC）映射方案未考虑测试需求的问题,提出了一种面向测试优化的NoC映射算法,兼顾了可测性的提升和映射开销的最小化。该映射方案首先依据特定的测试结构,使用划分算法进行片上系统所有IP核的测试分组,其优化目标为测试时间最短;之后,再基于分组内IP核之间的通信量,应用遗传算法实现NoC映射,其优化目标是在测试优化的基础上实现映射开销最小。通过多个ITC'02测试基准电路进行的实验结果表明:应用该方案后,测试时间平均减少12.67%;与随机任务映射相比,映射代价平均减少24.5%。     

An architectural co-synthesis algorithm for energy-aware Network-on-Chip design

Network-on-Chip (NoC) has been proposed to overcome the complex on-chip communication problem of System-on-Chip (SoC) design in deep sub-micron. A complete NoC design contains exploration on both hardware and software architectures. The hardware architecture includes the selection of Processing Elements (PEs) with multiple types and their topology. The software architecture contains allocating tasks to PEs, scheduling of tasks and their communications. To find the best hardware design for the target tasks, both hardware and software architectures need to be considered simultaneously. Previous works on NoC design have concentrated on solving only one or two design parameters at a time. In this paper, we propose a hardware–software co-synthesis algorithm for a heterogeneous NoC architecture. The design goal is to minimize energy consumption while meeting the real-time requirements commonly seen in embedded applications. The proposed algorithm is based on Simulated-Annealing (SA). To compare the solution quality and efficiency of the proposed algorithm, we also implement the branch-and-bound and iterative algorithm to solve the hardware–software co-synthesis problem of a heterogeneous NoC. With the given synthetic task sets, the experimental results show that the proposed SA-based algorithm achieves near-optimal solution in a reasonable time, while the branch-and-bound algorithm takes a very long time to find the optimal solution, and the iterative algorithm fails to achieve good solution quality. When applying the co-synthesis algorithms to a real-world application with PE library that has little variation in PE performance and energy consumption, the iterative algorithm achieves solution quality comparable to that of the proposed SA-based algorithm.     

A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms

Networks-on-Chip (NoCs) can be used for test data transportation during manufacturing tests. On one hand, NoC can avoid dedicated Test Access Mechanisms (TAMs), reducing long global wires, and potentially simplifying the layout. On the other hand, (a) it is not known how much wiring is saved by reusing NoCs as TAMs, (b) the impact of reuse-based approaches on test time is not clear, and (c) a computer aided test tool must be able to support different types of NoC designs. This paper presents a test environment where the designer can quickly evaluate wiring and test time for different test architectures. Moreover, this paper presents a new test scheduling algorithm for NoC TAMs which does not require any NoC timing detail and it can easily model NoCs of different topologies. The experimental results evaluate the proposed algorithm for NoC TAMs with an exiting algorithm for dedicated TAMs. The results demonstrate that, on average, 24% (up to 58%) of the total global wires can be eliminated if dedicated TAMs are not used. Considering the reduced amount of dedicated test resources with NoC TAM, the test time of NoC TAM is only, on average, 3.88% longer compared to dedicated TAMs.     

Time-Division-Multiplexed Test Delivery for NoC Systems

This test-scheduling approach for NoC designs minimizes test time through high-speed test delivery over the network, with test data interleaved via time-division multiplexing (TDM), and through slower test execution at the target cores. Results with a test-scheduling algorithm and a simulated test case from ITC 2002 SoC benchmarks show significant test time and I/O savings compared to a single-clock approach.     

改进量子算法的片上网络映射研究

片上网络（NoC）是解决片上系统（SoC）之间各个IP核通信的主要方法。其中NoC的映射是整个NoC设计过程中最为关键的步骤之一。采用一种改进的方法解决NoC映射问题,该方法基于量子进化算法,并在算法中采用一种改进的更新方法,之后引入精英策略,让所有中间过程的解都参与到迭代中,选择其中最好的解作为每次迭代的NoC映射最终解。使用该方法建立在延时约束下的NoC映射功耗数学模型,实验表明,该方法在NoC映射中能达到降低通信功耗的目的。     

Power-aware system-on-chip test scheduling using enhanced rectangle packing algorithm

The current semiconductor technology allows integration of all components onto a single chip called system-on-chip (SoC), which scales down the size of product and improves the performance. When a system becomes more complicated, testing process, such as test scheduling, becomes more challenging. Recently, peak power has also been considered as constraints in the test scheduling problem. Besides these constraints, some add-on techniques including pre-emption and non-consecutive test bus assignment have been introduced. The main contribution of each technique is the reduction of idling time in the test scheduling and thus reducing the total test time. This paper proposes a power-aware test scheduling called enhanced rectangle packing (ERP). In this technique, we formulate the test scheduling problem as the rectangle packing with horizontally and vertically split-able items (rectangles) which are smaller to fill up more compactly the test scheduling floor plan. Experimental results conducted on ITC’02 SoC benchmark circuits revealed positive improvement of the power-aware ERP algorithm in reducing total SoC test time.     

AEthereal network on chip: concepts, architectures, and implementations

The continuous advances in semiconductor technology enable the integration of increasing numbers of IP blocks in a single SoC. Interconnect infrastructures, such as buses, switches, and networks on chips (NoCs), combine the IPs into a working SoC. Moreover, the industry expects platform-based SoC design to evolve to communication-centric design, with NoCs as a central enabling technology. In this article, we introduce the AEthereal NoC. The tenet of the AEthereal NoC is that guaranteed services (GSs) - such as uncorrupted, lossless, ordered data delivery; guaranteed throughput; and bounded latency - are essential for the efficient construction of robust SoCs. To exploit the NoC capacity unused by the GS traffic, we provide best-effort services.     

延迟优化的片上网络低功耗映射*

片上网络（NoC）是解决传统基于总线的片上系统（SoC）所面临的功耗、延迟、同步和信号完整性等挑战的有效解决方案。功耗和延迟是NoC设计中的重要约束和性能指标,在设计的各个阶段都存在着优化空间。基于蚁群优化算法,通过通信链路上并发通信事件的均匀分布来降低NoC映射阶段的功耗和延迟。仿真实验表明,与链路通信量负载均衡的方法相比,该方案能进一步在拓扑映射阶段优化功耗和延迟。     

基于多核系统NOC架构的静态列表调度算法*

在单芯片多核系统中,NoC已成为主流片上通信架构,有效的任务调度是挖掘计算并行性的重要方面。本文在经典静态列表调度基础上,针对HEFT算法中节点排序会得出较多的优先级相同节点的问题,提出一种节点二次排序的调度方法,在边的调度上应用了ALAP原则,改进算法有效提高了调度效果。实验表明：新方法对bl、blcomp、blio等节点优先级算法得出的任务列表均有良好的调度效果,适应性较好;对于2D MESH同构NoC平台,改进算法对三种节点优先级算法有1.15倍的平均加速比,最大可有1.27倍加速比。     

基于NoC结构的图像中值滤波并行处理模式分析

给出了一个多处理器NoC结构以实现指定的中值滤波算法。为了提高图像处理的速度,在NoC设计的专用SoC中使用了系统并行机制与基本计算单元指令并行机制相结合的方法。它既可以满足处理速度的要求,又能达到降低功率损耗的目的。对图像处理中的中值滤波处理结构进行了并行设计,可极大地提高处理速度。