A low noise,high power efficiency supply regulator for near-field power delivery

In order to deliver near-field electromagnetic power to a biomedical device or an RFID tag efficiently, the downlink signal is preferred to be at a high voltage level. To reduce power consumption and meet low supply requirements, it is advantageous for the remote device power supply to step-down the input voltage following rectification, typically using switch-mode regulators. The output ripple of a switched capacitor converter is inversely proportional to the filtering capacitance at the output node and switching frequency. In this paper, a hybrid DC–DC converter utilizing a switched capacitor regulator in master–slave configuration with a linear regulator is presented. Linear regulator actively cancels the switching ripple, while low frequency and DC current is provided by the switched capacitor converter. The converter is designed to receive an average input voltage of 5 Vpk from the receiver coil, with an output voltage of 2 V, and 5 mA of output current. The proposed regulator is fabricated in 0.35 μm technology. The power efficiency is measured to be 67%, with a nominal peak to peak ripple of less than 2 mV at the output.     

A fully on-chip LDO voltage regulator with 37 dB PSRR at 1 MHz for remotely powered biomedical implants

This article presents a fully on-chip low-power LDO voltage regulator dedicated to remotely powered wireless cortical implants. This regulator is stable over the full range of alternating load current and provides fast load regulation achieved by applying a time-domain design methodology. Moreover, a new compensation technique is proposed and implemented to improve PSRR beyond the performance levels which can be obtained using the standard cascode compensation technique. Measurement results show that the regulator has a load regulation of 0.175 V/A, a line regulation of 0.024%, and a PSRR of 37 dB at 1 MHz power carrier frequency. The output of the regulator settles within 10-bit accuracy of the nominal voltage (1.8 V) within 1.6 μs, at full load transition. The total ground current including the bandgap reference circuit is 28 μA and the active chip area measures 290 μm × 360 μm in a 0.18 μm CMOS technology.     

Fully on-chip switched capacitor NMOS low dropout voltage regulator

This paper presents a 1.5 V 50 mA low dropout voltage (LDO) regulator using an NMOS transistor as the output pass element. Continuous time operation of the LDO is achieved using a new switched floating capacitor scheme that raises the gate voltage of the pass element. The regulator has a 0.2 V dropout at a 50 mA load and is stable for a wide load current range with loading capacitances up to 50 pF. The output variation when a full load step is applied is 300 mV and the recovery time is below 0.3 μs. It is designed in a 0.13 μm CMOS process with an area of 0.008 mm² and its operation does not require any external component.     

Sleep-mode ready,area efficient capacitor-free low-dropout regulator with input current-differencing

This paper proposes an input current-differencing technique in designing a capacitor-free low-dropout regulator to simultaneously achieve sleep-mode efficiency and silicon real estate saving. With no minimum output current required to be stable, the regulator could greatly improve SoC efficiency during standby, which is extremely attractive for battery powered applications. Designed in TSMC 0.18-μm CMOS technology, it regulates 1.8–1.2 V supply down to 1 V with 100 mA maximum output current and can drive up to 100 pF of load parasitic capacitance. Compared with prior arts with the same sleep-mode compatibility and similar output current range, it reduces the on-chip compensation capacitance from 21 to 4.5 pF.     

Area-efficient linear regulator with ultra-fast load regulation

We demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology. Ultra-fast single-stage load regulation achieves a 0.54-ns response time at 94% current efficiency. For a 1.2-V input voltage and 0.9-V output voltage the regulator enables a 90 mV/sub P-P/ output droop for a 100-mA load step with only a small on-chip decoupling capacitor of 0.6 nF. By using a PMOS pull-up transistor in the output stage we achieved a small regulator area of 0.008 mm/sup 2/ and a minimum dropout voltage of 0.2 V for 100 mA of output current. The area for the 0.6-nF MOS capacitor is 0.090 mm/sup 2/.     

A dual-phase charge pump circuit with compact size

In this paper, a regulated dual-phase charge pump with compact size is presented. By means of a nano-ampere switched-capacitor voltage reference (SCVR) circuit, the dual-phase charge pump regulator can reduce the quiescent current and the output ripple. Besides, a new power stage is proposed to define the stability of the overall system. Owing to the design of buffer stage, the charge pump regulator can extend bandwidth and increase phase margin. Thus, the transient response and driving capability can be improved. Beside, the proposed automatic body switching circuit can efficiently drive the bulk of the power p-type MOSFETs to avoid leakage and potential latch-up. This chip was fabricated by TSMC 0.35 μm, 3.3 V/5 V 2P4 M CMOS technology. The input voltage range varies from 2.9 to 4.9 V for the lithium battery and the output voltage is regulated at 5 V. Experimental results demonstrate the charge pump can provide 50 mA maximum load current without any oscillation problems.     

A new current-mode fast-transient-response shunt regulator using CMOS technology

The demand for current-mode fast-transient-response shunt regulator is increasing for the growth of portable electronics, such as cellular phones, PDA, laptops, etc. A new current-mode fast-transient-response shunt regulator is presented in this paper. The proposed shunt regulator used a single Miller compensation capacitor to increase stability. The current-mode shunt regulator helps the transient response to be faster than the voltage-mode low-dropout regulator (LDO) and the power noise (bounce noise) is smaller than one. The proposed current-mode shunt regulator has been fabricated with TSMC 0.35 μm 2P4M CMOS technology. The experimental results show the transient-response time is only 400 ns within 0.5% error and the maximum output voltage dip is only 70 mV for full loading current variation. Moreover, the line and load regulations are 26 μV/mA and 8 ppm/mA, respectively. The dropout current is 1.0741 mA for loading current 150 mA. The active chip area is 226 μm × 310 μm.     

A microwatt switched-capacitor voltage doubler-based voltage regulator for ultra-low power energy harvesting systems

This paper presents an SC voltage doubler-based voltage regulator for ultra-low power energy harvesting applications. It produces a stable 1.2-V power supply, using inputs from 0.63 to 1.8 V. External compensation and an on-chip output capacitor ensure good performance even with zero load current and any load capacitance. The regulator tolerates arbitrary input ramp-ups, and is immune to blackout and brownout. A stability analysis for the regulator control loop is presented. The regulator ASIC is implemented in a 180 nm CMOS process. The measured regulator peak power and current efficiency are 63 and 49 %, respectively. The performance has been characterized with load currents from zero to \(100\,\upmu\)A.     

An ultra low noise readout integrated circuit for uncooled microbolometers

A low noise readout architecture for uncooled microbolometer focal plane arrays is described. The on-chip readout circuit contains an integration circuit in which the bolometer current is directed injected into a capacitor, and exhibits extremely low noise with no decrease in signal by using an ultra low noise capacitive transimpedance amplifier (CTIA). The simple configuration of the integration circuit makes it possible to operate more circuits in parallel, and increases the integration time and number of pixels. A 40 × 30 uncooled microbolometer focal plane array based on the low noise ROIC was implemented on silicon using a 0.5 μm CMOS technology. The total output noise voltage is 260 μV RMS. A noise at this level is so low that can loosen required TCR in the bolometer material. Experimental values of voltage responsivities of 3.98 × 10⁵ V/W on average at 1 Hz modulation frequency have been achieved.     

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver is presented. The problems to implement the low voltage design and the on-chip input/output impedance matching are considered, and some improved circuits are presented to overcome the problems. Especially, a single-end input, differential output double balanced mixer with an on-chip bias loop is analyzed in detail to show its advantages over other mixers. The transceiver RF front-end has been implemented in 0.18 um CMOS process, the measured results show that the Rx front-end achieves 5.23 dB noise figure, 12.7 dB power gain (50 ohm load), −18 dBm input 1 dB compression point (ICP) and −7 dBm IIP3, and the Tx front-end could output +2.1 dBm power into 50 ohm load with 23.8 dB power gain. The transceiver RF front-end draws 13.6 mA current from a supply voltage of 1.8 V in receive mode and 27.6 mA current in transmit mode. The transceiver RF front-end could satisfy the performance requirements of IEEE802.11b WLAN standard. Supported by the National Natural Science Foundation of China, No. 90407006 and No. 60475018.     

Pseudo-V2 control with adaptive compensation for fast-transient current-mode buck converter

A type of pseudo-V² control, with on-chip adaptive compensation to achieve fast transient (FT) response for current mode DC–DC buck converter, has been proposed and simulated using 0.18 μm CMOS technology in this paper. Based on a new on-chip capacitor multiplier, adaptive compensation is achieved by making the compensation capacitance to track the load current. The proposed pseudo-V² control utilizes the output ripple to determine the duty cycle during load transient. Thus the overshoot/undershoot voltage and the transient recovery time are effectively reduced. Simulation results demonstrate the transient ripple is smaller than 50 mV and the transient recovery time is shorter than 10 μs for a 450 mA load current step. The maximum power conversion efficiency is 94.6% at 1 MHz switching frequency when input and output voltages are 5 V and 1.8 V, respectively.     

An 8-bit, 10 kHz, 5.1 μW, 0.18 μm CMOS SAR ADC for RFID applications with sensing capabilities

An 5.1 μW, 1.8 V, 8-bit, successive approximation (SAR) analog-to-digital converter (ADC) using 10 kHz clock was designed and fabricated in a 0.18 μm CMOS technology for passive UHF radio frequency identification (RFID) applications. The ADC utilises a resistive digital to analog converter (DAC). The ADC can operate with low power consumption. The proposed comparator with cascode active load can offer large gain and can operate at a low supply voltage. The measured total power consumption is 5.1 μW at a 10 kHz input clock with a 1.8 V single supply, and 0.5 μW with 970 mV supply.     

A high-PSR transient-enhanced output-capacitorless CMOS low-dropout regulator for SoC applications

A transient-enhanced output-capacitorless CMOS low-dropout voltage regulator (LDO) with high power supply rejection (PSR) is introduced for system-on-chip applications. In order to reduce external pin count and device area and be amenable to full integration, the large external capacitor used in the classical LDO design is eliminated and replaced with a much smaller 5.7?pF on-chip capacitor. High-gain folded-cascode stage, wideband common source stage, voltage subtractor stage and transient-enhanced circuit are designed altogether to realise circuit compensation and achieve good frequency and transient performances. A current-sensing and transient-enhanced circuit is utilised to reduce transient voltage dips effectively and efficiently drive different kinds of load capacitances. The active chip area of the proposed regulator is only 200?×?280?µm². The simulation results under mixed-signal 0.18?µm 1P6M process show that this novel LDO's output voltage can recover within 1.7?µs (rising) and 2.41?µs (falling) under full load-current changes. The input voltage is ranged from 2 to 5?V for a load current 50?mA and an output voltage of 1.8?V. This novel LDO has wide unity-gain frequency stability and is stable for estimated equivalent parasitic capacitive loads from 0 to 100?pF. Moreover, it can achieve a PSR of ?78.5 and ?73?dB at 1 and 10?kHz, respectively.     

Fast-response single-inductor dual-output hysteresis-current-controlled DC–DC buck converter

A fast-response single-inductor dual-output hysteresis-current-controlled DC–DC buck is proposed for enhancing the transient characteristics of switching DC–DC converters and fabricated with TSMC 0.35 μm DPQM CMOS processes. By adopting a hysteresis-current-controlled DC–DC buck converter, it is demonstrated that the hysteresis-current-controlled technique have improved dynamic response of load variations whether the load current is light or heavy. Fast-response structure achieves 5 μs response with load variation which betweens 10 and 110 mA. Also proposed single-inductor dual-output structure is a time-multiplexing circuit to decrease the influence of cross regulation than that of previous designs. With a 3.6 V input power supply, the DC–DC buck converter precisely provides an adjustable power output with a voltage range from 0.9 to 3 V.     

A fully on-chip area-efficient CMOS low-dropout regulator with fast load regulation

Fully integrated voltage regulators with fast transient response and small area overhead are in high demand for on-chip power management in modern SoCs. A fully on-chip low-dropout regulator (LDO) comprised of multiple feedback loops to tackle fast load transients is proposed, designed and simulated in 90?nm CMOS technology. The LDO also adopts an active frequency compensation scheme that only needs a small amount of compensation capacitors to ensure stability. Simulation results show that, by the synergy of those loops, the LDO improves load regulation accuracy to 3???V/mA with a 1.2?V input and 1?V output. For a 100?mA load current step with the rise/fall time of 100?ps, the LDO achieves maximum output voltage drop and overshoot of less than 95?mV when loaded by a 600?pF decoupling capacitor and consumes an average bias current of 408???A. The LDO also features a magnitude notch in both its PSRR and output impedance that provides better suppression upon the spectral components of the supply ripple and the load variation around the notch frequency. Monte Carlo simulations are performed to show that the LDO is robust to process and temperature variations as well as device mismatches. The total area of the LDO excluding the decoupling capacitor is about 0.005?mm². Performance comparisons with existing solutions indicate significant improvements the proposed LDO achieves.     

一种1.2V,80mA,5μF快速瞬态响应、高稳定性LDO的设计

基于上华0.5μm工艺,设计了输入电压为1.5V,输出电压为1.2V,最大输出电流为80mA,用于DC/DC里的CMOS低压差线性稳压器(Low-dropout regulator),作为带隙基准输出端的后续模块,以达到滤波和提高参考电压精度的目的。提出了一种补偿网络,可以保证负载电流发生变化时,相位裕量不发生变化;在补偿网络的基础上添加一个感应电容能够快速跟踪极点的变化,从而保证在负载电流跳变瞬间稳定性保持不变,防止了输出电压发生振荡的情形。此外,设计了一种瞬态响应提高电路结构来改善负载瞬态响应。仿真结果表明,在tt corner下该LDO线性稳压器在负载电流为1mA和80mA时的相位裕度均为83°,环路增益为80dB,流片测试结果显示过冲电压和欠冲电压均不超过100mV。     

A robust low quiescent current power receiver for inductive power transmission in bio implants

In this paper, a robust low quiescent current complementary metal-oxide semiconductor (CMOS) power receiver for wireless power transmission is presented. This power receiver consists of three main parts including rectifier, switch capacitor DC–DC converter and low-dropout regulator (LDO) without output capacitor. The switch capacitor DC–DC converter has variable conversion ratios and synchronous controller that lets the DC–DC converter to switch among five different conversion ratios to prevent output voltage drop and LDO regulator efficiency reduction. For all ranges of output current (0–10 mA), the voltage regulator is compensated and is stable. Voltage regulator stabilisation does not need the off-chip capacitor. In addition, a novel adaptive biasing frequency compensation method for low dropout voltage regulator is proposed in this paper. This method provides essential minimum current for compensation and reduces the quiescent current more effectively. The power receiver was designed in a 180-nm industrial CMOS technology, and the voltage range of the input is from 0.8 to 2 V, while the voltage range of the output is from 1.2 to 1.75 V, with a maximum load current of 10 mA, the unregulated efficiency of 79.2%, and the regulated efficiency of 64.4%.     

A technique for improving gain and noise figure of common-gate wideband LNAs

This paper presents a novel compensation design for regulators, i.e., modified NMCF (nested Miller compensation with feedforward Gm stage), resulting in a linear LDO (low dropout) regulator whose performance is independent of the off-chip capacitor and its ESR (equivalent series resistor). The proposed compensation method ensures the stability of the feedback loop and the sufficient phase margin of the LDO regulator. Besides, the transient response become faster. The analysis of the stability is derived to solidify the proposed design. The proposed design is implemented using TSMC 0.35 μm 2P4M CMOS process. The results verify the performance and the stability on silicon. The power supply rejection ratio is 25 dB @ [200 Hz, 3 MHz], [50 Ω, 500 Ω] provided that the input voltage varies from 4 to 5 V.     

A low power voltage limiter for a full passive UHF RFID sensor on a 0.35 μm CMOS process

This paper presents a low power voltage limiter design for avoiding possible damages in the analog front-end of a RFID sensor due to voltage surges whenever readers and tags are close. The proposed voltage limiter design takes advantage of the implemented bandgap reference and voltage regulator blocks in order to provide low deviation of the limiting voltage due to temperature variation and process dispersion. The measured limiting voltage is 2.9 V with a voltage deviation of only ±0.065 V for the 12 measured dies. The measured current consumption is only 150 nA when the reader and the tag are far away, not limiting the sensitivity of the tag due to an undesired consumption in the voltage limiter. The circuit is implemented on a low cost 2P4M 0.35 μm CMOS technology.     

High slew rate current mode transconductance error amplifier for low quiescent current output-capacitorless CMOS LDO regulator

This paper presents a CMOS low quiescent current output-capacitorless low-dropout regulator (LDO) based on a high slew rate current mode transconductance amplifier (CTA) as error amplifier. Using local common-mode feedback (LCMFB) in the proposed CTA, the order of transfer characteristic of the circuit is increased. Therefore, the slew rate at the gate of pass transistor is enhanced. This improves the LDO load transient characteristic even at low quiescent current. The proposed LDO topology has been designed and post simulated in HSPICE in a 0.18 µm CMOS process to supply the load current between 0 and 100 mA. The dropout voltage of the LDO is set to 200 mV for 1.2–2 V input voltage. Post-layout simulation results reveal that the proposed LDO is stable without any internal compensation strategy and with on-chip output capacitor or lumped parasitic capacitances at the output node between 10 and 100 pF. The total quiescent current of the LDO including the current consumed by the reference buffer circuit is only 3.7 µA. A final benchmark comparison considering all relevant performance metrics is presented.