A fully integrated switched-capacitor DC–DC converter with hybrid output regulation

In this paper, we propose a fully integrated switched-capacitor (SC) DC–DC converter with hybrid output regulation that allows a predictable switching noise spectrum. The proposed hybrid output regulation method is based on the digital capacitance modulation for fine regulation and the automatic frequency scaling for coarse regulation. The automatic frequency scaler and on-chip current sensor are implemented to adjust the switching frequency at one of the frequencies generated by a binary frequency divider with change in load current. Thus, the switching noise spectrum of the proposed SC DC–DC converter can be predicted over the entire load range. In addition, the bottom-plate losses due to the parasitic capacitances of the flying capacitors and the gate-drive losses due to the gate capacitances of switches are reduced at light load condition since the switching frequency is automatically adjusted. The proposed SC DC–DC converter was implemented in a 0.13 µm CMOS process with 1.5 V devices, and its measurement results show that the peak efficiency and the efficiency at light load condition are 69.2% and higher than 45%, respectively, while maintaining a predictable switching noise spectrum.     

A Dual-Mode Step-up DC/DC Converter IC with Current-Limiting and EMI Reduction Techniques

This paper presents a novel dual-mode step-up （boost） DC/DC converter. Pulse-frequency modulation （PFM） is used to improve the efficiency at light load. This converter can operate between pulse-width modulation （PWM） and pulse-frequency modulation. The converter will operate in PFM mode at light load and in PWM mode at heavy load. The maximum conversion efficiency of this converter is 96%. The conversion efficiency is greatly improved when load current is below 100 mA. Additionally, a soft-start circuit and a variable-sawtooth frequency circuit are proposed in this paper. The former is used to avoid the large switching current at the start up of the converter and the latter is utilized to reduce the EMI of the converter.     

A monolithic buck DC–DC converter with on-chip PWM circuit

A monolithic CMOS voltage-mode, buck DC–DC converter with integrated power switches and new on-chip pulse-width modulation (PWM) technique of switching control is presented in this paper. The PWM scheme is constructed by a CMOS ring oscillator, which duty is compensated by a pseudo hyperbola curve current generator to achieve almost constant frequency operation. The minimum operating voltage of this voltage-mode buck DC–DC converter is 1.2 V. The proposed buck DC–DC converter with a chip area of 0.82 mm² is fabricated with a standard 0.35-μm CMOS process. The experimental results show that the converter is well regulated over an output range from 0.3 to 1.2 V, with an input voltage of 1.5 V. The maximum efficiency of the converter is 88%, and its efficiency is kept above 80% over an output power ranging from 30 to 300 mW.     

Adaptive duty ratio modulation technique in switching DC–DC converter operating in discontinuous conduction mode

Adaptive duty ratio (ADR) modulation technique in switching DC–DC converter operating in discontinuous conduction mode is proposed in this paper. The proposed ADR modulation technique can regulate the output voltage of the DC–DC converter by generating a series of duty ratios with very simple circuit architecture. The duty ratio is approximately proportional to the square root of the voltage difference between the regulated output voltage and the reference voltage at the beginning of the switching cycle at the light load. As a result, the proposed ADR modulation technique can achieve smaller ripple than the conventional pulse skip modulation over the whole load range. Moreover, the compromise between the light-load ripple and the output power range in the design stage in previous works is solved in the ADR modulation technique. Theoretical analysis, simulation and experimental results are presented to show the operation principle and the advantage of the proposed ADR modulation technique.     

Switched-capacitor DC/DC converters with resonant gate drive

In this paper, we examine how switched-capacitor (SC) converters can be used in low-voltage low-power DC/DC applications with power management. Analysis of losses is presented to facilitate SC converter design and optimization. A resonant gate drive is proposed to reduce switching losses and simplify control of switches in SC converters. A closed-loop controller is designed to enable and disable oscillations of the resonant gate drive so that the output DC voltage is well regulated down to zero load and so that high efficiency is maintained for a very wide range of loads. Results are experimentally verified on two low-power (0.2 and 5 W) five-one step-down converters with regulated 3 Vdc output and efficiency greater than 80% in a 100-1 load range     

High efficiency,high switching speed,AlGaAs/GaAs P-HEMT DC–DC converter for integrated power amplifier modules

This paper presents a high efficiency, high switching frequency DC–DC buck converter in AlGaAs/GaAs technology, targeting integrated power amplifier modules for wireless communications. The switch mode, inductor load DC–DC converter adopts an interleaved structure with negatively coupled inductors. Analysis of the effect of negative coupling on the steady state and transient response of the converter is given. The coupling factor is selected to achieve a maximum power efficiency under a given duty cycle with a minimum penalty on the current ripple performance. The DC–DC converter is implemented in 0.5 μm GaAs p-HEMT process and occupies 2 × 2.1 mm² without the output network. An 8.7 nH filter inductor is implemented in 65 μm thick top copper metal layer, and flip chip bonded to the DC–DC converter board. The integrated inductor achieves a quality factor of 26 at 150 MHz. The proposed converter converts 4.5 V input to 3.3 V output for 1 A load current under 150 MHz switching frequency with a measured power efficiency of 84%, which is one of the highest efficiencies reported to date for similar current/voltage ratings.     

Dual-output switched-capacitor DC–DC converter with pseudo-three-phase swap-and-cross control and amplitude modulation mechanism

This paper presents an inductorless dual-output switched-capacitor DC–DC converter employing pseudo-three-phase swap-and-cross control (PTPSCC) and an amplitude modulation mechanism (AMM). The AMM circuit scales the amplitudes of the driving signals for the switches according to the loading conditions in order to minimize switching losses. To reduce output ripples, average charge distribution, and improve regulation, the PTPSCC circuit continuously switches power transistors to deliver enough charge to the outputs by keeping at least one flying capacitor connected to each output. The switched capacitor DC–DC converter was implemented in a standard 0.18-μm 3.3-V CMOS process. Measurements were used to verify that the proposed converter provides dual independently regulated output voltages without cross regulation. The two outputs were regulated at 2.5 and 0.8 V with input ranges of 1.7–2 V. The maximum output loading was 100 mA for both outputs. A power efficiency of 90.5% was achieved at a maximum total output power of 330 mW with a switching frequency of 500 kHz, and a maximum power efficiency of 92.1% was achieved for a total output power of 210 mW. The maximal peak-to-peak output ripple voltages for the two outputs at 100 mA load currents were suppressed to below 26 and 20 mV, respectively.     

A low noise,high power efficiency supply regulator for near-field power delivery

In order to deliver near-field electromagnetic power to a biomedical device or an RFID tag efficiently, the downlink signal is preferred to be at a high voltage level. To reduce power consumption and meet low supply requirements, it is advantageous for the remote device power supply to step-down the input voltage following rectification, typically using switch-mode regulators. The output ripple of a switched capacitor converter is inversely proportional to the filtering capacitance at the output node and switching frequency. In this paper, a hybrid DC–DC converter utilizing a switched capacitor regulator in master–slave configuration with a linear regulator is presented. Linear regulator actively cancels the switching ripple, while low frequency and DC current is provided by the switched capacitor converter. The converter is designed to receive an average input voltage of 5 Vpk from the receiver coil, with an output voltage of 2 V, and 5 mA of output current. The proposed regulator is fabricated in 0.35 μm technology. The power efficiency is measured to be 67%, with a nominal peak to peak ripple of less than 2 mV at the output.     

集成双层平面电感的单片DC/DC转换器设计

采用0.35μm标准CMOS工艺设计了3.3V/1.5V单片低压Buck转换器,开关频率为150MHz.本文采用了电压型脉宽调制的反馈控制模式,克服了频率提高所带来的转换器系统不稳定问题.对双层平面螺旋电感进行了设计与优化,获得品质因数2.6,电感值28nH的双层平面电感.模拟结果表明,对应于不同输入电压或不同负载,转换器系统工作稳定,输入调整率-40dB,输出调整率-60dB.输出电压纹波平均值可以控制在额定值75mV,转换效率71%.     

Pseudo-V2 control with adaptive compensation for fast-transient current-mode buck converter

A type of pseudo-V² control, with on-chip adaptive compensation to achieve fast transient (FT) response for current mode DC–DC buck converter, has been proposed and simulated using 0.18 μm CMOS technology in this paper. Based on a new on-chip capacitor multiplier, adaptive compensation is achieved by making the compensation capacitance to track the load current. The proposed pseudo-V² control utilizes the output ripple to determine the duty cycle during load transient. Thus the overshoot/undershoot voltage and the transient recovery time are effectively reduced. Simulation results demonstrate the transient ripple is smaller than 50 mV and the transient recovery time is shorter than 10 μs for a 450 mA load current step. The maximum power conversion efficiency is 94.6% at 1 MHz switching frequency when input and output voltages are 5 V and 1.8 V, respectively.     

A voltage mode buck DC–DC converter with automatic PWM/PSM mode switching by detecting the transient inductor current

This paper presents a voltage mode buck DC–DC converter that integrates pulse-width modulation (PWM) and pulse-skipping modulation (PSM) to achieve high efficiency under heavy and light load conditions, respectively. Automatic mode-switching is implemented simply by detecting the voltage drop of high-side power switch when it is on, which indicates the transient current flowing through the inductor. Unlike other methods based on average current sensing, the proposed auto-mode switching scheme is implemented based on voltage comparison and simple control logic circuit. In order to avoid unstable mode switching near the load condition boundary, the mode switching threshold voltage is set differently in PWM and PSM mode. Besides, a 16-cycle counter is also used to ensure correct detection of the change in the load condition and fast response of the converter. In addition, a dual-path error amplifier with clamp circuit is also adopted to realize loop compensation and ensure 100 % duty cycle operation. Fabricated in a 0.18-μm standard CMOS technology, the DC–DC converter is able to operate under supply voltage from 2.8 to 5.5 V with 3-MHz clock frequency. Measurement results show that the converter achieves a peak efficiency of 93 %, and an output voltage ripple of less than 40 mV, while the chip area is 1.02 mm².     

Analysis,design and implementation of an interleaved three-level PWM DC/DC ZVS converter

This paper presents a new parallel three-level soft switching pulse-width modulation (PWM) converter. The proposed converter has two circuit cells operated by the interleaved PWM modulation. Thus, the ripple currents at input and output sides are reduced. Each circuit cell has two three-level zero voltage switching circuits sharing the same power switches. Therefore, the current and power rating of the secondary side components are reduced. Current double rectifier topology is selected on the secondary side to decrease output ripple current. The main advantages of the proposed converter are soft switching of power switches, low ripple current on the output side and low-voltage rating of power switches for medium-power applications. Finally, the performance of the proposed converter is verified by experiments with 1 kW prototype circuit.     

不连续导通模式PSM PT控制开关变换器

脉冲跳周期调制（Pulse Skip Modulation,PSM）采用ON/OFF控制对输出电压进行调整,提高了开关变换器的轻载效率,但存在输出电压纹波大的缺点。文中结合开关变换器的脉冲序列调制（Pulse Train,PT）控制与PSM技术,提出了开关变换器的PSM PT控制技术,其降低了输出电压的纹波,并使PT控制开关变换器在空载时能稳定工作。     

A New PWM-Controlled Quasi-Resonant Converter for a High Efficiency PDP Sustaining Power Module

A new pulsewidth modulation (PWM)-controlled quasi-resonant converter for a high-efficiency plasma display panel (PDP) sustaining power module is proposed in this paper. The load regulation of the proposed converter can be achieved by controlling the ripple of the resonant voltage across the primary resonant capacitor with a bidirectional auxiliary circuit, while the main switches are operating at a fixed duty ratio and fixed switching frequency. Hence, the waveforms of the currents can be expected to be optimized from the view-point of conduction loss. Furthermore, the proposed converter has good zero-voltage switching (ZVS) capability, simple control circuits, no hign-voltage ringing problem of rectifier diodes, no dc offset of the magnetizing current and low-voltage stresses of power switches. Thus, the proposed converter shows higher efficiency than that of a half-bridge LLC resonant converter under light load condition. Although it shows the lower efficiency at heavy load, because of the increased power loss in auxiliary circuit, it still shows the high efficiency around 94%. In this paper, operational principles, features of the proposed converter, and analysis and design considerations are presented. Experimental results demonstrate that the output voltage can be controlled well by the auxiliary circuit using the PWM method.      

A dual-mode fast-transient average-current-mode buck converter without slope-compensation

A dual-mode fast-transient average-current-mode buck converter without slope-compensation is proposed in this paper. The benefits of the average-current-mode are fast-transient response, simple compensation design, and no requirement for slope-compensation, furthermore, that minimizes some power management problems, such as EMI, size, design complexity, and cost. Average-current-mode control employs two loop control methods, an inner loop for current and an outer one for voltage. The proposed buck converter using the current-sensing and average-current-mode control techniques can be stable even if the duty cycle is greater than 50%. Also, adaptively switch between pulse-width modulation (PWM) and pulse-frequency modulation (PFM) is operated with high conversion efficiency. Under light load condition, the proposed buck converter enters PFM mode to decrease the output ripple. Even more, switching PWM mode realizes a smooth transition under heavy load condition. Therefore, PFM is used to improve the efficiency at light load. Dual-mode buck converter has high conversion efficiency over a wide load conditions. The proposed buck converter has been fabricated with TSMC 0.35 μm CMOS 2P4M processes, the total chip area is 1.45×1.11 mm². Maximum output current is 450 mA at the output voltage 1.8 V. When the supply voltage is 3.6 V, the output voltage can be 0.8-2.8 V. Maximum transient response is less than 10 μs. Finally, the theoretical analysis is verified to be correct by simulations and experiments.     

一种新型交错并联同相降压升压DC/DC转换器

为了有效降低电流纹波和提高转换器效率,提出一种新型交错并联同相降压升压DC/DC转换器。提出的结构通过采用输入/输出（I/O）磁耦合交错并联和阻尼网络技术,降低了开关的电压应力、内部电压振荡和I/O电流纹波,并提升了转换器的效率。采用状态空间平均法,在连续导通模式下分析了提出转换器的稳态运行,从理论上证明了其优势。样机的功率设置为360W,输出电压为36 V,模拟结果以及实验结果显示,当输出电流为6A时,转换效率最高达到96%,最大输入电流纹波百分比仅为9.4%,相较于其他类似转换器,提出的转换器具有效率较高和I/O电流纹波较低的优势。     

Four-quadratic DC magnet power supply with fast dynamic responseand low ripple content

The authors discuss a power supply configuration based on a switching converter, with reasonably fast dynamic response and low ripple content, so that the linear power supplies can be replaced in four-quadrant DC magnet power supply applications. A new power supply configuration, based on the combination of a frequency converter and a dual converter with circulating current, is proposed for application in four-quadrant DC magnet power supplies. The dual converter is used with circulating current mode for smooth transition of output current polarity. The frequency converter is used at the front of the dual converter to boost the AC line frequency so that the dynamic response can be improved without increasing the ripple content     

An improved soft-switching PWM FB DC/DC converter for reducingconduction losses

An improved soft-switching topology of a full-bridge (FB) pulsewidth-modulated (PWM) DC/DC converter is described. The new topology employs an energy-recovery snubber to minimize a circulating current flowing through the transformer and switching devices. By using an energy-recovery snubber instead of adding a tapped inductor and a saturable reactor to reduce RMS current stress, the converter achieves zero-current switching (ZCS) for the right leg due to the minimized circulating current and achieves zero-voltage switching (ZVS) for the left leg due to the reflected output current during the interval of left leg transition. Both analysis and experiments are performed to verify the proposed topology by implementing a 7 kW (120 VDC, 58 A) 30 kHz insulated gate bipolar transistor (IGBT) based experimental circuit     

An automatic load-adaptive switching frequency selection technique for improving the light-load efficiency of a buck converter

A load-adaptive automatic switching frequency selection scheme is proposed to improve the power efficiency of a switching buck converter at light load condition. The buck converter operates in the continuous-conduction mode for heavy loading and the switching frequency is fixed at its maximum value. For light loading, the buck converter operates in the discontinuous-conduction mode and its switching frequency is automatically selected among a pre-defined set of frequencies according to the amount of the load current. The load current can be sensed indirectly by monitoring the on-time of power transistor because it is a function of the load current. With the proposed load-adaptive automatic switching frequency selection circuit, the power efficiency of a buck converter implemented in a 0.35-μm 2P4M BCDMOS technology is improved by 24.0-% when the load current load is 10-mA.     

Analysis of stepwise charging limits and its implementation for efficiency improvement in switched capacitor DC–DC converters

In this work we analysed the stepwise charging technique to find the limits from which it is beneficial in terms of load capacitance and charge–discharge frequency. We included in the analysis practical limitations such as the consumption of auxiliary logic needed to implement the technique and the minimum size of auxiliary switches imposed by the technology. We proposed an ultra-low-power logic block to push these limits and to obtain benefits from this technique in small capacitances. Finally, we proposed to use a stepwise driver in the driving of the gate capacitance of power switches in switched-capacitor (SC) DC–DC converters. We designed and manufactured, in a 130 nm process, a SC DC–DC converter and measured a 29% energy reduction in the gate-drive losses of the converter. This accounts for an improvement of 4% (from 69 to 73%) in the overall converter efficiency.