Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey

Todays digital signal processing (DSP) applications use computationally complex and/or adaptive algorithms and have stringent requirements in terms of speed, size, cost, power consumption, and throughput. Efficient hardware implementation techniques should be employed to meet the requirements of these applications. Run-Time Reconfiguration (RTR) is a promising technique for reducing the hardware required for implementing DSP systems as well as improving the performance, speed and power consumption of these systems. In this survey, we explain different issues in run-time reconfigurable systems and list the implemented systems which support run-time reconfiguration. We also describe different applications of run-time reconfiguration and discuss the improvements achieved by applying run-time reconfiguration.Alireza Shoa received his B.Sc degree in Electrical Engineering from Sharif University of Technology, Tehran, Iran in 2001 and M.A.Sc degree in Electrical Engineering from McMaster University, Hamilton, Canada in 2003. Currently, he is a PhD candidate in Electrical Engineering at McMaster University. His research interests include VLSI circuits for signal processing and communication applications and image and video processing.Shahram Shirani received his B.S. in Electrical Engineering from Isfahan University of Technology, Isfahan, Iran, and M.Sc. in Biomedical Engineering from Amirkabir University of Technology, Tehran, Iran, and Ph.D. in Electrical Engineering from University of British Columbia, Vancouver, Canada, in 1989, 1994 and 2000 respectively. Since 2000 he has been with the department of Electrical and Computer Engineering, McMaster University, where he is an assistant professor. His research interests include image and video compression, multimedia communications, and ultrasonic imaging. He is a member of technical committee of IEEE International Conference on Image Processing (ICIP). He is a licensed professional engineer and a member of Institute of Electrical and Electronics Engineers (IEEE).     

嵌入式可重构系统芯片的硬件验证平台设计

提出一种新的基于嵌入武可重构系统芯片的视频解码方案,采用了软硬件协同验证的方法.设计了相应的硬件验证平台,验证了H.264解码算法在可重构处理器上的可实现性.     

Designing Run-Time Reconfigurable Systems with JHDL

Run-time reconfigurable (RTR) systems are FPGA-based systems that reconfigure FPGAs during execution to alter hardware organization and composition to meet the varying needs of applications as they execute. These systems are difficult to describe with conventional tools (schematic capture, VHDL synthesis, etc.) because most tools assume that the underlying hardware organization is static. JHDL is a Java-based design environment capable of describing, netlisting, simulating and executing complex, dynamic RTR systems. Using conventional Java syntax, users describe hardware structures as objects; as these hardware-object constructors are invoked, JHDL automatically configures hardware circuits onto FPGA hardware, thus directly supporting the dynamic nature of RTR systems with standard language constructs. JHDL also supports codesign of the software and hardware parts of the system; in other words, the entire application can be described in a single piece of Java code that can be co-simulated/co-executed with the FPGA hardware. To date, RTR design with JHDL has focused on the development of automated target recognition (ATR) systems, and working systems described in JHDL have been demonstrated.     

Run-Time Integration of Reconfigurable Video Processing Systems

Embedded systems in field-programmable gate arrays (FPGAs) can be customized and adaptive if assembled from modular components at run time. This paper examines realizing run-time system assembly by extension of platform-based design. Two major challenges are addressed in this paper. First, the design of a reconfigurable platform architecture suitable for run-time system assembly is described. Different systems are constructed by integrating the platform architecture with different modular components, which employ the communication infrastructure supplied by the platform in order to interact. Second, where on-chip communications channels use shared media, we propose techniques for modeling the intermodule communication behavior based on statistical time-division multiplexing. The proposed techniques enable system designers to guarantee that logical communication requirements between the adjunct modules can be satisfied by the infrastructure. An in-depth analysis is presented and then verified with cycle-accurate simulations for an example reconfigurable platform for real-time video applications.     

Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems: The SAFES Perspective

Embedded systems present significant security challenges due to their limited resources and power constraints. This paper focuses on the issues of building secure embedded systems on reconfigurable hardware and proposes a security architecture for embedded systems (SAFES). SAFES leverages the capabilities of reconfigurable hardware to provide efficient and flexible architectural support for security standards and defenses against a range of hardware attacks. The SAFES architecture is based on three main ideas: (1) reconfigurable security primitives; (2) reconfigurable hardware monitors; and (3) a hierarchy of security controllers at the primitive, system and executive level. Results are presented for reconfigurable AES and RC6 security primitives and highlight the value of such an architecture. This paper also emphasizes that reconfigurable hardware is not just a technology for hardware accelerators dedicated to security primitives as has been focused on by most studies but a real solution to provide high-security and high-performance for a system.     

软硬件联合管理实时嵌入式多媒体应用

随着嵌入式处理解决方案复杂性和普及度的提高,软件工程师发现需要将多媒体算法从基于PC系统(带有足够大存储器)的概念验证移植到嵌入式系统,而资源管理对满足性能要求是非常必要的.理想情况下,他们希望在不增加其"舒适"的编程模式的复杂程度情况下,获得尽可能好的性能.图1描述了软件工程师们在功耗、存储器分配和性能方面面临的挑战.     

Hardware/Software Co-Design of Run-Time Schedulers for Real-Time Systems

Wepresent the Serra Run-Time Scheduler Synthesis and AnalysisTool which automatically generates a run-time scheduler froma heterogeneous system-level specification in both Verilog HDLand C. Part of the run-time scheduler is implemented in hardware,which allows the scheduler to be predictable in being able tomeet hard real-time constraints, while part is implemented insoftware, thus supporting features typical of software schedulers. Serra's real-time analysis generates a priority assignment forthe software tasks in the mixed hardware-software system. Thetasks in hardware and software have precedence constraints, resourceconstraints, relative timing constraints, and a rate constraint.A heuristic scheduling algorithm assigns the static prioritiessuch that a hard real-time rate constraint can be predictablymet. Serra supports the specification of critical regions insoftware, thus providing the same functionality as semaphores.We describe the task control/data-flow extraction,synthesis of the control portion of the run-time scheduler inhardware, real-time analysis and priority scheduler template.We also show how our approach fits into an overall tool flowand target architecture. Finally, we conclude with a sample applicationof the novel run-time scheduler synthesis and analysis tool toa robotics design example.     

Design-Space Exploration for Block-Processing Based Temporal Partitioning of Run-Time Reconfigurable Systems

The reconfiguration capability of modern FPGA devices can be utilized to execute an application by partitioning it into multiple segments such that each segment is executed one after the other on the device. This division of an application into multiple reconfigurable segments is called temporal partitioning. We present an automated temporal partitioning technique for acyclic behavior level task graphs. To be effective, any behavior-level partitioning method should ensure that each temporal partition meets the underlying resource constraints. For this, a knowledge of the implementation cost of each task on the hardware should be known. Since multiple implementations of a task that differ in area and delay are possible, we perform design-space exploration to choose the best implementation of a task from among the available implementations.To overcome the high reconfiguration overhead of the current day FPGA devices, we propose integration of the temporal partitioning and design space exploration methodology with block-processing. Block-processing is used to process multiple blocks of data on each temporal partition so as to amortize the reconfiguration time. We focus on applications that can be represented as task graphs that have to be executed many times over a large set of input data. We have integrated block-processing in the temporal partitioning framework so that it also influences the design point selection for each task. However, this does not exclude usage of our system for designs for which block-processing is not possible. For both block-processing and non block-processing designs our algorithm selects the best possible design point to minimize the execution time of the design.We present an ILP-based methodology for the integrated temporal partitioning, design space exploration and block-processing technique that is solved to optimality for small sized design problems and in an iterative constraint satisfaction approach for large sized design problems. We demonstrate with extensive experimental results for the Discrete Cosine Transform (DCT) and random graphs the validity of our approach.     

Medium-Grain Cells for Reconfigurable DSP Hardware

Reconfigurable hardware contains an array of programmable cells and interconnection structures. Field-programmable gate arrays use fine-grain cells that implement simple logic functions. Some proposed reconfigurable architectures for digital signal processing (DSP) use coarse-grain cells that perform 16-b or 32-b operations. A third alternative is to use medium-grain cells with a word length of 4 or 8 b. This approach combines high flexibility with inherent support for binary arithmetic such as multiplication. This paper presents two medium-grain cells for reconfigurable DSP hardware. Both cells contain an array of small lookup tables, or ldquoelementsrdquo, that can assume two structures. In memory mode, the elements act as a random-access memory. In mathematics mode, the elements implement 4-b arithmetic operations. The first design uses a matrix of 4 times 4 elements and operates in bit-parallel fashion. The second design uses an array of five elements and computes arithmetic functions in bit-serial fashion. Layout simulations in 180-nm CMOS indicate that the parallel cell operates at 267 MHz, whereas the serial cell runs at 167 MHz. However, the parallel design requires over twice the area. The proposed medium-grain cells provide the performance and flexibility needed to implement DSP. To evaluate the designs, the paper estimates the execution time and resource utilization for common benchmarks such as the fast Fourier transform. The architecture model used in this analysis combines the cells with a pipelined hierarchical interconnection network. The end results show great promise compared to other devices, including field-programmable gate arrays.     

Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Reconfigurable System

This paper presents performance improvements and energy savings from mapping real-world benchmarks on an embedded single-chip platform that includes coarse-grained reconfigurable logic with a microprocessor. The reconfigurable hardware is a 2-D array of processing elements connected with a mesh-like network. Analytical results derived from mapping seven real-life digital signal processing applications, with the aid of an automated design flow, on six different instances of the system architecture are presented. Significant overall application speedups relative to an all-software solution, ranging from 1.81 to 3.99 are reported being close to theoretical speedup bounds. Additionally, the energy savings range from 43% to 71%. Finally, a comparison with a system coupling a microprocessor with a very long instruction word core shows that the microprocessor/coarse-grained reconfigurable array platform is more efficient in terms of performance and energy consumption.     

System-Level Energy-Delay Exploration for Multimedia Applications on Embedded Cores with Hardware Cache

Program transformations are a powerful way of optimizing given applications for lower power and higher performance. In this paper, we explore avenues for power reduction by program transformations using the real-time constraints. In the sequel, we discuss the effects of our methodology, for optimization of power, on cache related performance aspects. Our target applications are in the real-time multimedia applications domain implemented on programmable multimedia or DSP processors. The effectiveness of our approach in obtaining a low power implementation and real-time performance is illustrated on three real-life applications, viz. a MPEG-2 decoder, a QSDPCM video codec and a Voicecoder application. Our experimental results indeed show that we are able to obtain lower power and still achieve a real-time performance.     

Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors

Embedded system security is often compromised when "trusted" software is subverted to result in unintended behavior, such as leakage of sensitive data or execution of malicious code. Several countermeasures have been proposed in the literature to counteract these intrusions. A common underlying theme in most of them is to define security policies at the system level in an application-independent manner and check for security violations either statically or at run time. In this paper, we present a methodology that addresses this issue from a different perspective. It defines correct execution as synonymous with the way the program was intended to run and employs a dedicated hardware monitor to detect and prevent unintended program behavior. Specifically, we extract properties of an embedded program through static program analysis and use them as the bases for enforcing permissible program behavior at run time. The processor architecture is augmented with a hardware monitor that observes the program's dynamic execution trace, checks whether it falls within the allowed program behavior, and flags any deviations from expected behavior to trigger appropriate response mechanisms. We present properties that capture permissible program behavior at different levels of granularity, namely inter-procedural control flow, intra-procedural control flow, and instruction-stream integrity. We outline a systematic methodology to design application-specific hardware monitors for any given embedded program. Hardware implementations using a commercial design flow, and cycle-accurate performance simulations indicate that the proposed technique can thwart several common software and physical attacks, facilitating secure program execution with minimal overheads     

Real-Time Speaker Verification System Implemented on Reconfigurable Hardware

Nowadays, biometrics is considered as a promising solution in the market of security and personal verification. Applications such as financial transactions, law enforcement or network management security are already benefitting from this technology. Among the different biometric modalities, speaker verification represents an accurate and efficient way of authenticating a person’s identity by analyzing his/her voice. This identification method is especially suitable in real-life scenarios or when a remote recognition over the phone is required. The processing of a signal of voice, in order to extract its unique features, that allows distinguishing an individual to confirm or deny his/her identity is, usually, a process characterized by a high computational cost. This complexity imposes that many systems, based on microprocessor clocked at hundreds of MHz, are unable to process samples of voice in real-time. This drawback has an important effect, since in general, the response time needed by the biometric system affects its acceptability by users. The design based on FPGA (Field Programmable Gate Arrays) is a suited way to implement systems that require a high computational capability and the resolution of algorithms in real-time. Besides, these devices allow the design of complex digital systems with outstanding performance in terms of execution time. This paper presents the implementation of a MFCC (Mel-Frequency Cepstrum Coefficients)—SVM (Support Vector Machine) speaker verification system based on a low-cost FPGA. Experimental results show that our system is able to verify a person’s identity as fast as a high-performance microprocessor based on a Pentium IV personal computer.     

一种适用于空间飞行器的可重构信息处理平台硬件设计

在我国空间通信技术取得巨大发展的今天,对空间飞行器电子设备功能可重构、可升级、运行代码可更换的需求越来越多。分析了空间辐射效应对高性能数字信号处理器（DSP）和SRAM型FPGA的影响,提出了一种适用于空间飞行器上的可重构信息处理平台的硬件设计方法,具有可重构、可在线升级运行代码的特点。该硬件架构计由高性能DSP和高可靠性的反熔丝FPGA为主要组成,提出了这种架构对抗空间单粒子效应的方法。该电路设计方法可以为空间飞行器通信设备的设计提供参考。     

Towards Software Defined Radios Using Coarse-Grained Reconfigurable Hardware

Mobile wireless terminals tend to become multimode wireless communication devices. Furthermore, these devices become adaptive. Heterogeneous reconfigurable hardware provides the flexibility, performance, and efficiency to enable the implementation of these devices. The implementation of a wideband code division multiple access and an orthogonal frequency division multiplexing receiver using the same coarse-grained reconfigurable MONTIUM tile processor is discussed. Besides the baseband processing part of the receiver, the same reconfigurable processor has also been used to implement Viterbi and Turbo channel decoders.     

Reconfigurable Component-based Middleware for Networked Embedded Systems

Next generation embedded systems will be composed of large numbers of heterogeneous devices. These will typically be resource-constrained (such as sensor motes), will use different operating systems, and will be connected through different types of network interfaces. Additionally, they may be mobile and/or form ad-hoc networks with their peers, and will need to be adaptive to changing conditions based on context-awareness. Our focus in this paper is on the provision of a middleware framework for such system environments. Our approach is based on a small and efficient ‘middleware kernel’ which supports highly modularised and customisable component-based middleware services that can be tailored for specific embedded environments, and are runtime reconfigurable to support adaptivity. These services are primarily communications-related but also address a range of other concerns including service discovery and logical mobility. In the paper we provide an overview of our approach, focusing in detail on both the middleware kernel and the services. We also discuss an application scenario in which we are currently applying and evaluating our middleware approach.

可重构硬件芯片级故障定位与自主修复方法

 外部集中控制的可重构硬件容错系统,其重构控制算法复杂、重构时间开销大,且存在单点失效问题.本文研究芯片级分布式在线自主容错技术,提出了能够实现芯片级自修复的新型可重构硬件细胞阵列结构,阐述了互连资源的在线故障定位和自主修复方法.设计了功能细胞电路和容错开关块电路,采用分段定位法检测互连资源中多路器故障和连线开路故障,通过重配置布线和线移位操作分别实现多路器与连线故障自修复.以4位串并乘法器电路为例进行实验验证,分析了容错设计的硬件开销与时间开销,实验结果表明新方案的容错时间短、资源利用率高.     

Hardware Supported Task Scheduling on Dynamically Reconfigurable SoC Architectures

Dynamically reconfigurable system-on-a-chip (RSoC) technology features embedded microprocessors that are dispersed on the same die with significant amounts of programmable logic fabric. In this paper, we present a strategy to solve the recently emerging problem of how to utilize the flexible but still limited RSoC resources in an effective manner for a multi-task application. The major contribution of this paper is the development of a dynamic task scheduling algorithm that can be implemented in fixed or reconfigurable hardware that will perform the online scheduling of task systems onto the RSoC type architecture. The results from extensive simulations demonstrate the benefits of the proposed dynamic scheduling approach as compared with that of other static scheduling techniques taken from the technical literature.      

模拟型演化硬件中可重构器件的比较研究

演化硬件的研究者受困于满足可演化要求的灵活可重构硬件平台的匮乏.一方面,虽然现有商用可重构平台多数具有动态可局部重构能力,但是其设计目的不是用来研究演化硬件的.另外一方面,用户定制的面向演化硬件研究的芯片没有商用化,而且也不太可能在最近走向商用市场.本文研究了两类用来进行模拟演化硬件研究的可重构器件:商用的现场可编程模拟阵列和用户定制的现场可编程三极管阵列.通过比较研究,作者认为在FPTA类定制用于演化的可重构平台商用化之前,在FPAA平台上开展EHW的研究是有意义的,因为FPAA已经具有充分灵活的重构接口和充足的可重配置资源.     

一种面向流应用加速的可重构协处理器

以图形处理、数字信号处理等为代表的流应用,对微处理器提出了高并行度、高性能和高带宽的要求。针对流应用加速的流处理器体系架构得到了广泛研究。流体系结构大多集成大量的功能单元、开发多层次并行和存储来加速流应用,但同时增加了系统功耗和芯片面积。分析和比较了近年来主流的流处理器架构,提出了一种用于流应用加速的可重构协处理器。该协处理器针对流应用特点,实现了数据级和指令级并行,并集成了多个可以动态配置的运算单元,可动态配置其运算类型和数据类型,提升系统灵活性,降低芯片面积。针对典型算法,该处理器实现了更高的加速比,综合后延时为9.74 ns,功耗为63.69 mW。