Optimum scheduling and memory management in input queued switches with finite buffer space

The goal of this paper is to design optimal scheduling and memory management so as to minimize packet loss in input queued switches with finite input buffers. The contribution is to obtain closed-form optimal strategies that minimize packet loss in 2/spl times/2 switches with equal arrival rates for all streams. For arbitrary arrival rates, the contribution is to identify certain characteristics of the optimal strategy, and use these characteristics to design a near-optimal heuristic. A lower bound for the cost associated with packet loss for N/spl times/N switches is obtained. This lower bound is used to design a heuristic which attains near-minimum packet loss in N/spl times/N switches with arbitrary N. These policies reduce packet loss by about 25% as compared to the optimal strategy for the infinite buffer case. The framework and the policies proposed here apply to buffer-constrained wireless networks as well.     

Optimal pricing for multiple services in telecommunications networks offering quality-of-service guarantees

We consider pricing for multiple services offered over a single telecommunications network. Each service has quality-of-service (QoS) requirements that are guaranteed to users. Service classes may be defined by the type of service, such as voice, video, or data, as well as the origin and destination of the connection provided to the user. We formulate the optimal pricing problem as a nonlinear integer expected revenue optimization problem. We simultaneously solve for prices and the resource allocations necessary to provide connections with guaranteed QoS. We derive optimality conditions and a solution method for this class of problems, and apply to a realistic model of a multiservice communications network.     

On the behavior of PHM distributed schedulers for input buffered packet switches

iSLIP and parallel hierarchical matching (PHM) are distributed maximal size matching schedulers for input-buffered switches. Previous research has analyzed the hardware cost of those schedulers and their performance after a small number of iterations. In this paper, we formulate an upper bound for the number of iterations required by PHM to converge. Then, we compare the number of iterations required by iSLIP and PHM to achieve a maximal throughput under uniform Bernoulli traffic, by means of simulation. Finally, we obtain the corresponding delay performances, which are similar. The results suggest that PHM has both the advantages of previous hierarchical matching algorithms (low hardware complexity) and iSLIP (low number of iterations).     

Optimum architecture for input queuing ATM switches

An input queueing ATM switch architecture employing the contention resolution called 'scheduling algorithm' is described. A high efficiency of over 90% can be achieved without any considerable increase in the amount of hardware or contention control speed.<>     

Self-firing cell scheduler for input queueing ATM switches

The authors propose a simple cell scheduler for input queueing ATM switches. The proposed self-firing cell scheduler consists of N² processing elements connected by a two dimensional torus network, where each processing element can determine the diagonal by itself in a distributed manner. It allows a simple implementation for high speed ATM switches     

Two-dimensional round-robin schedulers for packet switches withmultiple input queues

Presents a new scheduler, the two-dimensional round-robin (2DRR) scheduler, that provides high throughput and fair access in a packet switch that uses multiple input queues. We consider an architecture in which each input port maintains a separate queue for each output. In an N×N switch, our scheduler determines which of the queues in the total of N² input queues are served during each time slot. We demonstrate the fairness properties of the 2DRR scheduler and compare its performance with that of the input and output queueing configurations, showing that our scheme achieves the same saturation throughput as output queueing. The 2DRR scheduler can be implemented using simple logic components, thereby allowing a very high-speed implementation     

Parallel contention resolution control for input queueing ATM switches

Input queueing ATM switches requiring fast contentional resolution control have been negatively affected by long turn-around time (TAT) due to the distance between an input port controller and a centralised contention controller. A parallel contention resolution control for input queueing switches is presented. The proposed control allows a TAT of more than one cell slot, resulting in the potential development of a centralised contention controller for an ATM switch with an aggregate capacity of 1 Tbit/s.<>     

Throughput analysis for multicast switches with multiple input queues

This letter analyzes the saturated throughput for multicast switches with multiple input queues per input port. Under the assumptions of a Poisson uniform traffic model and random packet scheduling policy, we derive the multicast switch saturated throughput under different fanouts. To verify the analysis, extensive simulations are conducted with different switch sizes and fanouts. It is shown that the theoretical analysis and the simulation results have a discrepancy less than 1.9%. Results from this letter can be used as a guidance to design the optimal queuing for multicast switches.     

Analysis of input and output queueing for nonblocking ATM switches

A switch model for ATM networks is analyzed. Its interconnection network is internally nonblocking and is provided with dedicated input and output queues, one per switch inlet and one per switch outlet. The switch operates with an internal speed-up: more than one packet per slot can be transferred from the head-of-line positions of the input queues to each output queue by the interconnection network. Two different operation modes are considered for the interaction between input and output queues: backpressure mode and queue loss mode. The analytical model developed for the evaluation of the switch performance under random traffic assumes an infinite size for the switch, arbitrary values for input and output queue size, as well as for the speed-up factor. Switch throughput, packet delay and loss performance are evaluated and the analytical model accuracy is assessed using computer simulation results     

On the stability of local scheduling policies in networks of packet switches with input queues

A significant research effort has been devoted to the design of simple and efficient scheduling policies for input queued (IQ) and combined input-output queued (CIOQ) packet switches. As a result, a number of switch control algorithms have been proposed. Among these, scheduling policies based on maximum weight matching (MWM) were identified as optimal, in the sense that they were proved to achieve 100% throughput under any admissible arrival process satisfying the strong law of large number. On the contrary, it has been shown that the usual MWM policies fail to guarantee 100% throughput in networks of interconnected IQ/CIOQ switches. Hence, new policies suited for networks of interconnected switches were proposed and proved to achieve 100% throughput. All of these new policies require coordination and cooperation among different switches. We identify scheduling policies that require no coordination among switches (and are, thus, said to be local), and that guarantee 100% throughput in a network of IQ/CIOQ switches. The only assumptions on the input traffic pattern are that it is stationary, satisfies the strong law of large numbers and does not oversubscribe any link in the network.     

RPA: a flexible scheduling algorithm for input buffered switches

This paper presents and evaluates a quasi-optimal scheduling algorithm for input buffered cell-based switches, named reservation with preemption and acknowledgment (RPA). RPA is based on reservation rounds where the switch input ports indicate their most urgent data transfer needs, possibly overwriting less urgent requests by other input ports, and an acknowledgment round to allow input ports to determine what data they can actually transfer toward the desired switch output port. RPA must be executed during every cell time to determine which cells can be transferred during the following cell time. RPA is shown to be as simple as the simplest proposals of input queuing scheduling, efficient in the sense that no admissible traffic pattern was found under which RPA shows throughput limitations, and flexible, allowing the support of packet-mode operations and different traffic classes with either strict priority discipline or bandwidth guarantee requirements. The effectiveness of RPA is assessed with detailed simulations in uniform as well as unbalanced traffic conditions and its performance is compared with output queuing switches and the optimal maximum weighted matching (MWM) algorithm for input-buffered switches. A bound on the performance difference between the heuristic weight matching adopted in RPA and MWM is analytically computed     

FIRM: high-speed distributed scheduling for ATM switches withmultiple input queues

A new distributed scheduling algorithm for advanced input queueing switch architectures called FIRM is introduced. FIRM provides improved performance characteristics at high load compared to the most efficient alternative, improved fairness, and tighter service guarantees     

An efficient contention resolution algorithm for input queuing atm cross-connect switches

This paper describes an efficient contention resolution algorithm and its distributed implementation for large capacity input queuing cross-connect switches, which will establish virtual paths in future broadband ATM networks. The algorithm dynamically allocates sending time to cells held in input queues when no contention is indicated in the designated output ports. An expression for the mean delay and the cell loss probability for random traffic are derived through an approximate analysis. Input cells are served on a first-come, first-served basis as conventional contention resolution algorithms whose throughput saturates at 58 per cent because of head of line blocking in input queues. The proposed algorithm achieves a maximum throughput of 76 per cent.     

Analysis of nonblocking ATM switches with multiple input queues

An analytical model for the performance analysis of a multiple input queued asynchronous transfer mode (ATM) switch is presented. The interconnection network of the ATM switch is internally nonblocking and each input port maintains a separate queue of cells for each output port. The switch uses parallel iterative matching (PIM) to find the maximal matching between the input and output ports of the switch. A closed-form solution for the maximum throughput of the switch under saturated conditions is derived. It is found that the maximum throughput of the switch exceeds 99% with just four iterations of the PIM algorithm. Using the tagged input queue approach, an analytical model for evaluating the switch performance under an independent identically distributed Bernoulli traffic with the cell destinations uniformly distributed over all output ports is developed. The switch throughput, mean cell delay, and cell loss probability are computed from the analytical model. The accuracy of the analytical model is verified using simulation     

Analysis of packet switches with input and output queuing

A single-stage nonblocking N*N packet switch with both output and input queuing is considered. The limited queuing at the output ports resolves output port contention partially. Overflow at the output queues is prevented by a backpressure mechanism and additional queuing at the input ports. The impact of the backpressure effect on the switch performance for arbitrary output buffer sizes and for N to infinity is studied. Two different switch models are considered: an asynchronous model with Poisson arrivals and a synchronous model with Bernoulli arrivals. The investigation is based on the average delay and the maximum throughput of the switch. Closed-form expressions for these performance measures are derived for operation with fixed size packets. The results demonstrate that a modest amount of output queuing, in conjunction with appropriate switch speedup, provides significant delay and throughput improvements over pure input queuing. The maximum throughput is the same for the synchronous and the asynchronous switch model, although the delay is different.<>     

Throughput analysis for input-buffered ATM switches with multipleFIFO queues per input port

Using two different packet scheduling policies, the maximum throughputs of an input-buffered ATM switch with m-FIFO queues per input port are derived when the switch size is large     

On the speedup required for work-conserving crossbar switches

This paper describes the architecture for a work-conserving server using a combined I/O-buffered crossbar switch. The switch employs a novel algorithm based on output occupancy, the lowest occupancy output first algorithm (LOOFA), and a speedup of only two. A work-conserving switch provides the same throughput performance as an output-buffered switch. The work-conserving property of the switch is independent of the switch size and input traffic pattern. We also present a suite of algorithms that can be used in combination with LOOFA. These algorithms determine the fairness and delay properties of the switch. We also describe a mechanism to provide delay bounds for real-time traffic using LOOFA. These delay bounds are achievable without requiring output-buffered switch emulation     

RPA: a simple, efficient, and flexible policy for input bufferedATM switches

Reservation with Preemption and Acknowledgment (RPA) is a simple, efficient, and flexible queuing discipline and scheduling algorithm for input buffered asynchronous transfer-mode (ATM) switches. This letter describes the RPA algorithms, and presents simulation results to demonstrate the effectiveness of the proposed approach     

Head of the line arbitration of packet switches with combined input and output queueing

A single-stage non-blocking N × N packet switch is considered. Data units may be stored before switching at the inputs as well as after switching at the outputs. Some output buffering capacity is intended to achieve high throughput, whereas an additional input buffering capacity keeps losses due to input-buffer overflow reasonably low. The paper studies the impact on performance of the head of the line arbitration policy, i.e. the sequence which is used to transfer data units from the heads of input queues to each output queue. The investigation is based on two performance measures: the average delay and the maximum throughput of the switch. Closed-form expressions for the FCFS, LCFS and the ROS policies are obtained. The result of the average delay with the FCFS policy leads to a lower bound, and that with the LCFS policy to an upper bound for the average delay, corresponding to an arbitrary symmetric policy which does not use information related to the state of the input queues. It is shown that the maximum throughput does not depend on the head of the line arbitration policy. It depends only on the output-buffer size and the packet-size distribution. The cases of fixed and exponentially distributed packet sizes are studied. The effects of asymmetric policies which result in different behaviours of some of the input queues is also considered.